CN110995245A - Input circuit - Google Patents
Input circuit Download PDFInfo
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- CN110995245A CN110995245A CN201911375311.5A CN201911375311A CN110995245A CN 110995245 A CN110995245 A CN 110995245A CN 201911375311 A CN201911375311 A CN 201911375311A CN 110995245 A CN110995245 A CN 110995245A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
Abstract
An input circuit comprises an electrostatic protection module, a self-biased comparator module, a voltage stabilizing circuit module and an output drive circuit module, wherein the electrostatic protection module is used for carrying out electrostatic protection on an input high-speed signal and sending the high-speed signal subjected to electrostatic protection to the self-biased comparator module; the self-bias comparator module compares the high-speed signal from the electrostatic protection module with a threshold level and sends a comparison result signal to the voltage stabilizing circuit module; and the voltage stabilizing circuit module is used for stabilizing the voltage of the comparison result signal output by the self-bias comparator module to keep the comparison result signal stable, and sending the comparison result signal after voltage stabilization to the output driving circuit module for output. The input circuit can automatically adjust the input level of the self-biased comparator, reduce consumption, improve integration level and reduce cost.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to an input circuit.
Background
The input circuit is a key part of the chip interface and is a level of determining the performance of the chip. The indexes of speed, area, power consumption, jitter and the like determine the key technical indexes of the chip. In some high-speed application systems, due to the attenuation of the amplitude of a high-speed signal in the transmission process, the input signal cannot be normally distinguished, so that the chip cannot normally work.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide an input circuit which can automatically adjust the input level of a self-biased comparator, reduce consumption, improve integration level and reduce cost.
In order to achieve the above object, the present invention provides an input circuit, which comprises an electrostatic protection module, a self-biased comparator module, a voltage regulator circuit module, and an output driver circuit module, wherein,
the electrostatic protection module is used for performing electrostatic protection on the input high-speed signal and sending the high-speed signal subjected to electrostatic protection to the self-bias comparator module;
the self-bias comparator module compares the high-speed signal from the electrostatic protection module with a threshold level and sends a comparison result signal to the voltage stabilizing circuit module;
and the voltage stabilizing circuit module is used for stabilizing the voltage of the comparison result signal output by the self-bias comparator module to keep the comparison result signal stable, and sending the comparison result signal after voltage stabilization to the output driving circuit module for output.
Further, the electrostatic protection module includes a first transistor, a second transistor, and first to third resistors, wherein,
one end of the first resistor is connected with a power supply, the other end of the first resistor is connected with the grid electrode of the first transistor, and the source electrode of the first transistor is connected with the power supply;
one end of the second resistor is grounded, the other end of the second resistor is connected with the grid electrode of the second transistor, and the source electrode of the second transistor is grounded;
one end of the third resistor is connected with the drain electrode of the first transistor, the drain electrode of the second transistor and the circuit input end, and the other end of the third resistor is connected with the self-bias comparator module.
Further, the self-biased comparator module includes, third to seventh transistors, wherein,
the grid electrode of the fifth transistor is connected with the electrostatic protection module;
a source of the fifth transistor is connected with a source of the sixth transistor and a drain of the seventh transistor, a source of the seventh transistor is grounded, a drain of the fifth transistor is connected with a drain of the third transistor, a source of the third transistor and a source of the fourth transistor are connected with a power supply, and a gate of the third transistor and a gate of the fourth transistor are connected with a gate of the seventh transistor;
and the drain electrode of the sixth transistor and the drain electrode of the fourth transistor are connected with the voltage stabilizing circuit module.
Further, the self-biased comparator module further includes a voltage stabilizing unit disposed between the gate of the sixth transistor and ground for stabilizing the threshold voltage;
the voltage stabilizing unit comprises a combination of one or more transistors.
Further, the self-biased comparator module further includes an eighth transistor, a gate of the eighth transistor is connected to a gate of the sixth transistor and the threshold level unit, and a source and a drain of the voltage stabilizing unit are grounded.
Further, the voltage regulator circuit module comprises ninth to fourteenth transistors, wherein,
the grid electrode of the ninth transistor, the grid electrode of the tenth transistor, the grid electrode of the eleventh transistor and the grid electrode of the twelfth transistor are connected with the self-bias comparator module;
the source of the ninth transistor is connected with the power supply, the drain of the ninth transistor is connected with the source of the tenth transistor and the source of the fourteenth transistor, the source of the eleventh transistor is connected with the drain of the twelfth transistor and the source of the thirteenth transistor, the drain of the thirteenth transistor is connected with the power supply, and the drain of the fourteenth transistor is connected with the ground;
and the drain electrode of the tenth transistor and the drain electrode of the eleventh transistor are connected with the grid electrode of the fourteenth transistor and the grid electrode of the thirteenth transistor and the output driving circuit module.
Further, the output driving circuit module includes fifteenth to eighteenth transistors, wherein,
the grid electrode of the fifteenth transistor and the grid electrode of the sixteenth transistor are connected with the output of the voltage stabilizing circuit module;
the source electrode of the fifteenth transistor is connected with a power supply, the drain electrode of the fifteenth transistor and the drain electrode of the sixteenth transistor are connected with the grid electrode of the seventeenth transistor and the grid electrode of the eighteenth transistor, the source electrode of the sixteenth transistor is grounded, the source electrode of the eighteenth transistor is connected with a power supply, and the source electrode of the seventeenth transistor is grounded;
and the drain electrode of the eighteenth transistor and the drain electrode of the seventeenth transistor are connected with the output end of the circuit.
The input circuit of the invention has the following beneficial effects:
1) the input level of the self-bias comparator can be automatically adjusted, so that a high-speed signal attenuated by a large signal can be identified, and the working accuracy of the circuit is ensured.
2) The comparator adopts a self-bias structure, so that the consumption can be reduced, the integration level is improved, and the cost is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of an input circuit connection according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
In the embodiment of the invention, for the application of the FPGA, the 250MHz parallel signal can be called a height signal, and for the transmission of a high-speed interface, the signal of the upper Gbps can be called a high-speed signal, which all need special processing.
Fig. 1 is a schematic diagram of the connection of an input circuit according to the present invention, which will be described in detail with reference to fig. 1.
The input circuit of the invention comprises resistors R1-R3 and transistors M1-M18, which are mainly divided into an electrostatic protection module, a self-bias comparator module, a voltage stabilizing circuit module and an output drive circuit module, wherein,
the electrostatic protection module comprises a first resistor R1, a second resistor R2, a third resistor R3, a first transistor M1 and a second transistor M2, and plays a role IN electrostatic protection when the attenuated high-speed signal enters the input end IN of the input circuit.
Specifically, one end of the first resistor R1 is connected to the power supply, the other end is connected to the gate of the first transistor M1, and the source of the first transistor M1 is connected to the power supply; one end of the second resistor R2 is grounded, the other end is connected to the gate of the second transistor M2, and the source of the second transistor M2 is grounded; the drain of the first transistor M1 and the drain of the second transistor M2 are connected to one end of a third resistor R3, and the other end of the third resistor R3 is connected to a self-biased comparator block.
The self-bias comparator module comprises third to eighth transistors M3 to M8, which are used for forming a self-bias and low-jitter comparator when a signal subjected to electrostatic protection is connected to the grid electrode of the fifth transistor M5, and the third to eighth transistors M3 to M8 are used for comparing the grid voltage of the fifth transistor M5 and the grid voltage of the sixth transistor M6.
Specifically, the gate of the fifth transistor M5 is connected to the esd protection module, the source of the fifth transistor M5 is connected to the source of the sixth transistor M6 and the drain of the seventh transistor M7, and the source of the seventh transistor M7 is grounded; the drain of the fifth transistor M5 is connected with the drain of the third transistor M3, the drain of the sixth transistor M6 is connected with the drain of the fourth transistor M4, the sources of the third transistor M3 and the fourth transistor M4 are connected with the power supply, and the gates of the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are connected together to form a self-biasing structure; the gate of the sixth transistor M6 is connected to the gate of the eighth transistor M8 and the input threshold REF terminal, the drains of the sixth transistor M6 and the fourth transistor M4 are connected to the voltage regulator circuit module, and the source and the drain of the eighth transistor M8 are grounded.
Specifically, since the input circuit is usually connected to the whole input/output guard ring, the power and ground thereof have large disturbance, the eighth transistor M8 is added as a voltage stabilizing transistor and connected to the gate of the sixth transistor M6; the high speed signal is compared to a clean level threshold REF.
Specifically, the eighth transistor M8 may be a transistor or a combination of a plurality of transistors as a voltage regulator.
Specifically, since the high-speed signal is attenuated through the channel transmission, the threshold level REF for comparison should be lower than the high level of the attenuated high-speed signal and higher than the low level of the attenuated high-speed signal by a dc level value.
The voltage stabilizing circuit module comprises ninth to fourteenth transistors M9-M14, wherein the comparison results output are connected to the gates of the ninth to twelfth transistors M9-M12, and the ninth to fourteenth transistors M9-M14 form a voltage stabilizing circuit, so that the output results of the self-bias comparator are kept stable within a certain range.
Specifically, the gates of the ninth to twelfth transistors M9-M12 are connected to the self-biased comparator module, and receive the comparison result from the self-biased comparator module, the source of the ninth transistor M9 is connected to the power supply, the drain of the ninth transistor M14 is connected to the source of the tenth transistor M10, the drain of the tenth transistor M10 is connected to the drain of the eleventh transistor M11, the source of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12, the source of the twelfth transistor M12 is connected to the ground, and the drains of the tenth transistor M10 and the eleventh transistor M11 are connected to the gate of the thirteenth transistor M13 and the gate of the fourteenth transistor M14; the drain of the thirteenth transistor M13 is connected to the power supply, the source is connected to the drain of the twelfth transistor M12, the drain of the fourteenth transistor M14 is connected to the ground, the source is connected to the source of the tenth transistor M10, and the gates of the thirteenth transistor M13 and the fourteenth transistor M14 are connected to the output driving circuit module.
The output driving circuit module comprises fifteenth to eighteenth transistors M15-M18 which are formed by cascading a plurality of inverters and mainly depend on the size of a load driven by the output end OUT and the working frequency of a signal.
Specifically, gates of the fifteenth transistor M15 and the sixteenth transistor M16 are connected to the output of the voltage stabilizing circuit module, a source of the fifteenth transistor M15 is connected to the power supply, a drain of the fifteenth transistor M15 is connected to a drain of the sixteenth transistor M16, a drain of the sixteenth transistor M16 is connected to gates of the seventeenth transistor M17 and the eighteenth transistor M18, a source of the sixteenth transistor M16 is grounded, a source of the eighteenth transistor M18 is connected to the power supply, a drain of the eighteenth transistor M18 and a drain of the seventeenth transistor M17 are connected to the output terminal OUT, and a source of the seventeenth transistor M17 is grounded.
The input circuit of the invention solves the problems of low resolution ratio or wrong resolution ratio caused by the influence of signal attenuation on the amplitude of a high-speed signal in the transmission process.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. An input circuit comprises an electrostatic protection module, a self-bias comparator module, a voltage stabilizing circuit module and an output drive circuit module,
the electrostatic protection module is used for performing electrostatic protection on the input high-speed signal and sending the high-speed signal subjected to electrostatic protection to the self-bias comparator module;
the self-bias comparator module compares the high-speed signal from the electrostatic protection module with a threshold level and sends a comparison result signal to the voltage stabilizing circuit module;
and the voltage stabilizing circuit module is used for stabilizing the voltage of the comparison result signal output by the self-bias comparator module to keep the comparison result signal stable, and sending the comparison result signal after voltage stabilization to the output driving circuit module for output.
2. The input circuit of claim 1, wherein the ESD protection module comprises a first transistor, a second transistor, and first to third resistors, wherein,
one end of the first resistor is connected with a power supply, the other end of the first resistor is connected with the grid electrode of the first transistor, and the source electrode of the first transistor is connected with the power supply;
one end of the second resistor is grounded, the other end of the second resistor is connected with the grid electrode of the second transistor, and the source electrode of the second transistor is grounded;
one end of the third resistor is connected with the drain electrode of the first transistor, the drain electrode of the second transistor and the circuit input end, and the other end of the third resistor is connected with the self-bias comparator module.
3. The input circuit of claim 1, wherein the self-biased comparator block comprises, third through seventh transistors, wherein,
the grid electrode of the fifth transistor is connected with the electrostatic protection module;
a source of the fifth transistor is connected with a source of the sixth transistor and a drain of the seventh transistor, a source of the seventh transistor is grounded, a drain of the fifth transistor is connected with a drain of the third transistor, a source of the third transistor and a source of the fourth transistor are connected with a power supply, and a gate of the third transistor and a gate of the fourth transistor are connected with a gate of the seventh transistor;
and the drain electrode of the sixth transistor and the drain electrode of the fourth transistor are connected with the voltage stabilizing circuit module.
4. The input circuit of claim 3, wherein the self-biased comparator module further comprises a voltage stabilizing unit disposed between the gate of the sixth transistor and ground for stabilizing a threshold voltage;
the voltage stabilizing unit comprises a combination of one or more transistors.
5. The input circuit of claim 3, further comprising an eighth transistor, wherein a gate of the eighth transistor is connected to a gate of the sixth transistor and the threshold level unit, and a source and a drain of the voltage regulator unit are grounded.
6. The input circuit of claim 1, wherein the voltage regulator circuit module includes ninth through fourteenth transistors, wherein,
the grid electrode of the ninth transistor, the grid electrode of the tenth transistor, the grid electrode of the eleventh transistor and the grid electrode of the twelfth transistor are connected with the self-bias comparator module;
the source of the ninth transistor is connected with the power supply, the drain of the ninth transistor is connected with the source of the tenth transistor and the source of the fourteenth transistor, the source of the eleventh transistor is connected with the drain of the twelfth transistor and the source of the thirteenth transistor, the drain of the thirteenth transistor is connected with the power supply, and the drain of the fourteenth transistor is connected with the ground;
and the drain electrode of the tenth transistor and the drain electrode of the eleventh transistor are connected with the grid electrode of the fourteenth transistor and the grid electrode of the thirteenth transistor and the output driving circuit module.
7. An input circuit as claimed in claim 1, wherein said output driver circuit module comprises fifteenth to eighteenth transistors,
the grid electrode of the fifteenth transistor and the grid electrode of the sixteenth transistor are connected with the output of the voltage stabilizing circuit module;
the source electrode of the fifteenth transistor is connected with a power supply, the drain electrode of the fifteenth transistor and the drain electrode of the sixteenth transistor are connected with the grid electrode of the seventeenth transistor and the grid electrode of the eighteenth transistor, the source electrode of the sixteenth transistor is grounded, the source electrode of the eighteenth transistor is connected with a power supply, and the source electrode of the seventeenth transistor is grounded;
and the drain electrode of the eighteenth transistor and the drain electrode of the seventeenth transistor are connected with the output end of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911375311.5A CN110995245A (en) | 2019-12-27 | 2019-12-27 | Input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911375311.5A CN110995245A (en) | 2019-12-27 | 2019-12-27 | Input circuit |
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| CN110995245A true CN110995245A (en) | 2020-04-10 |
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| CN201911375311.5A Pending CN110995245A (en) | 2019-12-27 | 2019-12-27 | Input circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101030575A (en) * | 2006-02-28 | 2007-09-05 | 松下电器产业株式会社 | Semiconductor integrated circuit device |
| CN103066989A (en) * | 2012-12-20 | 2013-04-24 | 西安电子科技大学 | Single power electric level shift circuit with digital filtering function |
| CN105141305A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Level conversion method and device |
| US20190260361A1 (en) * | 2018-02-19 | 2019-08-22 | Texas Instruments Incorporated | Input buffer with low static current consumption |
-
2019
- 2019-12-27 CN CN201911375311.5A patent/CN110995245A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101030575A (en) * | 2006-02-28 | 2007-09-05 | 松下电器产业株式会社 | Semiconductor integrated circuit device |
| CN103066989A (en) * | 2012-12-20 | 2013-04-24 | 西安电子科技大学 | Single power electric level shift circuit with digital filtering function |
| CN105141305A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Level conversion method and device |
| US20190260361A1 (en) * | 2018-02-19 | 2019-08-22 | Texas Instruments Incorporated | Input buffer with low static current consumption |
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Address after: 610200 Chengdu City, Sichuan Province, Chengdu City, the Galactic Road, No. 596 scientific research complex 13 floor Applicant after: Chengdu Huada Jiutian Technology Co.,Ltd. Address before: 610200 Chengdu City, Sichuan Province, Chengdu City, the Galactic Road, No. 596 scientific research complex 13 floor Applicant before: CHENGDU JIUXIN MICRO TECHNOLOGY Co.,Ltd. |
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Application publication date: 20200410 |
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| RJ01 | Rejection of invention patent application after publication |