CN105141305A - Level conversion method and device - Google Patents
Level conversion method and device Download PDFInfo
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- CN105141305A CN105141305A CN201510579584.7A CN201510579584A CN105141305A CN 105141305 A CN105141305 A CN 105141305A CN 201510579584 A CN201510579584 A CN 201510579584A CN 105141305 A CN105141305 A CN 105141305A
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Abstract
The invention relates to a level conversion method and device. The device comprises an input circuit used for receiving input signals from a second power voltage domain; a threshold generation circuit used for generating threshold voltages for distinguishing high and low levels of the input signals; and a self-biased amplifier circuit used for comparing the input signals with the threshold voltages and generating logical values. The level conversion device generate output signals of the first second power voltage domain, which are corresponding to the logic values. According to the invention, the input signals of the different or same power voltage domain are converted into voltage signals required by the inner part of a chip, so that the requirements of low power and wide input voltage range are met.
Description
Technical field
The present invention relates to input and level conversion field, particularly relate to a kind of method and device of level conversion.
Background technology
In the system application of chip, often there is the situation needing to carry out communication between the chip being in different electrical power voltage domain, to realize required systemic-function.When chip needs to receive the control signal from other supply voltage domain, then need the operating voltage by level shifting circuit, external signal operating voltage being converted to chip internal logic.
The detection of the type adopts dual supply voltage system usually, and one of them voltage is identical with external input signal high level voltage, and another voltage is chip operating voltage.Desired signal voltage is obtained after input signal is accessed duplicate supply level translator.
This by using the level conversion mode of dual power supply can cause following comparatively distinct issues: if system does not need dual power supply except this level switch module, then to waste an independent pin and segment chip area.In addition, this conversion method is comparatively large to the restriction of the scope of input voltage, to be difficult to cover under various processes digital signal voltage comparatively widely.
Summary of the invention
The present invention, in order to overcome above-mentioned the deficiencies in the prior art, provides a kind of method and device of level conversion.By the input signal of similar and different supply voltage domain being converted to the voltage signal required for chip internal, thus reach the requirement of low-power consumption and wide input voltage range.
To achieve these goals, on the one hand, the invention provides a kind of device of level conversion, this device comprises: input circuit, for receiving the input signal from second source voltage domain; Threshold generation circuits, for generating the threshold voltage distinguishing input signal low and high level; Self biased amplifier circuit, for input signal and threshold voltage being compared, produces logical value; This level converter produces the output signal of first supply voltage domain corresponding to described logical value.
On the other hand, the invention provides a kind of method of level conversion, the method comprises the following steps: receive the input signal from second source voltage domain; The logical value of input signal is detected by self biased amplifier circuit and threshold generation circuits in the first supply voltage domain; The output signal corresponding to logical value is produced in the first supply voltage domain.
The present invention is operated in wide power voltage territory, and work is got final product under single-power voltage powers environment, by the input signal of similar and different supply voltage domain by automatic biasing structural design to reach the object not needing additional bias circuit, and the comparative threshold voltage of setting signal low and high level adapts to wider input voltage range, improve the flexibility of application.By adopting the design of low-power consumption and deburring, by the power consumption control of inner modules in extremely low level, and then ensureing lower overall power, improve the accuracy of signal.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of the first level converter that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the second level converter that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the third level converter that Fig. 3 provides for the embodiment of the present invention;
The method flow schematic diagram of a kind of level conversion that Fig. 4 provides for the embodiment of the present invention;
The structural representation of a kind of threshold generation circuits that Fig. 5 provides for the embodiment of the present invention;
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
The structural representation of the first level converter that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, this level converter comprises input circuit 101, self biased amplifier 102, threshold generation circuits 103.
Wherein, input circuit 101 is for receiving the input signal from identical or different supply voltage domain, and its input is input node, and output is connected to the positive input of self biased amplifier circuit 102.Self biased amplifier circuit 102 comprises positive input, negative input and output, threshold voltage for input signal and threshold generation circuits 103 being generated compares, and threshold value comparative result is exported by output, its positive input is connected to the output of input circuit 101, and negative input is connected to the output of threshold generation circuits 103.Threshold generation circuits 103 generates the threshold voltage for distinguishing input signal low and high level, and its output is connected to the negative input of self biased amplifier circuit 102.
When the chip chamber of identical or different supply voltage domain needs to carry out communication, the input signal of identical or different supply voltage domain and threshold voltage compare the logical value determining input signal, and Output rusults is converted to the logical signal corresponding to supply voltage, after suitable threshold voltage is set realizes detecting the input signal in identical or different Width funtion territory, by the output of self biased amplifier circuit 102, comparative result is exported.
The structural representation of the second level converter that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, this level converter comprises level converter, inverting amplifier 104, Si Mite inverter circuit 105 and the output buffer 106 on the first single supply low-power consumption automatic biasing sheet.
Wherein, inverting amplifier 104 exports after the output signal of threshold value comparative result being amplified, make output signal be easier to rear class process, its input is connected to the output of self biased amplifier circuit 102, and output is connected to the input of schmitt inverter circuit 105.The false triggering of schmitt inverter circuit 105 for preventing comparative result from exporting, its input is connected to the output of inverting amplifier 104, and its output is connected to the input of output buffer 106.Output buffer 106 exports the driving force of external signal to for improving, its input is connected to the output of schmitt inverter circuit 105, and its output is connected to output node.
When the chip chamber of identical or different supply voltage domain needs to carry out communication, by the level converter on the first single supply low-power consumption automatic biasing deburring sheet, export after the input signal of identical or different supply voltage domain is converted to the logical signal corresponding to supply voltage, output signal is carried out amplification process by inverting amplifier 104, and together filter out the burr signal that may produce false triggering in output signal with Si Mite inverter circuit 105, improve the driving force of output signal finally by output buffer 106 after, by the output signal in output node output supply voltage territory.
The present invention is operated in wide power voltage territory, and work is got final product under single-power voltage powers environment, by automatic biasing structural design to reach the object not needing additional bias circuit, and the comparative threshold voltage of setting signal low and high level adapts to wider input voltage range, improve the flexibility of application.By adopting the design of low-power consumption and deburring, by the power consumption control of inner modules in extremely low level, and then ensureing lower overall power, improve the accuracy of signal.
The structural representation of the third level converter that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, this level converter comprises input circuit 101, self biased amplifier circuit 102, threshold generation circuits 103/D1, inverting amplifier 104, schmitt inverter circuit 105 and output buffer 106/D3.
Input circuit 101 comprises a pull-up resistor Rpu and protective resistance Re, for receiving the input signal from identical or different supply voltage domain.Wherein, pull-up resistor Rpu is biased for providing the acquiescence of input, and its one end is connected to power supply, and the other end is connected to input node, and its resistance is infinitely great; Input circuit 101 also can adopt pull down resistor to be communicated with input node and ground according to design requirement; Protective resistance Re is used for providing protection to the input of self biased amplifier circuit 102, and its one end is connected to input node, and the other end is connected to the input of self biased amplifier circuit 102.
Threshold generation circuits 103/D1 is for generation of the threshold voltage distinguishing input signal low and high level; There is decoupling capacitance Cp1 and Cn1 being connected to VDD-to-VSS respectively in the output of threshold generation circuits 103/D1, produces the threshold voltage of circuit 103/D1 output for stable threshold; This decoupling filter electric capacity can have multiple way of realization, includes but not limited to variable capacitance, MOM capacitor, MIM capacitor and active device etc.
The active electric current mirror load that self biased amplifier circuit 102 comprises input stage that two PMOS form, NMOS tube is formed, PMOS form the current source of common gate; In input stage, the grid of the first PMOS is positive input, and the grid of the second PMOS is negative input; The source electrode of common gate current source is connected to supply voltage, drain electrode is connected to the source electrode of input stage, the grid of grid and the load of active electric current mirror is connected to the drain electrode of the first PMOS in input stage jointly, two drain electrodes of active electric current mirror load are connected to two drain electrodes of input stage respectively, this structure forms inner automatic biasing structure, to reach the object not needing additional bias circuit, reduce branch road and reduce power consumption.
Self biased amplifier circuit 102 is for comparing the input signal of identical or different voltage domain and threshold voltage, determine the logical value of input signal, judge whether comparative result is pressed with corresponding logical signal to power electric, if there is no corresponding logical signal, comparative result to be converted to and to be pressed with corresponding logical signal to power electric by the threshold voltage then exported by changing threshold voltage generation circuit 103, is exported by comparative result by the output of this partial circuit.
Wherein, the input stage of two PMOS formations forms input stage by MP1 and MP2, and the grid of MP1 is positive input, and the grid of MP2 is negative input.The NMOS tube MN1-MN2n that the active electric current mirror load that NMOS tube is formed is less than 1 by breadth length ratio is formed, and wherein the grid of all NMOS tube is all connected to the drain electrode of input PMOS MP1.The drain electrode of NMOS tube MN1 is connected to the drain electrode of input PMOS MP1, and the source electrode of MN1 is connected with the drain electrode of MN3, and the source electrode of MN3 is connected with the drain electrode of MN5, and by that analogy, the source electrode of MN2n-1 is connected to ground; The drain electrode of NMOS tube MN2 is connected to the drain electrode of input PMOS MP2, and the source electrode of MN2 is connected with the drain electrode of MN4, and the source electrode of MN4 is connected with the drain electrode of MN6, and by that analogy, the source electrode of MN2n is connected to ground.The PMOS MP3-MPn that the current source that PMOS is formed is less than 1 by breadth length ratio is formed, and wherein the grid of all PMOS is connected to the drain electrode of input PMOS MP1.The drain electrode of PMOS MP3 is connected to the source electrode of input PMOS MP1 and PM2, the source electrode of MP3 is connected with the drain electrode of MP4, and the source electrode of MP4 is connected with the drain electrode of MP5, by that analogy, the source electrode of MPn is connected to power supply, and this current source provides operating voltage for the input stage of self biased amplifier circuit 102.
The grid of NMOS tube MN1-MN2n and PMOS MP3-MPn is jointly connected to the drain electrode inputting PMOS MP1 and forms automatic biasing structure, and this structure, because of the function pin of Appropriate application element, decreases conducting branches, thus reduces the power consumption of this partial circuit.Input the output of drain electrode as self biased amplifier of PMOS MP2.Above n is integer, and its number determines according to design requirement.
Inverting amplifier 104 comprises n PMOS and 1 NMOS tube, form the inverter that PMOS is different from NMOS tube ratio, the PMOS NP1-NPn that wherein PMOS part is less than 1 by breadth length ratio is formed, the drain electrode of PMOS NP1 is connected to the drain electrode of NMOS tube NN1, the source electrode of NP1 is connected with the drain electrode of NP2, the source electrode of NP2 is connected with the drain electrode of NP3, and by that analogy, the source electrode of NPn is connected to power supply.Above n is integer, and its number determines according to design requirement.Input is the grid of PMOS NP1 and the grid of NMOS tube NN1; Output is the drain electrode of PMOS NP1 and the drain electrode of NMOS tube NN1, and the output signal of threshold value comparative result is amplified by this partial circuit, makes it be easy to rear class process, and the level of output signal is contrary with the signal level of input inversion amplifier 104.This inverting amplifier 104 also can adopt but be not limited to the structure such as low dissipation amplifier produce needed for output.
The input of schmitt inverter circuit 105 is connected to the output of inverting amplifier circuit 104, and its output is connected to the input of output buffer 106; Input signal utilizes the threshold voltage of schmitt inverter D2, is met the output signal that design needs; There is the decoupling filter electric capacity Cn2 being connected to ground in the input of schmitt inverter D2, for filtering out the burr signal that may produce false triggering; This decoupling capacitance can have multiple way of realization, includes but not limited to variable capacitance, MOM capacitor, MIM capacitor, active device etc.Wherein, decoupling capacitance also can adopt the form being connected to power supply.
The input of output buffer 106/D3 is connected to the output of schmitt inverter D2, and its output is connected to output node, for improving the driving force exporting external signal to; This output buffer 106/D3 can according to carrying out accepting or rejecting to the demand of driving force and adjusting.
This level converter is operated in wide power voltage territory, when it is operated in 5V supply voltage voltage domain, input node is low level input signal under receiving 1.8V voltage domain, first compared with threshold voltage input signal and threshold generation circuits 103 produced by self biased amplifier 102, distinguish the low and high level of input signal, judge whether comparative result is pressed with corresponding logical signal to power electric, even applied signal voltage is greater than threshold voltage, export high level, if applied signal voltage is less than threshold voltage, now no-output; Amplified by the output signal of sign-changing amplifier 104 by comparative result, by schmitt inverter circuit 105, the signal after amplification is carried out filtration treatment, filter out the burr signal that may produce false triggering, then its driving force is improved by output buffer 106/D3, the required voltage exported under 5V supply voltage domain by output node.When it is operated in 5V supply voltage voltage domain, input node receives the input signal of high level under 3.3V voltage domain, compared with threshold voltage input signal and threshold generation circuits 103 produced by self biased amplifier 102, if applied signal voltage is less than threshold voltage, then change threshold voltage by arranging threshold circuit, make applied signal voltage be greater than threshold voltage, export high level, the required voltage finally exported under 5V supply voltage domain by output node.Wherein, supply voltage need be greater than the input signal under the identical or different supply voltage domain of input.
In addition, self biased amplifier 102, inverting amplifier 104 and Si Mite inverter circuit 105, this three partial circuit achieves the denoising Processing to input signal jointly.If input signal is noise signal, after self biased amplifier 102, inverting amplifier 104 and Si Mite inverter circuit 105, by noise filtering in signal, output node exports without correspondence.
The method flow schematic diagram of a kind of level conversion that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, this level converter is under single power supply environment, and its level conversion method comprises:
Step S401, receive input signal from identical or different supply voltage domain;
Step S402, detect the logical value of input signal in supply voltage domain by self biased amplifier circuit and threshold generation circuits;
Step S403, produce the output signal corresponding to logical value in supply voltage domain.
The structural representation of a kind of threshold generation circuits that Fig. 5 provides for the embodiment of the present invention.As shown in Figure 5, threshold generation circuits 103 adopts the structure of resistance string dividing potential drop, is made up of two resistance R1, R2 that power supply to ground path is connected.One end of resistance R1 is connected to power supply, and the other end is connected to the output of threshold generation circuits 103; One end of resistance R2 is connected to ground, and the other end is connected to the output of threshold generation circuits 103.The threshold voltage that circuit produces is determined by resistance R1, R2 ratio, arranges according to design requirement the power consumption that larger R1, R2 resistance can reduce this partial circuit.Wherein, threshold generation circuits 103 also can adopt but be not limited to the circuit structure such as band-gap reference produce needed for threshold voltage.
The present invention is operated in wide power voltage territory, and work is got final product under single-power voltage powers environment, by the input signal of similar and different supply voltage domain by automatic biasing structural design to reach the object not needing additional bias circuit, and the comparative threshold voltage of setting signal low and high level adapts to wider input voltage range, improve the flexibility of application.By adopting the design of low-power consumption and deburring, by the power consumption control of inner modules in extremely low level, and then ensureing lower overall power, improve the accuracy of signal.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a device for level conversion, described level converter is operated in the first supply voltage domain, it is characterized in that, comprising:
Input circuit, for receiving the input signal from second source voltage domain;
Threshold generation circuits, for generating the threshold voltage distinguishing input signal low and high level;
Self biased amplifier circuit, for described input signal and described threshold voltage being compared, produces logical value;
Described level converter produces the output signal of first supply voltage domain corresponding to described logical value.
2. level converter according to claim 1, is characterized in that, described threshold generation circuits adopts the circuit structure of resistance string dividing potential drop, is made up of two resistance that power supply to the path on ground is connected; Or described threshold generation circuits adopts the circuit structure of band-gap reference.
3. level converter according to claim 1, is characterized in that, described self biased amplifier circuit, comprises two PMOS and forms input stage, the active electric current mirror load of NMOS tube formation, the current source of PMOS formation common gate;
Described input stage comprises two PMOS, and the grid of the first PMOS is positive input, and the grid of the second PMOS is negative input; Described common gate current source is made up of NMOS tube, its source electrode is connected to described first supply voltage, drain electrode is connected to the source electrode of input stage, the grid of grid and the load of described active electric current mirror is connected to the drain electrode of the first PMOS described in input stage jointly, the load of described active electric current mirror is made up of two row PMOS, the drain electrode of a described row PMOS be connected to the first PMOS of described input stage drain electrode, the drain electrode of another row PMOS described be connected to the second PMOS of described input stage drain electrode, form inner automatic biasing structure.
4. level converter according to claim 1, is characterized in that, described self biased amplifier circuit specifically for:
By input signal being determined compared with described threshold voltage the described logical value of input signal, and comparative result is converted to the logical signal corresponding to the first supply voltage and exports.
5. level converter according to claim 1, is characterized in that, also comprises inverting amplifier;
Described inverting amplifier comprises PMOS and NMOS tube, for the output signal of described comparative result being carried out amplification process; Or described inverting amplifier adopts low dissipation amplifier.
6. level converter according to claim 1, is characterized in that, described inverting amplifier is specifically made up of the different PMOS of ratio and NMOS tube.
7. level converter according to claim 1, is characterized in that, also comprises schmitt inverter circuit;
Described schmitt inverter circuit comprises schmitt inverter and decoupling zero filter capacitor, for the false triggering preventing described comparative result from exporting.
8. level converter according to claim 1, is characterized in that, described automatic biasing amplifying circuit, and described schmitt inverter circuit and described inverting amplifier and filter capacitor complete deburring function jointly.
9. level converter according to claim 1, is characterized in that, also comprises output buffer;
Described output buffer exports the driving force of external signal to for improving, can according to carrying out accepting or rejecting to the demand of driving force and adjusting.
10. a method for level conversion, is characterized in that, comprising:
Receive the input signal from described second source voltage domain;
The logical value of described input signal is detected by described self biased amplifier circuit and described threshold generation circuits in described first supply voltage domain;
The output signal corresponding to described logical value is produced in described first supply voltage domain.
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| CN106230432A (en) * | 2016-08-30 | 2016-12-14 | 成都紫微芯源科技有限公司 | A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth |
| CN106291064A (en) * | 2016-10-11 | 2017-01-04 | 英特格灵芯片(天津)有限公司 | A kind of closed loop voltage detecting system |
| CN109428586A (en) * | 2017-08-29 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Prevent the input/output circuitry and associated method of burr |
| CN110995245A (en) * | 2019-12-27 | 2020-04-10 | 成都九芯微科技有限公司 | Input circuit |
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| CN109428586A (en) * | 2017-08-29 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Prevent the input/output circuitry and associated method of burr |
| CN109428586B (en) * | 2017-08-29 | 2022-08-05 | 台湾积体电路制造股份有限公司 | Glitch prevention input/output circuit and related method |
| CN110995245A (en) * | 2019-12-27 | 2020-04-10 | 成都九芯微科技有限公司 | Input circuit |
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