CN101179269A - Converting circuit of implementing difference level signal to single end level signal - Google Patents
Converting circuit of implementing difference level signal to single end level signal Download PDFInfo
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- CN101179269A CN101179269A CNA2006101386705A CN200610138670A CN101179269A CN 101179269 A CN101179269 A CN 101179269A CN A2006101386705 A CNA2006101386705 A CN A2006101386705A CN 200610138670 A CN200610138670 A CN 200610138670A CN 101179269 A CN101179269 A CN 101179269A
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Abstract
The invention discloses a conversion circuit for converting differential electric level signals into single-ended electric level signals, which includes: a voltage comparator wherein one end of a forward input terminal and one end of a reverse input terminal are linked with an output terminal of the differential electric level with the input voltage obtained by partial pressure of a first resistance networks and a second resistance networks. The other end of the forward input terminal and the other end of the reverse input terminal of the voltage comparator are input terminals of reference voltage and the reference voltage of the input terminals are obtained by the partial pressure of a third resistance networks and a fourth resistance networks. An output terminal of the voltage comparator is linked with the single-ended electric level. The invention realizes the conversion from the differential electric level signals into the single-ended electric level signals.
Description
Technical field
The invention belongs to the circuit design technique field, be specifically related to realize the change-over circuit of difference level signal to single end level signal.
Background technology
Now, for satisfying different functional requirements, Circuits System is complicated day by day, and data quantity transmitted is increasing, and real-time requires more and more higher, and transmission range is more and more longer, and the speed of transmission is more and more higher.For adapting to this development, the interface level of electronic device has a lot of standards.Level standard commonly used has TTL (Transistor-Transistor Logic, transistor logic), CMOS (Complementary Metal Oxide Semiconductor PMOS+NMOS), LVTTL (Low Voltage TTL, the low-voltag transistor logic), LVCMOS (Low Voltage CMOS, low voltage cmos), ECL (Emitter Coupled Logic, emitter coupled logic), PECL (Pseudo/Positive Emitter Coupled Logic, the emitter coupled logic of positive electricity extreme pressure power supply), LVPECL (emitter coupled logic of Low Voltage PECL low-voltage positive voltage power supply), CML (CurrentMode Logic, the commonality schemata logic), LVDS (Low Voltage Differential Signaling, low-voltage shunting signal stream), GTL (Gunning Transceiver Logic, gunn transceiver logic), RS232, RS485 etc.
Wherein, this three class of PECL, LVDS and CML level adopts the level of differential pair transmit high-speed signals to solve the transmission rate height that requires in the high-speed line, and antijamming capability is strong, and problems such as long transmission distance are used very extensive.The PECL level, the emitter-coupled logic (ECL) that promptly adopts positive voltage to power, differential configuration, its level canonical parameter is: operating voltage 5V, output HIGH voltage representative value are 4.1V, the output LOW voltage representative value is 3.3V.The LVDS level, i.e. low-voltage differential signal, the core of this technology is to adopt extremely low voltage swing high speed differential transmission data, the differential pair input and output, there is a constant-current source 3.5-4mA inside, changes direction and represent 0 and 1 on differential lines.100 Europe build-out resistors by the outside (and on differential lines near receiving terminal) are converted to ± differential level of 350mV.The CML level is the simplest a kind of in all high speed interfaces, and the typical output circuit of its interface is a differential pair form.The collector resistance of this differential pair is 50 Ω, and the high-low level switching of output signal is to control by the switch of common emitter differential pair.The emitter of differential pair is 16mA to the constant-current source representative value on ground.The output loading of supposing CML is one 50 Ω pull-up resistor, and the amplitude of oscillation of then single-ended CML output signal is the V of VCC～(VCC-0.4).In this case, the differential output signal amplitude of oscillation is 800mV.Signal swing is less, so power consumption is very low, CML interface level power consumption is lower than 1/2 of ECL, and its differential signal interface and ECL, LVDS level have similar characteristics.
But owing to the reason of chip producer self etc., the interface level of a lot of chips is the single-ended level of TTL/CMOS.Wherein Transistor-Transistor Logic level is an audion, and its output HIGH voltage is greater than 2.4V, and low-voltage is less than 0.4V, and the input high voltage is greater than 2V, and the input low-voltage is less than 0.8V.
Therefore, realize the connection of differential level device (as PECL level device) to single-ended level device (as the Transistor-Transistor Logic level device), must be by level shifting circuit or level transferring chip.
Summary of the invention
In order to overcome above-mentioned defective, the object of the present invention is to provide a kind of change-over circuit of reliable and stable realization difference level signal to single end level signal.
For achieving the above object, a kind of change-over circuit of realizing difference level signal to single end level signal of the present invention, comprise: a voltage comparator, one of the forward input of this voltage comparator, reverse input end connects an output of differential level, and the input voltage of this input is obtained by the first input resistance network and the second input resistance network dividing potential drop;
The forward input of this voltage comparator, the other end of oppositely input are the reference voltage input terminal of this voltage comparator, and the reference voltage of this input is obtained by the 3rd resistor network and the 4th resistor network dividing potential drop;
The output of this voltage comparator connects single-ended level.
Further, described first resistor network input voltage that dividing potential drop obtains of connecting with second resistor network meets the impedance matching of differential level signal and the requirement of its dc offset voltage.
Further, connect with the 4th resistor network reference voltage that dividing potential drop obtains of described the 3rd resistor network equals the dc offset voltage of differential level.
Further, the output voltage of the output of described voltage comparator meets connected single-ended level standard.
Further, the power input at described voltage comparator disposes a decoupling capacitance.
Change-over circuit of the present invention converts with receiving terminal the high-low level amplitude of signal to and requires the signal level (VOUT) of mating, thereby has realized the conversion by difference level signal to single end level signal.
Description of drawings
Fig. 1 is a difference level signal to single end level signal change-over circuit schematic diagram of the present invention;
Fig. 2 is the change-over circuit schematic diagram of PECL level to Transistor-Transistor Logic level.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is further described in detail: as shown in Figure 1, the present invention realizes that the change-over circuit of difference level signal to single end level signal mainly is made up of an electric group network and a voltage comparator, end with the differential level signal of both-end output, be connected to an input (VIN) of the voltage comparator of change-over circuit of the present invention, the voltage of this input (DC level that b is ordered among Fig. 1) is by R1, R2 resistance and voltage (V3, V4) decision, should equal the DC biased level of corresponding input signal, the reference voltage of another input of voltage comparator is by voltage (V2, V5) by resistor network R3, the R4 dividing potential drop obtains (a point voltage of Fig. 1).
Wherein, the two-way of voltage comparator is input as analog signal, and output then be binary signal, and when the difference of input voltage increased or reduces, its output maintenance was constant.The selection of voltage comparator, the output voltage that guarantees voltage comparator meets corresponding single-ended level standard, simultaneously, according to real needs, be also noted that the output delay time and the reversal rate of voltage comparator, because this parameter directly determines the frequency range of the input signal of change-over circuit of the present invention.
Resistor voltage divider network (R3, R4) selection of resistance will guarantee that the reference voltage level of voltage comparator equals the dc offset voltage of differential level, simultaneously, resistance value is selected also should take into account the power consumption requirement.
The parameter of the R1 of voltage comparator signal input part, R2 resistor network is selected, and need consider impedance matching and its DC biased level of input difference level signal simultaneously.The single-ended matched impedance of common differential level signal requires to be about 50 ohm.
Fig. 2 is a concrete application example of change-over circuit of the present invention, realize the transformation applications of PECL level to Transistor-Transistor Logic level, wherein, signal source is the PECL level signal, the 5V power supply, the output high level is 4.1V, low level is 3.3 V, dc offset voltage is 3.7V, connects the positive input of voltage comparator.
By divider resistance R3, the R4 dividing potential drop obtains the reference voltage of voltage comparator by the 5V supply voltage, and resistance is selected to be respectively R3 and equaled 1K ohm, and R4 equals 3K ohm.The reference voltage that obtains of dividing potential drop is 3.75V thus, connects the reverse input end of voltage comparator.The receiving terminal requirement on devices is single-ended Transistor-Transistor Logic level, and supply voltage is direct current 5V.
At this PECL level in the transformation applications of Transistor-Transistor Logic level, the LMC7215 that is chosen as National Semiconductor company of voltage comparator, its working power voltage 2～8V.When supply voltage was selected 5V for use, its output high level is minimum to be 4.6V, and output low level is the highest 0.4V, meets the Transistor-Transistor Logic level requirement fully.
Because R1, the selection of R2 will be considered the single-ended impedance coupling of 50 ohm of PECL signals and the DC biased level of 3.7V, signal input part R1, and the resistance of R2 resistor network is selected to be respectively 68 ohm, 180 ohm.The Dai Weining equivalent impedance that calculates is 49.35 ohm, and the direct voltage bias point is 3.63V, meets the design object value substantially.
To the power input of voltage comparator, the decoupling capacitance C1 of one 0.1 μ F of configuration reduces the influence of power supply noise to voltage comparator.At the TTL of voltage comparator output, the resistance R 5 that seals in 33 ohm is as the source terminal impedance build-out resistor of TTL signal.
In sum, change-over circuit of the present invention converts with receiving terminal the high-low level amplitude of signal to and requires the signal level (VOUT) of mating, and finishes the conversion of difference level signal to single end level signal.
Claims (5)
1. change-over circuit of realizing difference level signal to single end level signal, it is characterized in that, comprise: a voltage comparator, one of the forward input of this voltage comparator, reverse input end connects an output of differential level, and the input voltage of this input is obtained by the first input resistance network and the second input resistance network dividing potential drop;
The forward input of this voltage comparator, the other end of oppositely input are the reference voltage input terminal of this voltage comparator, and the reference voltage of this input is obtained by the 3rd resistor network and the 4th resistor network dividing potential drop;
The output of this voltage comparator connects single-ended level.
2. the change-over circuit of realization difference level signal to single end level signal according to claim 1, it is characterized in that described first resistor network input voltage that dividing potential drop obtains of connecting with second resistor network meets the impedance matching of differential level signal and the requirement of its dc offset voltage.
3. the change-over circuit of realization difference level signal to single end level signal according to claim 2 is characterized in that, connect with the 4th resistor network reference voltage that dividing potential drop obtains of described the 3rd resistor network equals the dc offset voltage of differential level.
4. according to the change-over circuit of claim 1 or 3 described realization difference level signal to single end level signal, it is characterized in that the output voltage of the output of described voltage comparator meets connected single-ended level standard.
5. the change-over circuit of realization difference level signal to single end level signal according to claim 4 is characterized in that, at decoupling capacitance of power input configuration of described voltage comparator.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101386705A CN101179269A (en) | 2006-11-10 | 2006-11-10 | Converting circuit of implementing difference level signal to single end level signal |
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| CNA2006101386705A CN101179269A (en) | 2006-11-10 | 2006-11-10 | Converting circuit of implementing difference level signal to single end level signal |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534117B (en) * | 2009-03-31 | 2011-08-24 | 炬力集成电路设计有限公司 | A signal switching circuit |
| CN102857210A (en) * | 2012-09-28 | 2013-01-02 | 无锡江南计算技术研究所 | Different voltage standard label virtual circuit metal oxide semiconductor (LVCMOS) signal direct interconnection method |
| CN103346773A (en) * | 2013-07-10 | 2013-10-09 | 昆山锐芯微电子有限公司 | Level conversion circuit |
| CN105141305A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Level conversion method and device |
| CN107465397A (en) * | 2017-08-08 | 2017-12-12 | 中国电子科技集团公司第二十九研究所 | A kind of LVPECL signal communications termination power and its selection control method |
| CN111181826A (en) * | 2019-12-31 | 2020-05-19 | 中国铁道科学研究院集团有限公司 | Dynamic networking master control device |
| CN113595841A (en) * | 2020-04-30 | 2021-11-02 | 烽火通信科技股份有限公司 | PECI bus expansion method and system |
-
2006
- 2006-11-10 CN CNA2006101386705A patent/CN101179269A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534117B (en) * | 2009-03-31 | 2011-08-24 | 炬力集成电路设计有限公司 | A signal switching circuit |
| CN102857210A (en) * | 2012-09-28 | 2013-01-02 | 无锡江南计算技术研究所 | Different voltage standard label virtual circuit metal oxide semiconductor (LVCMOS) signal direct interconnection method |
| CN103346773A (en) * | 2013-07-10 | 2013-10-09 | 昆山锐芯微电子有限公司 | Level conversion circuit |
| CN103346773B (en) * | 2013-07-10 | 2016-11-09 | 昆山锐芯微电子有限公司 | Level shifting circuit |
| CN105141305A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Level conversion method and device |
| CN105141305B (en) * | 2015-09-11 | 2018-06-15 | 英特格灵芯片(天津)有限公司 | A kind of method and device of level conversion |
| CN107465397A (en) * | 2017-08-08 | 2017-12-12 | 中国电子科技集团公司第二十九研究所 | A kind of LVPECL signal communications termination power and its selection control method |
| CN107465397B (en) * | 2017-08-08 | 2020-09-29 | 中国电子科技集团公司第二十九研究所 | LVPECL signal alternating-current coupling circuit and selection control method thereof |
| CN111181826A (en) * | 2019-12-31 | 2020-05-19 | 中国铁道科学研究院集团有限公司 | Dynamic networking master control device |
| CN111181826B (en) * | 2019-12-31 | 2021-10-01 | 中国铁道科学研究院集团有限公司 | Dynamic networking master control device |
| CN113595841A (en) * | 2020-04-30 | 2021-11-02 | 烽火通信科技股份有限公司 | PECI bus expansion method and system |
| CN113595841B (en) * | 2020-04-30 | 2022-10-18 | 烽火通信科技股份有限公司 | PECI bus expansion method and system |
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Open date: 20080514 |