CN103346773B - Level shifting circuit - Google Patents
Level shifting circuit Download PDFInfo
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- CN103346773B CN103346773B CN201310288505.8A CN201310288505A CN103346773B CN 103346773 B CN103346773 B CN 103346773B CN 201310288505 A CN201310288505 A CN 201310288505A CN 103346773 B CN103346773 B CN 103346773B
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Abstract
A kind of level shifting circuit, including generating circuit from reference voltage, difference channel and difference turn single-end circuit, wherein, described generating circuit from reference voltage is suitable to obtain reference voltage according to first object voltage and the second target voltage, and described reference voltage is the mean value of described first object voltage and the second target voltage；Described difference channel is suitable to obtain the described first driving signal and two driving signal according to the first input signal, the second input signal and described reference voltage；Described difference turns single-end circuit and is driven by described first driving signal and two driving signal.The conversion that the level shifting circuit that the present invention provides is capable of between varying level, has very strong versatility.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly to a kind of level shifting circuit.
Background technology
Level shifting circuit is highly important a kind of interface circuit in integrated circuit, and its function is one
Supply voltage/ground voltage changes into another kind of supply voltage/ground voltage.By level shifting circuit, can will believe
It number is transformed into another kind of power domain from a kind of power domain, facilitate signal being suitable in respective power domain carrying out
Various calculation process.
For example, the high-frequency digital signal disturbing with high voltage amplitude is very strong, is suitable in low tension source domain
In do various logic computing, and analog signal is in order to obtain high s/n ratio, is suitable in high-tension electricity source domain
Reason.Under normal circumstances, the digital circuit of low pressure needs to be controlled signal between the analog circuit of high pressure
Communication, low pressure is turned high voltage level change-over circuit the low-voltage signal that digital circuit exports is converted into high pressure
Signal, to analog circuit, is turned low voltage level change-over circuit by high pressure and turns the high-voltage signal that analog circuit exports
Changing low-voltage signal into digital circuit, the former is referred to as shift circuit on level, and the latter is referred to as shift circuit under level.
In prior art, on common level shift circuit include phase inverter, two powered by high voltage power supply
High pressure NMOS pipe and drive circuit.When carrying out level conversion, low-voltage signal can after inverter drive
Obtain the signal of two-way opposite in phase, using the signal of two-way opposite in phase as two high pressure NMOSs
The driving signal of tube grid, under the control of described driving signal, the drain electrode output of high pressure NMOS pipe is passed through
Drive circuit i.e. obtains high-voltage signal.
Under common level, shift circuit has two classes: a class includes high pressure NMOS pipe and low-voltage driving circuit,
When carrying out level conversion, using high-voltage signal as the driving of the high pressure NMOS tube grid powered by low-tension supply
Signal, under the control of described driving signal, the drain electrode of high pressure NMOS pipe exports through low-voltage driving circuit
I.e. obtain low-voltage signal；Another kind of include resistance, source follower and diode, by the dividing potential drop of resistance,
Gate source voltage displacement, diode translocation realize the conversion of level.
But, the limit of the factors such as scarce capacity driven, high-low pressure metal-oxide-semiconductor threshold voltage, circuit structure
System, level shifting circuit of the prior art cannot realize the conversion between any two absolute level, logical
Relatively low by property.
More technical schemes with regard to level shifting circuit are referred to Publication No. US2008054941, send out
Bright entitled Voltage Level Shifter Circuit(level shift circuit) U.S. Patent application file.
Content of the invention
What the present invention solved is the problem that existing level shifting circuit versatility is low.
For solving the problems referred to above, the present invention provides a kind of level shifting circuit, comprising:
Generating circuit from reference voltage, is suitable to obtain with reference to electricity according to first object voltage and the second target voltage
Pressure, described reference voltage is the mean value of described first object voltage and the second target voltage, described first
Target voltage is higher than described second target voltage；
The difference powered by described first object voltage and described second target voltage turns single-end circuit, including
The first load metal-oxide-semiconductor that cross-coupled positive feedback connects and the second load metal-oxide-semiconductor, first negative with described
Carrying the first input metal-oxide-semiconductor that metal-oxide-semiconductor connects, second being connected with described second load metal-oxide-semiconductor is defeated
Enter metal-oxide-semiconductor；The grid of described first input metal-oxide-semiconductor is suitable to input the first driving signal, and described second
The grid of input metal-oxide-semiconductor is suitable to input two driving signal, described first input metal-oxide-semiconductor and second defeated
The threshold voltage entering metal-oxide-semiconductor is equal；
Difference channel, is suitable to obtain according to the first input signal, the second input signal and described reference voltage
Described first driving signal and two driving signal, described first input signal and the second input signal are poor
Sub-signal, described first driving signal and two driving signal are differential signal, described first driving signal
High level voltage and described reference voltage difference be equal to described reference voltage and described first driving signal
The difference of low level voltage, described first driving signal be suitable to make the described first input metal-oxide-semiconductor conducting or
Cut-off.
Optionally, described generating circuit from reference voltage include the first divider resistance, the second divider resistance,
Three input metal-oxide-semiconductors and the first biasing metal-oxide-semiconductor；Wherein, one end of described first divider resistance is suitable to defeated
Entering described first object voltage, the other end of described first divider resistance connects described second divider resistance
One end and the grid of described 3rd input metal-oxide-semiconductor；The other end of described second divider resistance is suitable to input institute
State the second target voltage；The drain electrode of described 3rd input metal-oxide-semiconductor is suitable to input described first object voltage,
The source electrode of described 3rd input metal-oxide-semiconductor connects the drain electrode of the described first biasing metal-oxide-semiconductor and as described ginseng
Examine the output of the described reference voltage of voltage generation circuit output；The grid of described first biasing metal-oxide-semiconductor is fitted
Make the first conducting voltage of the described first biasing metal-oxide-semiconductor saturation conduction, described first biasing MOS in input
The source electrode of pipe is suitable to input described second target voltage；Described first divider resistance and described second dividing potential drop electricity
The resistance of resistance is according to Vss1+(Vdd1-Vss1) * r2/(r1+r2)=(Vdd1+Vss1)/2+Vthn+
(2*ID*L/μn*Cox* W)1/2Determining, wherein, Vdd1 represents described first object voltage, and Vss1 represents
Described second target voltage, r1 represents the resistance of described first divider resistance, and r2 represents described second dividing potential drop
The resistance of resistance, Vthn represents the threshold voltage of the described 3rd input metal-oxide-semiconductor, IDRepresent that the described 3rd is defeated
Entering the drain current of metal-oxide-semiconductor, L represents the channel length of the described 3rd input metal-oxide-semiconductor, μnRepresent institute
State the carrier mobility of the 3rd input metal-oxide-semiconductor, CoxRepresent the grid list of the described 3rd input metal-oxide-semiconductor
Plane amasss oxide layer electric capacity, and W represents the channel width of the described 3rd input metal-oxide-semiconductor.
Optionally, described generating circuit from reference voltage include the 3rd divider resistance, the 4th divider resistance,
Two biasing metal-oxide-semiconductors and the 4th input metal-oxide-semiconductor；Wherein, one end of described 3rd divider resistance is suitable to defeated
Entering described first object voltage, the other end of described 3rd divider resistance connects described 4th divider resistance
One end and the grid of described 4th input metal-oxide-semiconductor；The other end of described 4th divider resistance is suitable to input institute
State the second target voltage；The grid of described second biasing metal-oxide-semiconductor is suitable to input makes the described second biasing MOS
Second conducting voltage of pipe saturation conduction, the source electrode of described second biasing metal-oxide-semiconductor is suitable to input described first
Target voltage, the drain electrode of described second biasing metal-oxide-semiconductor connects the source electrode of the described 4th input metal-oxide-semiconductor simultaneously
Output as the described reference voltage of described generating circuit from reference voltage output；Described 4th input MOS
The drain electrode of pipe is suitable to input described second target voltage；Described 3rd divider resistance and described 4th dividing potential drop electricity
The resistance of resistance is according to Vss1+(Vdd1-Vss1) * r4/(r3+r4)=(Vdd1+Vss1)/2-Vthp-
(2*ID*L/μp*Cox* W)1/2Determining, wherein, Vdd1 represents described first object voltage, and Vss1 represents
Described second target voltage, r3 represents the resistance of described 3rd divider resistance, and r4 represents described 4th dividing potential drop
The resistance of resistance, Vthp represents the threshold voltage of the described 4th input metal-oxide-semiconductor, IDRepresent that the described 4th is defeated
Entering the drain current of metal-oxide-semiconductor, L represents the channel length of the described 4th input metal-oxide-semiconductor, μpRepresent institute
State the carrier mobility of the 4th input metal-oxide-semiconductor, CoxRepresent the grid list of the described 4th input metal-oxide-semiconductor
Plane amasss oxide layer electric capacity, and W represents the channel width of the described 4th input metal-oxide-semiconductor.
Optionally, described first load metal-oxide-semiconductor and described second load metal-oxide-semiconductor are NMOS tube, institute
State the first input metal-oxide-semiconductor and described second input metal-oxide-semiconductor is PMOS, described first object voltage
It is less than the threshold value of the described first input metal-oxide-semiconductor with the difference of the high level voltage of described first driving signal
Voltage, the difference of the low level voltage with described first driving signal for the described first object voltage is more than described
The threshold voltage of the first input metal-oxide-semiconductor.
Optionally, described difference channel include the first constant current metal-oxide-semiconductor, the second constant current metal-oxide-semiconductor, first
Common mode sample resistance, the second common mode sample resistance, the first Differential Input metal-oxide-semiconductor, the second Differential Input
Metal-oxide-semiconductor and the first tail current source metal-oxide-semiconductor；Wherein, described first common mode sample resistance and described second
The resistance of common mode sample resistance is identical；The grid of described first constant current metal-oxide-semiconductor connects described second constant current
The grid of metal-oxide-semiconductor is simultaneously suitable to input and makes described first constant current metal-oxide-semiconductor and described second constant current metal-oxide-semiconductor satisfy
With the 3rd conducting voltage of conducting, the source electrode of described first constant current metal-oxide-semiconductor is suitable to input described first object
Voltage, the drain electrode of described first constant current metal-oxide-semiconductor connects the drain electrode of described first Differential Input metal-oxide-semiconductor simultaneously
The first output as the described first driving signal of described difference channel output；Described second constant current MOS
The source electrode of pipe is suitable to input described first object voltage, and the drain electrode of described second constant current metal-oxide-semiconductor connects described
The drain electrode of the second Differential Input metal-oxide-semiconductor as the described two driving signal of described difference channel output
Second output；One end of described first common mode sample resistance connects the leakage of described first constant current metal-oxide-semiconductor
Pole, the other end connects one end of described second common mode sample resistance and as described in the input of described difference channel
The input of reference voltage；The other end of described second common mode sample resistance connects described second constant current MOS
The drain electrode of pipe；The grid of described first Differential Input metal-oxide-semiconductor is suitable to input described first input signal, institute
State the source electrode of the first Differential Input metal-oxide-semiconductor and connect the source electrode of described second Differential Input metal-oxide-semiconductor and described
The drain electrode of the first tail current source metal-oxide-semiconductor；The grid of described second Differential Input metal-oxide-semiconductor is suitable to input institute
State the second input signal；The grid of described first tail current source metal-oxide-semiconductor is suitable to input makes described first tail electricity
4th conducting voltage of stream source metal-oxide-semiconductor saturation conduction, the source electrode of described first tail current source metal-oxide-semiconductor is fitted
It is less than the first supply voltage of described first object voltage in input.
Optionally, described first load metal-oxide-semiconductor and described second load metal-oxide-semiconductor are PMOS, institute
State the first input metal-oxide-semiconductor and described second input metal-oxide-semiconductor is NMOS tube, described first driving signal
The difference of high level voltage and described second target voltage more than the threshold value of described first input metal-oxide-semiconductor
Voltage, the low level voltage of described first driving signal is less than described with the difference of described second target voltage
The threshold voltage of the first input metal-oxide-semiconductor.
Optionally, described difference channel includes the second tail current source metal-oxide-semiconductor, the 3rd Differential Input MOS
Pipe, the 4th Differential Input metal-oxide-semiconductor, the 3rd common mode sample resistance, the 4th common mode sample resistance, the 3rd perseverance
Stream metal-oxide-semiconductor and the 4th constant current metal-oxide-semiconductor；Wherein, described 3rd common mode sample resistance and the described 4th is altogether
The resistance of mould sample resistance is identical, and the grid of described second tail current source metal-oxide-semiconductor is suitable to input makes described
5th conducting voltage of two tail current source metal-oxide-semiconductor saturation conductions, described second tail current source metal-oxide-semiconductor
Source electrode is suitable to the second source voltage higher than described second target voltage for the input, described second tail current source
The drain electrode of metal-oxide-semiconductor connects the source electrode of described 3rd Differential Input metal-oxide-semiconductor and described 4th Differential Input
The source electrode of metal-oxide-semiconductor；The grid of described 3rd Differential Input metal-oxide-semiconductor is suitable to input the described first input letter
Number, the drain electrode of described 3rd Differential Input metal-oxide-semiconductor connects the drain electrode of described 3rd constant current metal-oxide-semiconductor and makees
The first output for the described first driving signal of described difference channel output；Described 4th Differential Input
The grid of metal-oxide-semiconductor is suitable to input described second input signal, the leakage of described 4th Differential Input metal-oxide-semiconductor
Pole connects the drain electrode of described 4th constant current metal-oxide-semiconductor and drives as described difference channel output described second
Second output of signal；One end of described 3rd common mode sample resistance connects described 3rd Differential Input
The drain electrode of metal-oxide-semiconductor, the other end connects one end of described 4th common mode sample resistance and as described differential electrical
The input of the described reference voltage of road input；The other end of described 4th common mode sample resistance connects described the
The drain electrode of four Differential Input metal-oxide-semiconductors；The grid of described 3rd constant current metal-oxide-semiconductor connects described 4th constant current
The grid of metal-oxide-semiconductor is simultaneously suitable to input and makes described 3rd constant current metal-oxide-semiconductor and described 4th constant current metal-oxide-semiconductor satisfy
With the 6th conducting voltage of conducting, the source electrode of described 3rd constant current metal-oxide-semiconductor is suitable to input described second target
Voltage；The source electrode of described 4th constant current metal-oxide-semiconductor is suitable to input described second target voltage.
Optionally, described level shifting circuit also includes by described first object voltage and described second target
The CMOS inverter of power voltage supply, the input of described CMOS inverter connects the described second load
Metal-oxide-semiconductor and the described second connection end inputting metal-oxide-semiconductor.
Compared with prior art, technical scheme has the advantage that
Being produced magnitude of voltage by generating circuit from reference voltage is the average of first object voltage and the second target voltage
The reference voltage of value, and by described reference voltage input difference circuit.Defeated in the first input signal and second
Enter under the control of signal, utilize the common mode sample resistance that in described difference channel, two resistances are equal, force
The the first driving signal and second making the output of described difference channel follow the change of described reference voltage drives letter
Number.Described first driving signal and two driving signal are differential signal, the height of described first driving signal
The difference of level voltage and described reference voltage is equal to described reference voltage and described first and drives the low of signal
The difference of level voltage.
When described first object voltage and described second target voltage change, described reference voltage is sent out therewith
Changing, so that the low and high level of described first driving signal and described two driving signal is followed described
First object voltage and described second target voltage change, can drive by described first object voltage and institute
State the difference that the second target voltage powers and turn single-end circuit, it is achieved the conversion between varying level, therefore,
The level shifting circuit that the present invention provides has very strong versatility.
Brief description
Fig. 1 is the structural representation of the level shifting circuit of embodiment of the present invention；
Fig. 2 is a kind of circuit diagram of the generating circuit from reference voltage of the embodiment of the present invention 1；
Fig. 3 is the another kind of circuit diagram of the generating circuit from reference voltage of the embodiment of the present invention 1；
Fig. 4 is the partial circuit diagram of the level shifting circuit of the embodiment of the present invention 1；
Fig. 5 is the signal waveforms during level shifting circuit work of the embodiment of the present invention 1；
Fig. 6 is the partial circuit diagram of the level shifting circuit of the embodiment of the present invention 2.
Detailed description of the invention
Just as described in the background art, existing level shifting circuit is owing to can not realize any two
Conversion between absolute level, the versatility of level shifting circuit is relatively low.Inventor, through research, provides
A kind of level shifting circuit of highly versatile.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Fig. 1 is the structural representation of the level shifting circuit of embodiment of the present invention.With reference to Fig. 1, described electricity
Flat change-over circuit includes that generating circuit from reference voltage the 11st, difference channel 12 and difference turn single-end circuit 13.
Described generating circuit from reference voltage 11 is suitable to according to first object voltage Vdd1 and the second target voltage
Vss1 obtains reference voltage Vcm, and described reference voltage Vcm is described first object voltage Vdd1 and institute
State the mean value of the second target voltage Vss1, i.e. Vcm=(Vdd1+Vss1)/2, described first object electricity
Pressure Vdd1 is higher than described second target voltage Vss1.
Described first object voltage Vdd1 and described second target voltage Vss1 is respectively the letter needing to obtain
Number high level voltage and low level voltage, in meeting circuit transistor pressure under the conditions of, described
One target voltage Vdd1 and described second target voltage Vss1 can arbitrarily be arranged according to the actual requirements.
Described difference turns single-end circuit 13 by described first object voltage Vdd1 and described second target voltage
Vss1 powers, including the first load metal-oxide-semiconductor, second load metal-oxide-semiconductor, first input metal-oxide-semiconductor and
Second input metal-oxide-semiconductor (Fig. 1 is not shown).
Described first load metal-oxide-semiconductor becomes cross-coupled positive feedback to connect with described second load metal-oxide-semiconductor,
Described first input metal-oxide-semiconductor is connected with described first load metal-oxide-semiconductor, described second input metal-oxide-semiconductor
It is connected with described second load metal-oxide-semiconductor.The grid of described first input metal-oxide-semiconductor is suitable to input first and drives
Dynamic signal Von, the grid of described second input metal-oxide-semiconductor is suitable to input two driving signal Vop, described
The threshold voltage of the first input metal-oxide-semiconductor and the second input metal-oxide-semiconductor is equal.
Those skilled in the art know, and level shifting circuit includes level that low transition is high level
Upper shift circuit and high level is converted to shift circuit under low level level, therefore, constitutes described difference and turns
The transistor of single-end circuit 13 can be PMOS transistor or nmos pass transistor, each crystalline substance
Concrete annexation between body pipe sees the detailed description in following example.
Described difference channel 12 is suitable to according to the first input signal Vin1, the second input signal Vin2 and institute
State reference voltage Vcm and obtain the described first driving signal Von and described two driving signal Vop.Described
First input signal Vin1 and described second input signal Vin2 are differential signal, described first driving signal
Von and described two driving signal Vop is also differential signal, and differential signal refers to equal in magnitude, polarity
A pair contrary signal.
Described first input signal Vin1 or described second input signal Vin2 are for needing the letter changed
Number, i.e. by described level shifting circuit, the high level voltage of described first input signal Vin1 is converted to
The low level voltage of described first input signal Vin1 is converted to institute by described first object voltage Vdd1
State the second target voltage Vss1；Or, by described level shifting circuit by described second input signal Vin2
High level voltage be converted to described first object voltage Vdd1, by described second input signal Vin2
Low level voltage is converted to described second target voltage Vss1.
If described first input signal Vin1 is for needing the signal of conversion, described second input signal Vin2
Anti-phase acquisition can be carried out by described first input signal Vin1；If described second input signal Vin2 is for needing
Signal to be changed, described first input signal Vin1 can be carried out instead by described second input signal Vin2
Obtain mutually.
Due to the effect of described difference channel 12, the high level voltage of described first driving signal Von and institute
The difference stating reference voltage Vcm is equal to described reference voltage Vcm's and described two driving signal Vop
The difference of low level voltage, i.e. described reference voltage Vcm is the high level of the described first driving signal Von
Voltage and the average of low level voltage.Described first driving signal Von and described two driving signal Vop
For differential signal, therefore, described reference voltage Vcm is also for the high level of described two driving signal Vop
Voltage and the average of low level voltage.
In the technical program, described first driving signal Von is suitable to make the described first input metal-oxide-semiconductor lead
Lead to or cut-off, owing to described first driving signal Von and described two driving signal Vop is differential signal,
And the threshold voltage of described first input metal-oxide-semiconductor and described second input metal-oxide-semiconductor is equal, therefore,
When described first driving signal Von makes the described first input metal-oxide-semiconductor conducting, described two driving signal
Vop makes the described second input metal-oxide-semiconductor cut-off；Described first driving signal Von makes described first to input
During metal-oxide-semiconductor cut-off, described two driving signal Vop makes the described second input metal-oxide-semiconductor conducting.
As described first object voltage Vdd1 and described second target voltage Vss1 change, described reference
Voltage Vcm changes therewith, so that described first driving signal Von and described two driving signal
The level of Vop and the amplitude of oscillation are followed described first object voltage Vdd1 and described second target voltage Vss1 and are become
Change, the difference powered by described first object voltage Vdd1 and described second target voltage Vss1 can be driven
Divide and turn single-end circuit 13, it is achieved the conversion between varying level.
Level shifting circuit includes on level shift circuit under shift circuit and level, for being more fully understood that the present invention
The structure of the level shifting circuit providing and operation principle, carried out with specific embodiment below in conjunction with the accompanying drawings
Detailed description.
Embodiment 1
In the present embodiment, to realize to carry out as a example by shift circuit on the level as high level for the low transition
Explanation.Fig. 2 is a kind of circuit diagram of the present embodiment generating circuit from reference voltage.With reference to Fig. 2, described reference
Voltage generation circuit includes the first divider resistance R1, the second divider resistance R2, the 3rd input metal-oxide-semiconductor
N1 and first biasing metal-oxide-semiconductor N2, described 3rd input metal-oxide-semiconductor N1 and described first biasing MOS
Pipe N2 forms source follower.
One end of described first divider resistance R1 is suitable to input described first object voltage Vdd1, and described
The other end of one divider resistance R1 connects one end of described second divider resistance R2 and described 3rd input
The grid of metal-oxide-semiconductor N1.The other end of described second divider resistance R2 is suitable to input described second target electricity
Pressure Vss1.
The drain electrode of described 3rd input metal-oxide-semiconductor N1 is suitable to input described first object voltage Vdd1, described
The source electrode of the 3rd input metal-oxide-semiconductor N1 connects the drain electrode of the described first biasing metal-oxide-semiconductor N2 and as described
The output of the described reference voltage Vcm of generating circuit from reference voltage output.
The grid of described first biasing metal-oxide-semiconductor N2 is suitable to input makes the described first biasing metal-oxide-semiconductor N2 satisfy
With the first conducting voltage V1 of conducting, the source electrode of described first biasing metal-oxide-semiconductor N2 is suitable to input described the
Two target voltage Vss1.
Described first conducting voltage V1 is to make the voltage of the described first biasing metal-oxide-semiconductor N2 saturation conduction,
Concrete magnitude of voltage can be configured according to the threshold voltage of described first biasing metal-oxide-semiconductor N2.
For making described generating circuit from reference voltage output voltage values be described first object voltage Vdd1 and institute
State the reference voltage Vcm of the mean value of the second target voltage Vss1, described first divider resistance R1 and institute
State the resistance of the second divider resistance R2 according to Vss1+(Vdd1-Vss1) * r2/(r1+r2)=(Vdd1+Vss1)
/ 2+Vthn+(2*ID*L/μn*Cox* W)1/2Determining, wherein, r1 represents described first divider resistance R1's
Resistance, r2 represents the resistance of described second divider resistance R1, and Vthn represents the described 3rd input metal-oxide-semiconductor
The threshold voltage of N1, IDRepresenting the drain current of the described 3rd input metal-oxide-semiconductor, L represents the described 3rd
The channel length of input metal-oxide-semiconductor, μnRepresent the carrier mobility of the described 3rd input metal-oxide-semiconductor, Cox
Representing the grid unit are oxide layer electric capacity of the described 3rd input metal-oxide-semiconductor, W represents described 3rd input
The channel width of metal-oxide-semiconductor.
Source follower in described generating circuit from reference voltage also can use PMOS to realize, reference
The another kind of circuit diagram of the present embodiment generating circuit from reference voltage shown in Fig. 3.Described reference voltage produces
Circuit includes the 3rd divider resistance R3, the 4th divider resistance R4, the second biasing metal-oxide-semiconductor P1 and the 4th
Input metal-oxide-semiconductor P2, the concrete annexation between each device refers to Fig. 3, does not repeats them here.
Similar with to the description of Fig. 2, described second conducting voltage V2 is for making the described second biasing metal-oxide-semiconductor
The voltage of P1 saturation conduction, concrete magnitude of voltage can be according to the threshold voltage of described second biasing metal-oxide-semiconductor P1
Being configured, the resistance of described 3rd divider resistance R3 and described 4th divider resistance R4 is according to Vss1+
(Vdd1-Vss1) * r4/(r3+r4)=(Vdd1+Vss1)/2-Vthp-(2*ID*L/μp*Cox* W)1/2
Determining, wherein, r3 represents the resistance of described 3rd divider resistance R3, and r4 represents described 4th divider resistance
The resistance of R4, Vthp represents the threshold voltage of the described 4th input metal-oxide-semiconductor P2, IDRepresent the described 4th
The drain current of input metal-oxide-semiconductor, L represents the channel length of the described 4th input metal-oxide-semiconductor, μpRepresent
The carrier mobility of described 4th input metal-oxide-semiconductor, CoxRepresent the grid of the described 4th input metal-oxide-semiconductor
Unit are oxide layer electric capacity, W represents the channel width of the described 4th input metal-oxide-semiconductor.
It should be noted that be the driving force increasing described reference voltage Vcm, shown in Fig. 2 and Fig. 3
Generating circuit from reference voltage all include and followed by input metal-oxide-semiconductor and the biasing source electrode that forms of metal-oxide-semiconductor
Device, in other embodiments, described generating circuit from reference voltage also can not include source follower.This
Skilled person also can use the circuit of other forms, as long as can according to the spirit of the present embodiment
Realize that producing magnitude of voltage is described first object voltage Vdd1 and described second target voltage Vss2 average
The reference voltage Vcm of value.Therefore, the generating circuit from reference voltage in the present embodiment should not be used as right
The restriction of the present invention.
With reference to Fig. 4, the level shifting circuit of the embodiment of the present invention also includes that difference channel 41 and difference turn single
Terminal circuit 42.
Described difference channel 41 include the first constant current metal-oxide-semiconductor P3, the second constant current metal-oxide-semiconductor P4, first
Common mode sample resistance R5, the second common mode sample resistance R6, the first Differential Input metal-oxide-semiconductor N3, second
Differential Input metal-oxide-semiconductor N4 and the first tail current source metal-oxide-semiconductor N5.
Wherein, described first constant current metal-oxide-semiconductor P3 and described second constant current metal-oxide-semiconductor P4 is PMOS,
Described first Differential Input metal-oxide-semiconductor N3, described second Differential Input metal-oxide-semiconductor N4 and described first tail
Current source metal-oxide-semiconductor N5 is NMOS tube, described first common mode sample resistance R5 and described second common mode
The resistance of sample resistance R6 is identical.
The grid of described first constant current metal-oxide-semiconductor P3 connects the grid of described second constant current metal-oxide-semiconductor P4 simultaneously
Being suitable to input makes described first constant current metal-oxide-semiconductor P3 and described second constant current metal-oxide-semiconductor P4 saturation conduction
3rd conducting voltage V3, the source electrode of described first constant current metal-oxide-semiconductor P3 is suitable to input described first object electricity
Pressure Vdd1, the drain electrode of described first constant current metal-oxide-semiconductor P3 connects described first Differential Input metal-oxide-semiconductor N3
Drain electrode and as described difference channel 41 export described first driving signal Von the first output.
The source electrode of described second constant current metal-oxide-semiconductor P4 is suitable to input described first object voltage Vdd1, described
The drain electrode of the second constant current metal-oxide-semiconductor P4 connects drain electrode the conduct of described second Differential Input metal-oxide-semiconductor N4
Described difference channel 41 exports second output of described two driving signal Vop.
Described first constant current metal-oxide-semiconductor P3 and described second constant current metal-oxide-semiconductor P4 is current source loads,
Increase the first output of described difference channel 41 and the impedance of the second output so that it is become during circuit work
For high-impedance node, so that described first driving signal Von and described two driving signal Vop is with institute
Swing up and down centered on stating reference voltage Vcm.
One end of described first common mode sample resistance R5 connects the drain electrode of described first constant current metal-oxide-semiconductor P3,
The other end connects one end of described second common mode sample resistance R6 and inputs institute as described difference channel 41
State the input of reference voltage Vcm；The other end of described second common mode sample resistance R6 connects described the
The drain electrode of two constant current metal-oxide-semiconductor P4.
The grid of described first Differential Input metal-oxide-semiconductor N3 is suitable to input the first input signal Vin1, described
The source electrode of the first Differential Input metal-oxide-semiconductor N3 connect described second Differential Input metal-oxide-semiconductor N4 source electrode and
The drain electrode of described first tail current source metal-oxide-semiconductor N5.The grid of described second Differential Input metal-oxide-semiconductor N4
Be suitable to input the second input signal Vin2.
The grid of described first tail current source metal-oxide-semiconductor N5 is suitable to input makes described first tail current source MOS
4th conducting voltage V4 of pipe N5 saturation conduction, the source electrode of described first tail current source metal-oxide-semiconductor N5 is fitted
It is less than the first supply voltage Vss2 of described first object voltage Vdd1 in input.In the present embodiment,
Described first supply voltage Vss2 is ground voltage.
Described 4th conducting voltage V4 is to make the electricity of described first tail current source metal-oxide-semiconductor N5 saturation conduction
Pressure, concrete magnitude of voltage can be configured according to the threshold voltage of described first tail current source metal-oxide-semiconductor N5.
Described first tail current source metal-oxide-semiconductor N5 can improve the common-mode rejection ratio of described difference amplifier 41, meanwhile,
There is provided stable quiescent current, it is ensured that late-class circuit can steady operation.
Described difference turn single-end circuit 42 include the first load metal-oxide-semiconductor N6, second load metal-oxide-semiconductor N7,
First input metal-oxide-semiconductor P5 and the second input metal-oxide-semiconductor P6.
Wherein, described first load metal-oxide-semiconductor N6 and described second load metal-oxide-semiconductor N7 is NMOS
Pipe, described first input metal-oxide-semiconductor P5 and described second input metal-oxide-semiconductor P6 are PMOS.
The grid of described first input metal-oxide-semiconductor P5 is suitable to input the described first driving signal Von, described
The source electrode of the first input metal-oxide-semiconductor P5 is suitable to input described first object voltage Vdd1, described first input
The drain electrode of metal-oxide-semiconductor P5 connects the drain electrode of the described first load metal-oxide-semiconductor N6 and described second load MOS
The grid of pipe N7.
The grid of described second input metal-oxide-semiconductor P6 is suitable to input described two driving signal Vop, described
The source electrode of the second input metal-oxide-semiconductor P6 is suitable to input described first object voltage Vdd1, described second input
The drain electrode of metal-oxide-semiconductor P6 connects the drain electrode of the described second load metal-oxide-semiconductor N7 and described first load MOS
The grid of pipe N6, and, the drain electrode of described second input metal-oxide-semiconductor P6 is as generation output signal Vout
Output.
The source electrode of the source electrode of described first load metal-oxide-semiconductor N6 and described second load metal-oxide-semiconductor N7 is suitable to
Input described second target voltage Vss1.
In order to strengthen the driving force of described level shifting circuit, in the present embodiment, described level conversion
Circuit also includes being powered by described first object voltage Vdd1 and described second target voltage Vss2
CMOS inverter 43.
Described CMOS inverter 43 includes the first driving PMOS P7 and the first driving NMOS tube
N8.The grid of described first driving PMOS P7 and the described first grid driving NMOS tube N8
Connect and input as described CMOS inverter 43 input of described output signal Vout, described the
The source electrode of one driving PMOS P7 is suitable to input described first object voltage Vdd1, and described first drives
The drain electrode of PMOS P7 is connected as producing described defeated with the drain electrode of described first driving NMOS tube N8
Go out the output of the inversion signal Vout1 of signal Vout.The source electrode of described first driving NMOS tube N8
Be suitable to input described second target voltage Vss1.
For the principle of the level switching circuit of the embodiment of the present invention is better described, Fig. 5 gives described electricity
The signal waveforms during work of flat switching circuit.
With reference to Fig. 5, described first input signal Vin1 and described second input signal Vin2 are differential signal,
Described second input signal Vin2 can be entered inverter by described first input signal Vin1 and obtain.?
In the present embodiment, the high level voltage of described first input signal Vin1 is second source voltage Vdd2,
Low level voltage is described first supply voltage Vss2, and described second source voltage Vdd2 is not higher than described
First object voltage Vdd1.
When described first input signal Vin1 be high level signal, described second input signal Vin2 be low electricity
During ordinary mail, with reference to Fig. 4, described first Differential Input metal-oxide-semiconductor N3 conducting, described first constant current MOS
The drain electrode of pipe P3 is pulled to electronegative potential；Described second Differential Input metal-oxide-semiconductor N4 cut-off, described second
The drain electrode of constant current metal-oxide-semiconductor P4 is pulled to high potential.Therefore, described first driving signal Von is low electricity
Ordinary mail number, described two driving signal Vop is high level signal.
When described first input signal Vin1 is that low level signal, described second input signal Vin2 are electric for height
During ordinary mail, described first Differential Input metal-oxide-semiconductor N3 cut-off, described first constant current metal-oxide-semiconductor P3's
Drain electrode is pulled to high potential；Described second Differential Input metal-oxide-semiconductor N4 conducting, described second constant current MOS
The drain electrode of pipe P4 is pulled to electronegative potential.Therefore, described first driving signal Von is high level signal, institute
Stating two driving signal Vop is low level signal.
Owing to described reference voltage Vcm is by described first common mode sample resistance R5 and described second common mode
Sample resistance R6, is added in described difference channel 41 and exports first output of the described first driving signal Von
End and exporting between second output of described two driving signal Vop, accordingly, there exist relation:
Von-Vcm=Vcm-Vop, i.e. 2Vcm=Von+Vop.With reference to Fig. 5, described first driving signal Von
Centered on described reference voltage, point swings up and down with described two driving signal Vop.
Further, described reference voltage Vcm is described first object voltage Vdd1 and described second target electricity
Mean value, described first constant current metal-oxide-semiconductor P3 and the described second constant current metal-oxide-semiconductor P4 work of pressure Vss1
Make in saturation region, increase the first output of described difference channel 41 and the impedance of the second output, from
And make described first driving signal Von and described two driving signal Vop with described reference voltage Vcm be
Center swings up and down, therefore, by described first constant current metal-oxide-semiconductor P3 and described second constant current MOS
The pull-up effect of pipe P4 and described first Differential Input metal-oxide-semiconductor N3 and described second Differential Input MOS
The drop-down effect of pipe N4, the first driving signal Von and described second of described difference channel 41 output drives
The high level voltage of dynamic signal Vop close to described first object voltage Vdd1, low level voltage close to
Described second target voltage Vss1.
With continued reference to Fig. 4, as described above, the first driving signal Von of described difference channel 41 output and
The high level voltage of described two driving signal Vop is close to described first object voltage Vdd1, therefore,
The difference of the high level voltage with described first driving signal Von for the described first object voltage Vdd1 is less than institute
Stating the threshold voltage of the first input metal-oxide-semiconductor P5, described first object voltage Vdd1 drives with described first
The threshold voltage more than described first input metal-oxide-semiconductor P5 for the difference of the low level voltage of dynamic signal Von.
The threshold voltage of described second input metal-oxide-semiconductor P6 and the described first threshold value inputting metal-oxide-semiconductor P5
Voltage is equal, therefore, and the high level of described first object voltage Vdd1 and described first driving signal Von
The threshold voltage less than described second input metal-oxide-semiconductor P6 for the difference of voltage, described first object voltage
Vdd1 and the difference of the low level voltage of described first driving signal Von are more than described second input MOS
The threshold voltage of pipe P6.
When described first drives signal Von to be that low level signal, described two driving signal Vop are electric for height
During ordinary mail, described second input metal-oxide-semiconductor P6 cut-off, described first input metal-oxide-semiconductor P5 conducting,
The grid making the described second load metal-oxide-semiconductor N7 is pulled to high potential, and described second load metal-oxide-semiconductor N7 leads
Logical, described output signal Vout is low level signal, and magnitude of voltage is described second target voltage Vss1.With
When, described output signal Vout is that low level signal makes the described first load metal-oxide-semiconductor N6 turn off, and is formed
Positive feedback.
When described first drive signal Von be high level signal, described two driving signal Vop be low electricity
During ordinary mail, described first input metal-oxide-semiconductor P5 cut-off, described second input metal-oxide-semiconductor P6 conducting,
Described output signal Vout is high level signal, and magnitude of voltage is described first object voltage Vdd1.Meanwhile,
Described output signal Vout is that high level signal makes the described first load metal-oxide-semiconductor N6 turn on, described second
Load metal-oxide-semiconductor N7 cut-off, forms positive feedback.
Turn the effect of single-end circuit 42 through described difference, it is thus achieved that the high level voltage of output signal Vout
For described first object voltage Vdd1, low level voltage is described second target voltage Vss1, and, letter
Number rise/fall time shorten.
Further, described CMOS inverter 43 can strengthen the driving force of described output signal Vout,
The inversion signal Vout1(waveform producing described output signal Vout is not shown).
Embodiment 2
In the present embodiment, to realize high level is converted to carry out as a example by shift circuit under low level level
Explanation.The generating circuit from reference voltage of the present embodiment refers to embodiment 1, does not repeats them here.With reference to figure
6, the level shifting circuit of the embodiment of the present invention also includes that difference channel the 61st, difference turns single-end circuit 62 and
CMOS inverter 63.
Specifically, described difference channel 61 includes the second tail current source metal-oxide-semiconductor P8, the 3rd Differential Input
Metal-oxide-semiconductor P9, the 4th Differential Input metal-oxide-semiconductor P10, the 3rd common mode sample resistance R7, the 4th common mode take
Sample resistance R8, the 3rd constant current metal-oxide-semiconductor N9 and the 4th constant current metal-oxide-semiconductor N10.
Wherein, described second tail current source metal-oxide-semiconductor P8, the 3rd Differential Input metal-oxide-semiconductor P9 and the 4th
Differential Input metal-oxide-semiconductor P10 is PMOS, the 3rd constant current metal-oxide-semiconductor N9 and the 4th constant current MOS
Pipe N10 is NMOS tube, the resistance of the 3rd common mode sample resistance R7 and the 4th common mode sample resistance R8
Identical.
The grid of described second tail current source metal-oxide-semiconductor P8 is suitable to input the 5th conducting voltage V5, and described
Five conducting voltage V5 are to make the voltage of described second tail current source metal-oxide-semiconductor P8 saturation conduction, specifically electricity
Pressure value can be configured according to the threshold voltage of described second tail current source metal-oxide-semiconductor P8.
The grid of described 3rd constant current metal-oxide-semiconductor N9 and described 4th constant current metal-oxide-semiconductor N10 is suitable to input
6th conducting voltage V6, described 6th conducting voltage V6 is for making described 3rd constant current metal-oxide-semiconductor N9 and institute
Stating the voltage of the 4th constant current metal-oxide-semiconductor N10 saturation conduction, concrete magnitude of voltage can be according to described 3rd constant current
The threshold voltage of metal-oxide-semiconductor N9 and described 4th constant current metal-oxide-semiconductor N10 is configured.
Described difference turns single-end circuit 62 and includes the 3rd load metal-oxide-semiconductor P11, the 4th load metal-oxide-semiconductor
P12, the 5th input metal-oxide-semiconductor N11 and the 6th input metal-oxide-semiconductor N12.Wherein, described 5th input
Metal-oxide-semiconductor N11 and described 6th input metal-oxide-semiconductor N12 is NMOS tube, described 3rd load MOS
Pipe P11 and described 4th load metal-oxide-semiconductor P12 is PMOS.
Described CMOS inverter 63 includes the second driving PMOS P13 and the second driving NMOS tube
N13。
Described difference channel the 61st, described difference turns single-end circuit 62 and the electricity of described CMOS inverter 63
The description of line structure and circuit function reference implementation example 1 and the description of Fig. 6, do not repeat them here.
In the present embodiment, the high level voltage of described first input signal Vin1 is second source voltage
Vdd2, low level voltage is described first supply voltage Vss2, and described second source voltage Vdd2 is not low
In described first object voltage Vdd1.
Similar to Example 1, the first driving signal Von and described second of described difference channel 61 output
Drive the high level voltage of signal Vop close to described first object voltage Vdd1, therefore, described first
The high level voltage of signal Von and the difference of described second target voltage Vss1 is driven to be more than the described 5th defeated
Enter the threshold voltage of metal-oxide-semiconductor N11, the low level voltage of described first driving signal Von and described the
The threshold voltage less than described 5th input metal-oxide-semiconductor N11 for the difference of two target voltage Vss1.
The threshold voltage of described 6th input metal-oxide-semiconductor N12 and the described 5th threshold inputting metal-oxide-semiconductor N11
Threshold voltage is equal, therefore, and the high level voltage of described first driving signal Von and described second target electricity
The threshold voltage more than described 6th input metal-oxide-semiconductor N12 for the difference of pressure Vss1, described first drives letter
The low level voltage of number Von and the difference of described second target voltage Vss1 are less than described 6th input MOS
The threshold voltage of pipe N12.
The working signal waveform of the level shifting circuit of embodiment 2 refers to shown in Fig. 5, and specific works is former
Manage similar to Example 1, do not repeat them here.
In sum, the level shifting circuit that the present invention provides, is taken by the equal common mode of two resistance values
The reference voltage of the average that magnitude of voltage is first object voltage and the second target voltage is added in difference by sample resistance
Parallel circuit output first driving signal the first output and output two driving signal the second output it
Between, make the described first driving signal and described two driving signal point centered on described reference voltage upper and lower
Swing.Further, the high level voltage of described first driving signal and described two driving signal is close to institute
Stating first object voltage, low level voltage is close to described second target voltage.
Therefore, when described first object voltage and described second target voltage change, described reference voltage
Change therewith so that described first driving signal and described two driving signal low and high level with
With described first object voltage and described second target voltage change, can drive by described first object electricity
The difference that pressure and described second target voltage are powered turns single-end circuit, it is achieved the conversion between varying level,
Improve the versatility of level shifting circuit.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (8)
1. a level shifting circuit, it is characterised in that include:
Generating circuit from reference voltage, is suitable to obtain with reference to electricity according to first object voltage and the second target voltage
Pressure, described reference voltage is the mean value of described first object voltage and the second target voltage, described first
Target voltage is higher than described second target voltage；
The difference powered by described first object voltage and described second target voltage turns single-end circuit, including
The first load metal-oxide-semiconductor that cross-coupled positive feedback connects and the second load metal-oxide-semiconductor, first negative with described
Carrying the first input metal-oxide-semiconductor that metal-oxide-semiconductor connects, second being connected with described second load metal-oxide-semiconductor is defeated
Enter metal-oxide-semiconductor；The grid of described first input metal-oxide-semiconductor is suitable to input the first driving signal, and described second
The grid of input metal-oxide-semiconductor is suitable to input two driving signal, described first input metal-oxide-semiconductor and second defeated
The threshold voltage entering metal-oxide-semiconductor is equal；
Difference channel, is suitable to obtain according to the first input signal, the second input signal and described reference voltage
Described first driving signal and two driving signal, described first input signal and the second input signal are poor
Sub-signal, described first driving signal and two driving signal are differential signal, described first driving signal
High level voltage and described reference voltage difference be equal to described reference voltage and described first driving signal
The difference of low level voltage, described first driving signal be suitable to make the described first input metal-oxide-semiconductor conducting or
Cut-off.
2. level shifting circuit according to claim 1, it is characterised in that described reference voltage produces electricity
Road includes the first divider resistance, the second divider resistance, the 3rd input metal-oxide-semiconductor and the first biasing metal-oxide-semiconductor；
Wherein, one end of described first divider resistance is suitable to input described first object voltage, described first dividing potential drop
The other end of resistance connects one end of described second divider resistance and the grid of described 3rd input metal-oxide-semiconductor；
The other end of described second divider resistance is suitable to input described second target voltage；Described 3rd input MOS
The drain electrode of pipe is suitable to input described first object voltage, and the source electrode of described 3rd input metal-oxide-semiconductor connects described
First drain electrode biasing metal-oxide-semiconductor simultaneously exports described reference voltage as described generating circuit from reference voltage
Output；The grid of described first biasing metal-oxide-semiconductor is suitable to input makes the described first biasing metal-oxide-semiconductor saturated
First conducting voltage of conducting, the source electrode of described first biasing metal-oxide-semiconductor is suitable to input described second target electricity
Pressure；The relation that the resistance of described first divider resistance and described second divider resistance meets, according to Vss1+
(Vdd1-Vss1) * r2/ (r1+r2)=(Vdd1+Vss1)/2+Vthn+ (2*ID*L/μn*Cox*W)1/2
Determining, wherein, Vdd1 represents described first object voltage, and Vss1 represents described second target voltage, r1
Representing the resistance of described first divider resistance, r2 represents the resistance of described second divider resistance, and Vthn represents
The threshold voltage of described 3rd input metal-oxide-semiconductor, IDRepresent the drain current of the described 3rd input metal-oxide-semiconductor,
L represents the channel length of the described 3rd input metal-oxide-semiconductor, μnRepresent the load of the described 3rd input metal-oxide-semiconductor
Stream transport factor, CoxRepresent the grid unit are oxide layer electric capacity of the described 3rd input metal-oxide-semiconductor, W
Represent the channel width of the described 3rd input metal-oxide-semiconductor.
3. level shifting circuit according to claim 1, it is characterised in that described reference voltage produces electricity
Road includes the 3rd divider resistance, the 4th divider resistance, the second biasing metal-oxide-semiconductor and the 4th input metal-oxide-semiconductor；
Wherein, one end of described 3rd divider resistance is suitable to input described first object voltage, described 3rd dividing potential drop
The other end of resistance connects one end of described 4th divider resistance and the grid of described 4th input metal-oxide-semiconductor；
The other end of described 4th divider resistance is suitable to input described second target voltage；Described second biasing MOS
The grid of pipe is suitable to input the second conducting voltage making the described second biasing metal-oxide-semiconductor saturation conduction, and described the
The source electrode of two biasing metal-oxide-semiconductors is suitable to input described first object voltage, described second biasing metal-oxide-semiconductor
Drain electrode connects the source electrode of the described 4th input metal-oxide-semiconductor and exports institute as described generating circuit from reference voltage
State the output of reference voltage；The drain electrode of described 4th input metal-oxide-semiconductor is suitable to input described second target electricity
Pressure；The relation that the resistance of described 3rd divider resistance and described 4th divider resistance meets, according to Vss1+
(Vdd1-Vss1) * r4/ (r3+r4)=(Vdd1+Vss1)/2-Vthp-(2*ID*L/μp*Cox*W)1/2
Determining, wherein, Vdd1 represents described first object voltage, and Vss1 represents described second target voltage, r3
Representing the resistance of described 3rd divider resistance, r4 represents the resistance of described 4th divider resistance, and Vthp represents
The threshold voltage of described 4th input metal-oxide-semiconductor, IDRepresent the drain current of the described 4th input metal-oxide-semiconductor,
L represents the channel length of the described 4th input metal-oxide-semiconductor, μpRepresent the load of the described 4th input metal-oxide-semiconductor
Stream transport factor, CoxRepresent the grid unit are oxide layer electric capacity of the described 4th input metal-oxide-semiconductor, W
Represent the channel width of the described 4th input metal-oxide-semiconductor.
4. level shifting circuit according to claim 1, it is characterised in that described first load MOS
Pipe and described second load metal-oxide-semiconductor are NMOS tube, described first input metal-oxide-semiconductor and described second defeated
Entering metal-oxide-semiconductor is PMOS, described first object voltage and the described first high level voltage driving signal
Difference less than described first input metal-oxide-semiconductor threshold voltage, described first object voltage and described first
Drive the difference of low level voltage of signal more than the described first threshold voltage inputting metal-oxide-semiconductor.
5. level shifting circuit according to claim 4, it is characterised in that described difference channel includes
One constant current metal-oxide-semiconductor, the second constant current metal-oxide-semiconductor, the first common mode sample resistance, the second common mode sample resistance,
First Differential Input metal-oxide-semiconductor, the second Differential Input metal-oxide-semiconductor and the first tail current source metal-oxide-semiconductor；Its
In, described first common mode sample resistance is identical with the resistance of described second common mode sample resistance；Described first
The grid of constant current metal-oxide-semiconductor connects the grid of described second constant current metal-oxide-semiconductor and is suitable to input and makes described first
Constant current metal-oxide-semiconductor and the 3rd conducting voltage of described second constant current metal-oxide-semiconductor saturation conduction, described first perseverance
The source electrode of stream metal-oxide-semiconductor is suitable to input described first object voltage, the drain electrode of described first constant current metal-oxide-semiconductor
Connect the drain electrode of described first Differential Input metal-oxide-semiconductor and drive as described difference channel output described first
First output of dynamic signal；The source electrode of described second constant current metal-oxide-semiconductor is suitable to input described first object electricity
Pressure, the drain electrode of described second constant current metal-oxide-semiconductor connects the drain electrode of described second Differential Input metal-oxide-semiconductor and makees
The second output for the described two driving signal of described difference channel output；Described first common mode sampling electricity
One end of resistance connects the drain electrode of described first constant current metal-oxide-semiconductor, and the other end connects described second common mode sampling electricity
One end of resistance the input as the described reference voltage of described difference channel input；Described second common mode takes
The other end of sample resistance connects the drain electrode of described second constant current metal-oxide-semiconductor；Described first Differential Input MOS
The grid of pipe is suitable to input described first input signal, and the source electrode of described first Differential Input metal-oxide-semiconductor connects
The source electrode of described second Differential Input metal-oxide-semiconductor and the drain electrode of described first tail current source metal-oxide-semiconductor；Described
The grid of the second Differential Input metal-oxide-semiconductor is suitable to input described second input signal；Described first tail current source
The grid of metal-oxide-semiconductor is suitable to input the 4th electric conduction making described first tail current source metal-oxide-semiconductor saturation conduction
Pressure, the source electrode of described first tail current source metal-oxide-semiconductor is suitable to input less than the first of described first object voltage
Supply voltage.
6. level shifting circuit according to claim 1, it is characterised in that described first load MOS
Pipe and described second load metal-oxide-semiconductor are PMOS, described first input metal-oxide-semiconductor and described second defeated
Entering metal-oxide-semiconductor is NMOS tube, the high level voltage of described first driving signal and described second target electricity
The difference of pressure is more than the threshold voltage of described first input metal-oxide-semiconductor, the low level of described first driving signal
Voltage and the difference of described second target voltage are less than the described first threshold voltage inputting metal-oxide-semiconductor.
7. level shifting circuit according to claim 6, it is characterised in that described difference channel includes
Two tail current source metal-oxide-semiconductors, the 3rd Differential Input metal-oxide-semiconductor, the 4th Differential Input metal-oxide-semiconductor, the 3rd
Common mode sample resistance, the 4th common mode sample resistance, the 3rd constant current metal-oxide-semiconductor and the 4th constant current metal-oxide-semiconductor；
Wherein, described 3rd common mode sample resistance is identical with the resistance of described 4th common mode sample resistance, and described
The grid of two tail current source metal-oxide-semiconductors is suitable to input makes described second tail current source metal-oxide-semiconductor saturation conduction
5th conducting voltage, the source electrode of described second tail current source metal-oxide-semiconductor is suitable to input and is higher than described second target
The second source voltage of voltage, it is defeated that the drain electrode of described second tail current source metal-oxide-semiconductor connects described 3rd difference
Enter the source electrode of metal-oxide-semiconductor and the source electrode of described 4th Differential Input metal-oxide-semiconductor；Described 3rd Differential Input
The grid of metal-oxide-semiconductor is suitable to input described first input signal, the leakage of described 3rd Differential Input metal-oxide-semiconductor
Pole connects the drain electrode of described 3rd constant current metal-oxide-semiconductor and drives as described difference channel output described first
First output of signal；The grid of described 4th Differential Input metal-oxide-semiconductor is suitable to input the described second input
Signal, the drain electrode of described 4th Differential Input metal-oxide-semiconductor connects the drain electrode of described 4th constant current metal-oxide-semiconductor simultaneously
The second output as the described two driving signal of described difference channel output；Described 3rd common mode sampling
One end of resistance connects the drain electrode of described 3rd Differential Input metal-oxide-semiconductor, and the other end connects described 4th common mode
One end of sample resistance the input as the described reference voltage of described difference channel input；Described 4th
The other end of common mode sample resistance connects the drain electrode of described 4th Differential Input metal-oxide-semiconductor；Described 3rd constant current
The grid of metal-oxide-semiconductor connects the grid of described 4th constant current metal-oxide-semiconductor and is suitable to input and makes described 3rd constant current
Metal-oxide-semiconductor and the 6th conducting voltage of described 4th constant current metal-oxide-semiconductor saturation conduction, described 3rd constant current
The source electrode of metal-oxide-semiconductor is suitable to input described second target voltage；The source electrode of described 4th constant current metal-oxide-semiconductor is fitted
In described second target voltage of input.
8. the level shifting circuit according to any one of claim 1 to 7, it is characterised in that also include by
The CMOS inverter that described first object voltage and described second target voltage are powered, described CMOS is anti-
The input of phase device connects the connection end of the described second load metal-oxide-semiconductor and described second input metal-oxide-semiconductor.
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| CN104679082B (en) * | 2013-11-29 | 2016-03-02 | 展讯通信（上海）有限公司 | A kind of adaptive circuit and voltage signal amplifier |
| CN104579256B (en) * | 2014-12-23 | 2017-05-24 | 昆山锐芯微电子有限公司 | Level switching circuit and device |
| CN104682946B (en) * | 2015-03-04 | 2017-10-17 | 中国科学院微电子研究所 | A kind of differential signal turns single-ended signal circuit |
| US9621138B1 (en) * | 2015-11-05 | 2017-04-11 | Nxp B.V. | Slew control using a switched capacitor circuit |
| US9536593B1 (en) * | 2016-05-23 | 2017-01-03 | Qualcomm Incorporated | Low power receiver with wide input voltage range |
| CN106130536B (en) * | 2016-06-20 | 2019-06-14 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
| DE102017213732A1 (en) * | 2017-08-08 | 2019-02-14 | Robert Bosch Gmbh | Input stage for an LVDS receiver circuit |
| CN108616269B (en) * | 2018-07-27 | 2023-12-29 | 无锡安趋电子有限公司 | Low-working-voltage downlink level shift circuit |
| CN110958031B (en) * | 2019-12-26 | 2021-05-07 | 上海贝岭股份有限公司 | RS485 receiver circuit, integrated circuit and transceiver |
| CN112367067B (en) * | 2021-01-12 | 2021-04-02 | 棱晶半导体(南京)有限公司 | Differential drive circuit of floating isolating switch |
| CN115224936A (en) * | 2021-04-15 | 2022-10-21 | 瑞昱半导体股份有限公司 | Voltage conversion circuit with self-adaptive mechanism |
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| US5446400A (en) * | 1994-11-07 | 1995-08-29 | Motorola Inc. | GTL compatible BICMOS input stage |
| CN101060324A (en) * | 2007-04-06 | 2007-10-24 | 中兴通讯股份有限公司 | A differential signal interface circuit |
| CN101179269A (en) * | 2006-11-10 | 2008-05-14 | 中兴通讯股份有限公司 | Converting circuit of implementing difference level signal to single end level signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7312636B2 (en) * | 2006-02-06 | 2007-12-25 | Mosaid Technologies Incorporated | Voltage level shifter circuit |
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2013
- 2013-07-10 CN CN201310288505.8A patent/CN103346773B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5446400A (en) * | 1994-11-07 | 1995-08-29 | Motorola Inc. | GTL compatible BICMOS input stage |
| CN101179269A (en) * | 2006-11-10 | 2008-05-14 | 中兴通讯股份有限公司 | Converting circuit of implementing difference level signal to single end level signal |
| CN101060324A (en) * | 2007-04-06 | 2007-10-24 | 中兴通讯股份有限公司 | A differential signal interface circuit |
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| CN103346773A (en) | 2013-10-09 |
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