CN106230432B - High-speed signal level conversion circuit with low power consumption and ultra wide bandwidth - Google Patents
High-speed signal level conversion circuit with low power consumption and ultra wide bandwidth Download PDFInfo
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- CN106230432B CN106230432B CN201610767815.1A CN201610767815A CN106230432B CN 106230432 B CN106230432 B CN 106230432B CN 201610767815 A CN201610767815 A CN 201610767815A CN 106230432 B CN106230432 B CN 106230432B
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Abstract
The invention discloses a high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth, which comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and bias current. The invention has the beneficial effects that: the circuit has a certain current driving capability, can realize the conversion of a high-speed signal level from a lower/higher common-mode voltage level to a higher/lower common-mode level circuit, can directly transmit a high-speed signal to a transmitting end, provides an effective direct-current common-mode voltage, and can provide a high-speed signal with ultra-wide bandwidth on the premise of low power consumption, wherein the low power consumption is only about 600uA, and the ultra-wide bandwidth can reach 50GHZ or even 100GHZ.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth.
Background
The high-speed signal level converter converts a high-speed signal from a common-mode voltage to another common-mode voltage so as to meet the common-mode voltage requirement of a signal receiving end, and particularly in a high-speed signal interface, when the common-mode level of a high-speed differential signal sent by a sending end exceeds the common-mode voltage input range of the receiving end, the high-speed signal level conversion circuit is required to convert the common-mode level of the signal sent by the sending end into the common-mode level range of the receiving end.
In the existing high-speed signal level conversion circuit, the most common is a passive RC high-pass filter, as shown in fig. 1, the high-speed differential input signal can be effectively transmitted to the output end, and the common mode level of the output end is any VREF value and cannot be interfered by the common mode level of the input end. However, once the cut-off frequency of the input low-frequency signal is limited by the values of the resistor R and the capacitor C in the figure, the bandwidth of the input signal is far smaller than the cut-off frequency of the RC, the input signal is filtered by the high-pass filter, and the output voltage is only maintained at the VREF value, so that the circuit can only transmit the high-frequency signal higher than the cut-off frequency thereof and cannot transmit the low-frequency signal, and the maximum limitation of the circuit is that the output end has no driving capability, and if a load needs a certain current, the output common-mode voltage of the circuit is greatly influenced.
In addition, in the conventional high-speed signal level conversion circuit, as shown in fig. 2 and 3, the output bandwidth of the most commonly used active level conversion circuit is affected by the output impedance and the load capacitance, so that to increase the bandwidth of the circuit, the resistance value in fig. 2 must be reduced, and thus the power consumption is increased, and for the circuit in fig. 3, the current source current needs to be increased to reduce the on-resistance of the current source to increase the bandwidth, which is a cost of sacrificing the power consumption, and under the requirement of the upper GHZ frequency band, the circuit needs several milliamperes or even tens milliamperes.
Name interpretation:
NMOS (N-type Metal-Oxide-Semiconductor);
PMOS (P-type metal oxide semiconductor), which refers to an n-type substrate, a P-channel, and a MOS tube for transporting current by hole flow
DIODE: a diode;
BJT (bipolar junction transistor-BJT);
NPN: an N-type bipolar transistor;
PNP: p-type bipolar transistor.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth, which can realize the conversion of a high-speed signal level from a lower/higher common-mode voltage level to a higher/lower common-mode level circuit, and the circuit has certain current driving capability.
The invention is realized by the following technical scheme: a high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and bias current;
the drain electrode of the first MOS tube is grounded, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, and the grid electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first capacitor and the grid electrode of the sixth MOS tube through a fourth capacitor respectively; similarly, the drain electrode of the second MOS tube is grounded, the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through the second resistor and the second capacitor, and the grid electrode of the second MOS tube is connected with the grid electrode of the fifth MOS tube through the third capacitor; the grid electrodes of the first MOS tube and the second MOS tube are respectively differential input ends VIP and VIN; the drains of the fifth MOS tube and the sixth MOS tube are respectively a differential output end VOP and a differential output end VON;
the grid electrode of the fifth MOS tube is connected to the grid electrode of the sixth MOS tube through a fourth resistor and a third resistor respectively, the VBIAS1 shared by the third resistor and the fourth resistor is a bias voltage, the seventh MOS tube is a current mirror tube, currents are provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube respectively, the grid electrode of the seventh MOS tube is connected with the drain electrode, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected together through a fourth capacitor; the drain electrode of the seventh MOS tube is grounded through bias current;
the fifth MOS tube and the sixth MOS tube are used for bias of the KICKER circuit, a KICKER core circuit is formed by the fifth MOS tube and the sixth MOS tube, the first MOS tube, the second MOS tube, the first resistor and the second resistor, a feed-forward capacitance circuit is formed by the second capacitor and the first capacitor, and a high-pass circuit is formed between the third resistor and the fourth resistor, the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube.
Preferably, the drain electrode of the seventh MOS transistor is grounded through a bias current, the gates of the seventh MOS transistor, the third MOS transistor and the fourth MOS transistor are sequentially connected, the source electrode of the seventh MOS transistor, the source electrode of the third MOS transistor and the source electrode of the fourth MOS transistor are sequentially connected and connected with a power supply, and the drain electrode of the third MOS transistor is also connected with the drain electrode of the fourth MOS transistor through a fourth capacitor.
Preferably, the first resistor and the second resistor can be replaced by NMOS, PMOS, DIODE, PNP or NPN at the same time for the purpose of level conversion.
Preferably, the third MOS transistor, the fourth MOS transistor and the seventh MOS transistor can be replaced by 2 cascade current mirrors or PNP triode current mirrors at the same time, and for the input pair of transistors, the first MOS transistor and the second MOS transistor can be replaced by PNP transistor to improve the process accuracy thereof.
Preferably, the PNP transistor specifically includes a first triode and a second triode, an emitter of the first triode is connected to a drain electrode of the fifth MOS transistor through a first resistor, a base of the first triode is connected to one end of the first capacitor and one end of the fourth capacitor respectively, and a collector of the first triode is grounded.
Preferably, the emitter of the second triode is connected to the drain of the sixth MOS transistor through a second resistor, the collector of the second triode is grounded, and the base of the second triode is connected to the gate of the fifth MOS transistor through a third capacitor and connected to the drain of the sixth MOS transistor through a first capacitor, respectively.
The invention also provides another technical scheme, which comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first resistor, a second resistor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube is grounded, and the source electrode of the first MOS tube is connected to the drain electrode of the fifth MOS tube through a first resistor; similarly, the drain electrode of the second MOS tube is grounded, and the source electrode of the second MOS tube is connected to the drain electrode of the sixth MOS tube through a second resistor; the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube and the grid electrode shared end VBIAS1 of the sixth MOS tube are bias voltages, the seventh MOS tube is a current mirror tube, currents are respectively provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube, the grid electrode of the seventh MOS tube is connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube, and the drain electrode of the seventh MOS tube is grounded through bias currents.
The invention also provides another technical scheme, which comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor, a second capacitor, a first resistor, a second resistor, a first feedforward capacitor, a second feedforward capacitor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube is grounded, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, and the grid electrode of the first MOS tube is connected with the positive end of the input differential signal; similarly, the drain electrode of the second MOS tube is grounded, the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through the second resistor, the grid electrode of the second MOS tube is connected with the negative end of the input differential signal, the two ends of the first capacitor are respectively connected with the grid electrode of the first MOS tube and the drain electrode of the fifth MOS tube, and the two ends of the second capacitor are respectively connected with the grid electrode of the second MOS tube and the drain electrode of the sixth MOS tube;
the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube and the grid electrode shared end VBIAS1 of the sixth MOS tube are bias voltages, the seventh MOS tube is a current mirror tube, currents are respectively provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube, the grid electrode of the seventh MOS tube is connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube, and the drain electrode of the seventh MOS tube is grounded through bias currents.
The invention also provides another technical scheme, which comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube is grounded, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, and the grid electrode of the first MOS tube is connected with the grid electrode of the sixth MOS tube through a fourth capacitor; similarly, the drain electrode of the second MOS tube is grounded, the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through the second resistor, and the grid electrode of the second MOS tube is connected with the grid electrode of the fifth MOS tube through the third capacitor;
the grid electrode of the fifth MOS tube is connected to the grid electrode of the sixth MOS tube through a fourth resistor and a third resistor respectively, the VBIAS1 shared by the third resistor and the fourth resistor is a bias voltage, the seventh MOS tube is a current mirror tube, currents are provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube respectively, the grid electrode of the seventh MOS tube is connected to the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected through a fifth capacitor; the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube, the grid electrode of the seventh MOS tube is connected with the drain electrode, and the drain electrode of the seventh MOS tube is grounded through bias current.
The invention also provides another technical scheme, which comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are both connected with power supply voltage, the grid electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first capacitor, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, the grid electrode of the first MOS tube is connected with the grid electrode of the sixth MOS tube through a fourth capacitor, and the grid electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through a second capacitor and the grid electrode of the fifth MOS tube through a third capacitor respectively;
the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through a second resistor, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube through a fourth resistor and a third resistor, the common end VBIAS1 of the third resistor and the fourth resistor is a bias voltage, the source electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, the source electrode of the sixth MOS tube is connected with the drain electrode of the fourth MOS tube, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected through a fourth capacitor;
the grid electrodes of the seventh MOS tube are respectively connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the drain electrode of the seventh MOS tube is connected with the grid electrode of the seventh MOS tube and is connected with a power supply through bias current, and the source electrodes of the third MOS tube, the fourth MOS tube and the seventh MOS tube are grounded.
Compared with the prior art, the invention has the following beneficial effects: a high-speed signal level converter with feedforward capacitor and forward exciting circuit has a certain current driving capability, which can realize the conversion of high-speed signal level from a lower/higher common-mode voltage level to a higher/lower common-mode level circuit, which utilizes the low impedance characteristic of capacitor under high frequency to directly transmit high-speed signal to transmitting terminal, providing an effective DC common-mode voltage, and providing ultra-wide bandwidth high-speed signal under the premise of low power consumption, the low power consumption is only about 600uA, and the ultra-wide bandwidth can reach 50GHZ or even 100GHZ. In addition, the circuit provides current driving capability, and can effectively drive a current load, especially when a certain base current is required for driving a BJT input end in a BCD process.
Drawings
FIG. 1 is a differential RC high pass filter;
FIG. 2 shows an active signal level shifter circuit (resistor is a load);
FIG. 3 shows an active signal level shifter circuit (current is load);
fig. 4 is a whole circuit configuration diagram of embodiment 1;
fig. 5 is a whole circuit configuration diagram of embodiment 2;
fig. 6 is a whole circuit configuration diagram of embodiment 3;
fig. 7 is a general active level shifter circuit (CMOS source follower) of embodiment 4;
FIG. 8 is an AC gain curve of a normal level shifter circuit;
FIG. 9 is a level shifter circuit with feedforward capacitor according to embodiment 5;
FIG. 10 is a graph of the output AC gain of a level shifter circuit with a feedforward capacitor;
FIG. 11 is a level shifter circuit with feed forward excitation (KICKER) according to example 6;
FIG. 12 is a graph of gain with feed forward excitation (KICKER) level shift circuit;
FIG. 13 is a graph of overall circuit gain;
fig. 14 is a high-to-low circuit of embodiment 7.
Detailed Description
The present invention is further described below with reference to the accompanying drawings.
The overall circuit configuration of the present invention is shown in connection with fig. 4 to 14, and is exemplified as follows:
embodiment one:
as shown in fig. 4, the circuit composition: bias current I0; the current mirror formed by the PMOS tube second MOS tube P2, the third MOS tube P3 and the fourth MOS tube P4 provides bias current for the circuit, and the current flowing through the third MOS tube P3 and the fourth MOS tube P4 increases along with the increase of the current loads of the output VOP and the VON; the P5 and P6PMOS tubes are used for bias of the KICKER circuit, and form a KICKER core circuit together with the resistor R2/R3, the capacitor C2/C3 and the capacitor C4, and the circuit needs a DC bias voltage VBIAS1 to ensure that PMOSP5 and P6 work in a saturation region when the circuit is in a DC working state; the PMOS tubes P1 and P2 are used for forming a common source follower and resistors R1/R2 to form a level conversion circuit, and the common mode level of an input signal is improved to VCMIN+VGS+IR output, wherein I is current flowing through the resistors, VGS is gate-source voltage of the PMOS tubes P1 and P2, and VCMIN is input common mode voltage with the value of (VIP+VIN)/2; the first capacitor C1 and the second capacitor C2 form a feedforward capacitor circuit.
The MOS transistor comprises a first MOS transistor P1, a second MOS transistor P2, a third MOS transistor P3, a fourth MOS transistor P4, a fifth MOS transistor P5, a sixth MOS transistor P6, a seventh MOS transistor P7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and bias current IO; the drain electrode of the first MOS tube P1 is grounded, the source electrode of the first MOS tube P1 is connected to the drain electrode of the fifth MOS tube P5 through a first resistor R1, and the grid electrode of the first MOS tube P1 is connected to the drain electrode of the fifth MOS tube P5 through a first capacitor C1 and connected to the grid electrode of a sixth MOS tube P6 through a fourth capacitor C4 respectively; similarly, the drain electrode of the second MOS tube P2 is grounded, the source stage of the second MOS tube P2 is connected to the drain electrode of the sixth MOS tube P6 through the second resistor R2 and the second capacitor C2, and the grid electrode of the second MOS tube P2 is connected to the grid electrode of the fifth MOS tube P5 through the third capacitor C3.
The grid electrode of the fifth MOS tube P5 is connected to the grid electrode of the sixth MOS tube P6 through a fourth resistor R4 and a third resistor R3 respectively, the shared end VBIAS1 of the third resistor R3 and the fourth resistor R4 is a bias voltage, the seventh MOS tube P7 is a current mirror tube, currents are provided for the fifth MOS tube and the sixth MOS tube respectively through the third MOS tube and the fourth MOS tube, the drain electrodes of the third MOS tube and the fourth MOS tube are connected to the source electrodes of the fifth MOS tube and the sixth MOS tube respectively, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected together through a fourth capacitor C4; the drain electrode of the seventh MOS tube P7 is grounded through bias current;
the fifth MOS tube P5 and the sixth MOS tube P6 are used for bias of the KICKER circuit, a KICKER core circuit is formed by the fifth MOS tube P5 and the sixth MOS tube P6 and the second resistor R2, the third resistor R3, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, the first MOS tube P1, the second MOS tube P2, the first resistor R1 and the second resistor R2 form a level conversion circuit, the second capacitor C2 and the first capacitor C1 form a feedforward capacitor circuit, and a high-pass circuit is formed between the third capacitor C3 and the fourth resistor R4, and between the third capacitor R3 and the fourth capacitor C4 and between the grid of the fifth MOS tube P5 and the grid of the sixth MOS tube.
Further, the drain electrode of the seventh MOS transistor P7 is grounded through the bias current IO, the gate electrode of the seventh MOS transistor P7, the gate electrode of the third MOS transistor P3 and the gate electrode of the fourth MOS transistor P4 are sequentially connected, the source electrode of the seventh MOS transistor P7, the source electrode of the third MOS transistor P3 and the source electrode of the fourth MOS transistor P4 are sequentially connected, and the drain electrode of the third MOS transistor P3 is also connected to the drain electrode of the fourth MOS transistor P4 through the fourth capacitor C4.
Embodiment two:
the first resistor R1 and the second resistor R2 in the circuit of fig. 4 may be replaced with NMOS, PMOS, DIODE, PNP or NPN simultaneously for level shifting purposes, as indicated by the arrow in fig. 5 below.
Embodiment III:
the third MOS transistor P3, the fourth MOS transistor P4 and the fifth MOS transistor P5 of the current mirror may be replaced by 2 cascades or PNP to form a current mirror at the same time under the condition of higher power supply, and for the input pair transistor, the first MOS transistor P1 and the second MOS transistor P2 may be replaced by PNP transistor to improve the process accuracy, as shown in fig. 6. And if a higher output level is desired, the resistors, MOS transistors or DIODE or BJT transistors can be selected for different combinations and output in a cascade manner.
Embodiment four:
first, if the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5, and the second resistor R2 and the third resistor R3 are not considered, the circuit result is shown in fig. 7. This circuit is a common level shifter circuit, i.e., a CMOS source follower, which has a low frequency circuit configuration with input to output bandwidths as shown in fig. 8 below. The total current consumption of the circuit design is 600uA, which is characterized by a low-pass characteristic, as can be seen in FIG. 8, with a frequency of-3 dB around 1 Ghz. It cannot transmit signals of 5G or even more than 10G.
Fifth embodiment:
next, if the feedforward first capacitor C1 and the second capacitor C2 in fig. 4 are added to the circuit, the structure thereof is as shown in fig. 9. The corresponding ac gain profile is shown in fig. 10. As can be seen in fig. 10, this circuit basically achieves an ac gain of ultra wide bandwidth gain, but in the mid-band, the gain of the mid-band is waved due to the 2 paths formed by the gain of the normal level shift circuit path in fig. 10 and the gain of the feedforward first capacitor C1 and the second capacitor C2 paths in fig. 9, with the peak and trough differences of 83mdB, and this circuit causes the gain to be significantly higher at 100Ghz than at low frequencies.
Example six:
if this circuit only retains the capacitance of the feed forward excitation (KICKER) section, the second capacitance C2, the third capacitance C3, the fourth capacitance C4, and the second resistor R2 and the third resistor R3, the circuit is as shown in fig. 11; for the second capacitor C2 and the third capacitor C3, and the second resistor R2 and the third resistor R3, the third resistor R3 and the second capacitor C2 thereof, the second resistor R2 and the third capacitor C3 form a high-pass characteristic for the gate path of the signal to the fifth MOS transistor P5 and the sixth MOS transistor P6. The effect is that when the signal is input from the input end, if a differential signal from 0 to 1 is obtained at this time, when the VIP rising edge arrives, the VIN arrives at the falling edge, at this time, the gate voltage of the fifth MOS transistor P5 is influenced by the AC current of the second capacitor C2, there is a transient pull-down process, the gate voltage of the sixth MOS transistor P6 is influenced by the third capacitor C3, there is a transient rise process, the fifth MOS transistor P5 causes a transient increase of the gate-source voltage of the fifth MOS transistor P5 due to the decrease of the gate voltage, and a high-frequency low-impedance current path is formed due to the fourth capacitor C4, so that the transient current flowing through the fifth MOS transistor P5 increases, and the transient current flowing through the sixth MOS transistor P6 decreases, thereby increasing the high-frequency gain of the circuit at this time.
The circuit is subjected to alternating current gain analysis, and the gain curve of the circuit can be seen as shown in figure 12; as can be seen from fig. 12, the circuit of fig. 11 significantly increases the bandwidth of the circuit of fig. 4. Meanwhile, due to the existence of a fast path (KICKER) and a slow path (common source follower), zero points are introduced into the circuit, so that a part with gain larger than direct current gain is caused, and the pole-zero position of the gain can be effectively adjusted by adjusting the proportion parameters of the KICKER part circuit so as to compensate the wave gain part in FIG. 10 and reduce the change of the wave gain part. Fig. 13 is a gain curve of the overall circuit.
It can be seen in fig. 13 that although the gain has a wavy shape, its peak is only increased by 10mdB compared to the dc gain, and the trough is only reduced by-4.3 mdB compared to the dc gain, the overall gain variation is only 14.3mdB, and only a 0.165% variation of the input signal is introduced, achieving a variation that is completely negligible in most applications. And the whole gain tends to be smooth in the range from direct current to 100G. And the entire circuit consumes only 600uA of current.
Embodiment seven:
the circuit is a process of converting a low common-mode voltage into a high common-mode voltage, and can also form a process of converting the high common-mode voltage into the low common-mode voltage. As shown in fig. 14. The principle is the same as in fig. 4. The device can also be replaced with the corresponding alternative of fig. 4.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the invention.
Claims (10)
1. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and bias current;
the drain electrode of the first MOS tube is grounded, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, and the grid electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first capacitor and the grid electrode of the sixth MOS tube through a fourth capacitor respectively; similarly, the drain electrode of the second MOS tube is grounded, the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through the second resistor and the second capacitor, and the grid electrode of the second MOS tube is connected with the grid electrode of the fifth MOS tube through the third capacitor; the grid electrodes of the first MOS tube and the second MOS tube are respectively differential input ends VIP and VIN; the drains of the fifth MOS tube and the sixth MOS tube are respectively a differential output end VOP and a differential output end VON;
the grid electrode of the fifth MOS tube is connected to the grid electrode of the sixth MOS tube through a fourth resistor and a third resistor respectively, the VBIAS1 shared by the third resistor and the fourth resistor is a bias voltage, the seventh MOS tube is a current mirror tube, currents are provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube respectively, the grid electrode of the seventh MOS tube is connected with the drain electrode, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected together through a fourth capacitor; the drain electrode of the seventh MOS tube is grounded through bias current;
the fifth MOS tube and the sixth MOS tube are used for bias of the KICKER circuit, a KICKER core circuit is formed by the fifth MOS tube and the sixth MOS tube, the first MOS tube, the second MOS tube, the first resistor and the second resistor, a feed-forward capacitance circuit is formed by the second capacitor and the first capacitor, and a high-pass circuit is formed between the third resistor and the fourth resistor, the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube.
2. A high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth as recited in claim 1, wherein: the drain electrode of the seventh MOS tube is grounded through bias current, the grid electrode of the seventh MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube are sequentially connected, the source electrode of the seventh MOS tube, the source electrode of the third MOS tube and the source electrode of the fourth MOS tube are sequentially connected and connected with a power supply, and the drain electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube through a fourth capacitor.
3. A high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth according to claim 1 or 2, wherein the first resistor and the second resistor can be replaced by NMOS, PMOS, DIODE, PNP or NPN simultaneously for the purpose of level conversion.
4. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth according to claim 1 or 2, wherein the third MOS transistor, the fourth MOS transistor and the seventh MOS transistor can be replaced by 2 cascade current mirrors or PNP triode current mirrors at the same time, and for the input pair of transistors, the first MOS transistor and the second MOS transistor can be replaced by PNP transistor to improve the process accuracy.
5. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth according to claim 4, wherein the PNP transistor specifically comprises a first triode and a second triode, an emitter of the first triode is connected to a drain of the fifth MOS transistor through a first resistor, a base of the first triode is connected to one end of the first capacitor and one end of the fourth capacitor respectively, and a collector of the first triode is grounded.
6. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth according to claim 5, wherein the emitter of the second triode is connected to the drain of the sixth MOS transistor through a second resistor, the collector of the second triode is grounded, and the base of the second triode is connected to the gate of the fifth MOS transistor through a third capacitor and the drain of the sixth MOS transistor through a first capacitor respectively.
7. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first resistor, a second resistor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube is grounded, and the source electrode of the first MOS tube is connected to the drain electrode of the fifth MOS tube through a first resistor; similarly, the drain electrode of the second MOS tube is grounded, and the source electrode of the second MOS tube is connected to the drain electrode of the sixth MOS tube through a second resistor;
the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube and the grid electrode shared end VBIAS1 of the sixth MOS tube are bias voltages, the seventh MOS tube is a current mirror tube, currents are respectively provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube, the grid electrode of the seventh MOS tube is connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube, and the drain electrode of the seventh MOS tube is grounded through bias currents.
8. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor, a second capacitor, a first resistor, a second resistor, a first feedforward capacitor, a second feedforward capacitor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube is grounded, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, and the grid electrode of the first MOS tube is connected with the positive end of the differential signal; similarly, the drain electrode of the second MOS tube is grounded, the source electrode of the second MOS tube passes through the drain electrode of the sixth MOS tube of the second resistor, the grid electrode of the second MOS tube is connected with the negative end of the differential signal, the two ends of the first capacitor are respectively connected with the grid electrode of the first MOS tube and the drain electrode of the fifth MOS tube, and the two ends of the second capacitor are respectively connected with the grid electrode of the second MOS tube and the drain electrode of the sixth MOS tube;
the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube and the grid electrode shared end VBIAS1 of the sixth MOS tube are bias voltages, the seventh MOS tube is a current mirror tube, currents are respectively provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube, the grid electrode of the seventh MOS tube is connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube, and the drain electrode of the seventh MOS tube is grounded through bias currents.
9. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube is grounded, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, and the grid electrode of the first MOS tube is connected with the grid electrode of the sixth MOS tube through a fourth capacitor; similarly, the drain electrode of the second MOS tube is grounded, the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through the second resistor, and the grid electrode of the second MOS tube is connected with the grid electrode of the fifth MOS tube through the third capacitor;
the grid electrode of the fifth MOS tube is connected to the grid electrode of the sixth MOS tube through a fourth resistor and a third resistor respectively, the VBIAS1 shared by the third resistor and the fourth resistor is a bias voltage, the seventh MOS tube is a current mirror tube, currents are provided for the fifth MOS tube and the sixth MOS tube through the third MOS tube and the fourth MOS tube respectively, the grid electrode of the seventh MOS tube is connected to the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected through a fifth capacitor; the drain electrode of the third MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube, the grid electrode of the seventh MOS tube is connected with the drain electrode, and the drain electrode of the seventh MOS tube is grounded through bias current.
10. The high-speed signal level conversion circuit with low power consumption and ultra wide bandwidth is characterized by comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, bias current, differential input ends VIP and VIN and differential output ends VOP and VON;
the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are both connected with power supply voltage, the grid electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first capacitor, the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube through a first resistor, the grid electrode of the first MOS tube is connected with the grid electrode of the sixth MOS tube through a fourth capacitor, and the grid electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through a second capacitor and the grid electrode of the fifth MOS tube through a third capacitor respectively;
the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube through a second resistor, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube through a fourth resistor and a third resistor, the common end VBIAS1 of the third resistor and the fourth resistor is a bias voltage, the source electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, the source electrode of the sixth MOS tube is connected with the drain electrode of the fourth MOS tube, and the source electrodes of the fifth MOS tube and the sixth MOS tube are connected through a fourth capacitor; the grid electrodes of the seventh MOS tube are respectively connected with the grid electrodes of the third MOS tube and the fourth MOS tube, the drain electrode of the seventh MOS tube is connected with the grid electrode of the seventh MOS tube and is connected with a power supply through bias current, and the source electrodes of the third MOS tube, the fourth MOS tube and the seventh MOS tube are grounded.
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| CN108400784B (en) * | 2017-02-06 | 2022-02-25 | 晶豪科技股份有限公司 | Level shift circuit and integrated circuit |
| CN109039327A (en) * | 2018-10-18 | 2018-12-18 | 上海艾为电子技术股份有限公司 | A kind of level shifting circuit |
| CN110324027B (en) * | 2019-06-27 | 2020-09-29 | 复旦大学 | Comparator with level shift function |
| CN111697962B (en) * | 2020-06-08 | 2023-08-04 | 中国工程物理研究院电子工程研究所 | Analog sampling circuit of ultra-wideband signal and control method thereof |
| CN113595546B (en) * | 2021-07-01 | 2022-05-17 | 深圳市汇芯通信技术有限公司 | Broadband high-speed level switching circuit and high-speed clock chip |
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