CN106230432A - A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth - Google Patents
A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth Download PDFInfo
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- CN106230432A CN106230432A CN201610767815.1A CN201610767815A CN106230432A CN 106230432 A CN106230432 A CN 106230432A CN 201610767815 A CN201610767815 A CN 201610767815A CN 106230432 A CN106230432 A CN 106230432A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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Abstract
The invention discloses a kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first resistance, the second resistance, the 3rd resistance, the 4th resistance and bias current.The method have the benefit that this circuit has certain current driving ability, it can realize high speed signal level and be converted to higher/relatively low common mode electrical level circuit from relatively low/higher common mode voltage level, high speed signal can be transmitted directly to transmitting terminal, one effective DC common mode is provided, and the high speed signal of ultra wide bandwidth can be provided on the premise of low-power consumption, described low-power consumption is only about 600uA, and described ultra wide bandwidth is up to 50GHZ even 100GHZ.
Description
Technical field
The present invention relates to technical field of integrated circuits, be specifically related to a kind of high speed signal electricity with low-power consumption ultra wide bandwidth
Flat change-over circuit.
Background technology
High speed signal level translator is that from certain common-mode voltage, high speed signal is converted to another one common-mode voltage, with
Meet the common-mode voltage demand of signal receiving end, particularly in high speed signal interface, when the high-speed-differential letter that transmitting terminal sends
When number common mode electrical level is beyond the common-mode voltage input range of receiving terminal, it is necessary to high speed signal level switching circuit is sent to
Signal common mode electrical level be changed into the common mode electrical level scope of receiving terminal.
In existing high speed signal level switching circuit, modal it is passive RC high pass filter, as it is shown in figure 1,
It can effectively transmit high-speed-differential input signal to outfan, and to make the common mode electrical level of outfan be any one VREF
Value, will not be disturbed by the common mode electrical level of input.But, the electricity in frequency receives figure of the low frequency signal once inputted
The size of resistance R and electric capacity C value limits, and the bandwidth of input signal is much smaller than RC by frequency, then input signal can be by this high pass
Wave filter filters, and output voltage only maintains in VREF value, so this circuit is only capable of its high frequency high by frequency of transfer ratio
Signal, and low frequency signal can not be transmitted, and maximum restriction of this circuit is that outfan does not has any driving force, if load
Need certain electric current, then this circuit output common mode voltage will be largely influenced.
In addition, in existing high speed signal level switching circuit, the most frequently used active level shifting circuit such as Fig. 2 and
Shown in Fig. 3, its output bandwidth is all affected by its output impedance and load capacitance, will improve the bandwidth of this circuit, it is necessary to reduce
Resistance value in Fig. 2, thus increase power consumption, for circuit in Fig. 3, need to increase current source current, reduce leading of current source
Energising resistance increases bandwidth, and the cost paid is all to sacrifice power consumption, and under upper GHZ band requirement, this circuit needs several millis
Pacify even tens milliamperes electric currents.
Name Resolution:
NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal-oxide semiconductor (MOS))；
PMOS (positive channel Metal Oxide Semiconductor, P-type mos,
Refer to n-type substrate, p-channel, by the metal-oxide-semiconductor of the flowing transport electric current in hole
DIODE: diode；
BJT (Bipolar Junction Transistor BJT, bipolar junction transistor)；
NPN:N type bipolar transistor；
PNP:P type bipolar transistor.
Summary of the invention
It is an object of the invention to overcome the shortcoming of prior art, propose a kind of high speed letter with low-power consumption ultra wide bandwidth
Number level shifting circuit, it can realize high speed signal level and be converted to one from relatively low/higher common mode voltage level
Higher/relatively low common mode electrical level circuit, and this circuit has certain current driving ability.
The present invention is achieved through the following technical solutions: a kind of high speed signal level conversion electricity with low-power consumption ultra wide bandwidth
Road, it is characterised in that include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th MOS
Pipe, the 7th metal-oxide-semiconductor, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first resistance, the second resistance,
3rd resistance, the 4th resistance and bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the 5th metal-oxide-semiconductor by the first resistance
Drain electrode, the grid of described first metal-oxide-semiconductor is accessed the drain electrode of the 5th metal-oxide-semiconductor by the first electric capacity respectively and is connect by the 4th electric capacity
Enter the grid of the 6th metal-oxide-semiconductor；In like manner, the second metal-oxide-semiconductor grounded drain, the source electrode of the second metal-oxide-semiconductor is by the second resistance and the second electricity
Holding the drain electrode accessing the 6th metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor accesses the grid of the 5th metal-oxide-semiconductor by the 3rd electric capacity；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor respectively by the 4th resistance and the 3rd resistance, and the 3rd
It is bias voltage that resistance and the 4th resistance share end VBIAS1, and the 7th metal-oxide-semiconductor is electric current telescope, by the third and fourth metal-oxide-semiconductor
Providing current to the 5th and the 6th metal-oxide-semiconductor respectively, the grid of the 7th metal-oxide-semiconductor is connected with drain electrode, the source electrode of the 5th and the 6th metal-oxide-semiconductor
Connected together by the 4th electric capacity；The drain electrode of described 7th metal-oxide-semiconductor is by bias current ground connection；
Described 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are for KICKER circuit bias, with the second resistance, the 3rd resistance, the second electricity
Hold, the 3rd electric capacity and the 4th electric capacity form KICKER core circuit, described first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance and the
Two resistance form level shifting circuits, and described second electric capacity and the first electric capacity form feed-forward capacitance circuit, described 3rd electric capacity with
4th resistance, forms a high pass between the 3rd resistance and the 4th electric capacity and the grid of the 5th metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor
Circuit.
Preferably, the drain electrode of described 7th metal-oxide-semiconductor by bias current ground connection, the grid of described 7th metal-oxide-semiconductor, the 3rd
It is sequentially connected between grid and the grid of the 4th metal-oxide-semiconductor of metal-oxide-semiconductor, the source electrode of described 7th metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor
And the 4th metal-oxide-semiconductor source electrode between be sequentially connected and access power supply, the drain electrode of described 3rd metal-oxide-semiconductor accesses also by the 4th electric capacity
The drain electrode of the 4th metal-oxide-semiconductor.
Preferably, described first resistance and the second resistance can be replaced into NMOS, PMOS, DIODE, PNP or NPN to reach simultaneously
Purpose to level conversion.
Preferably, described second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor can be replaced into 2 cascades simultaneously or PNP is formed
Current mirror, and for input to pipe, the first metal-oxide-semiconductor and the second metal-oxide-semiconductor can change PNP pipe into improve its craft precision.
Preferably, specifically including the first audion and the second audion after replacement, the emitter stage of described first audion leads to
Crossing the 4th resistance and access the drain electrode of the 5th metal-oxide-semiconductor, the base stage of described first audion is respectively connected to one end and the of the second electric capacity
One end of five electric capacity, the grounded collector of described first audion.
Preferably, the emitter stage of described second audion by first resistance access the 6th metal-oxide-semiconductor drain electrode, described second
The grounded collector of audion, the base stage of described second audion respectively by the 3rd electric capacity access the 5th metal-oxide-semiconductor grid and
The drain electrode of the 6th metal-oxide-semiconductor is accessed by the first electric capacity.
Present invention also offers another technical scheme, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th MOS
Pipe, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the first resistance, the second resistance and bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the 5th metal-oxide-semiconductor by the first resistance
Drain electrode；In like manner, the second metal-oxide-semiconductor grounded drain, the source electrode of the second metal-oxide-semiconductor accesses the drain electrode of the 6th metal-oxide-semiconductor by the second resistance；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor and shares end
VBIAS1 is bias voltage, and the 7th metal-oxide-semiconductor is electric current telescope, provides current to the 5th He respectively by the third and fourth metal-oxide-semiconductor
6th metal-oxide-semiconductor, the grid of the 7th metal-oxide-semiconductor accesses the grid of the third and fourth metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor drain electrode and the 5th metal-oxide-semiconductor
Source electrode is connected, and the 4th metal-oxide-semiconductor drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor, and the drain electrode of described 7th metal-oxide-semiconductor is connect by bias current
Ground.
Present invention also offers another technical scheme, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th MOS
Pipe, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the first electric capacity, the second electric capacity, the first resistance, the second resistance and biased electrical
Stream；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the 5th metal-oxide-semiconductor by the first resistance
Drain electrode, the grid of described first metal-oxide-semiconductor accesses input differential signal anode；In like manner, the second metal-oxide-semiconductor grounded drain, the 2nd MOS
The drain electrode by the second resistance the 6th metal-oxide-semiconductor of the source electrode of pipe, the grid of the second metal-oxide-semiconductor accesses input differential signal negative terminal, described
The two ends of the first electric capacity are respectively connected to grid and the drain electrode of the 5th metal-oxide-semiconductor of the first metal-oxide-semiconductor, and the two ends of described second electric capacity are respectively
Access grid and the drain electrode of the 6th metal-oxide-semiconductor of the second metal-oxide-semiconductor；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor
Extremely sharing end VBIAS1 is bias voltage, and the 7th metal-oxide-semiconductor is electric current telescope, provides electric current respectively by the third and fourth metal-oxide-semiconductor
To the 5th and the 6th metal-oxide-semiconductor, the grid of the 7th metal-oxide-semiconductor accesses the grid of the third and fourth metal-oxide-semiconductor, and the 3rd metal-oxide-semiconductor drain electrode is with the
The source electrode of five metal-oxide-semiconductors is connected, and the 4th metal-oxide-semiconductor drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor, and the drain electrode of described 7th metal-oxide-semiconductor is passed through
Bias current ground connection.
Present invention also offers another technical scheme, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th MOS
Pipe, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first resistance, the second electricity
Resistance, the 3rd resistance, the 4th resistance and bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the 5th metal-oxide-semiconductor by the first resistance
Drain electrode, the grid of described first metal-oxide-semiconductor by the 4th electric capacity access the 6th metal-oxide-semiconductor grid；In like manner, the second metal-oxide-semiconductor drain electrode
Ground connection, the source electrode of the second metal-oxide-semiconductor accesses the drain electrode of the 6th metal-oxide-semiconductor by the second resistance, and the grid of the second metal-oxide-semiconductor is by the 3rd electricity
Hold the grid accessing the 5th metal-oxide-semiconductor；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor respectively by the 4th resistance and the 3rd resistance, and the 3rd
It is bias voltage that resistance and the 4th resistance share end VBIAS1, and the 7th metal-oxide-semiconductor is electric current telescope, by the third and fourth metal-oxide-semiconductor
Providing current to the 5th and the 6th metal-oxide-semiconductor respectively, the grid of the 7th metal-oxide-semiconductor accesses the grid of the third and fourth metal-oxide-semiconductor, the 5th He
The source electrode of the 6th metal-oxide-semiconductor is connected by the 5th electric capacity；3rd metal-oxide-semiconductor drain electrode is connected with the 5th metal-oxide-semiconductor source electrode, the 4th metal-oxide-semiconductor leakage
Pole is connected with the 6th metal-oxide-semiconductor source electrode, and the grid of described 7th metal-oxide-semiconductor is connected with drain electrode, and the drain electrode of the 7th metal-oxide-semiconductor is by biasing
Current earthing.
Present invention also offers another technical scheme, including the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th MOS
Pipe, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first resistance, the second electricity
Resistance, the 3rd resistance, the 4th resistance and bias current；
The drain electrode of described first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor are all connected with supply voltage, the grid of described first metal-oxide-semiconductor
The drain electrode of the 5th metal-oxide-semiconductor is accessed by the first electric capacity in pole, and the source electrode of described first metal-oxide-semiconductor accesses the 5th MOS by the first resistance
The drain electrode of pipe, the grid of described first metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the grid of described second metal-oxide-semiconductor by the 4th electric capacity
Pole is accessed the drain electrode of the 6th metal-oxide-semiconductor by the second electric capacity respectively and is accessed the grid of the 5th metal-oxide-semiconductor by the 3rd electric capacity；
The source electrode of described second metal-oxide-semiconductor accesses the drain electrode of the 6th metal-oxide-semiconductor, the grid of described 5th metal-oxide-semiconductor by the second resistance
Pole is accessed the grid of the 6th metal-oxide-semiconductor, described 3rd resistance and the 4th resistance by the 4th resistance and the 3rd resistance and is shared end
VBIAS1 is bias voltage, and the source electrode of described 5th metal-oxide-semiconductor accesses the drain electrode of the 3rd metal-oxide-semiconductor, and the source electrode of described 6th metal-oxide-semiconductor connects
Enter the drain electrode of the 4th metal-oxide-semiconductor, connected by the 4th electric capacity between source electrode and the source electrode of the 6th metal-oxide-semiconductor of described 5th metal-oxide-semiconductor；
The grid of described 7th metal-oxide-semiconductor is respectively connected to the 3rd metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, described 7th metal-oxide-semiconductor
Drain electrode is connected with the grid of the 7th metal-oxide-semiconductor, and accesses power supply, the source electrode of described 3rd metal-oxide-semiconductor, the 4th MOS by bias current
The source electrode of pipe and the source grounding of the 7th metal-oxide-semiconductor.
Compared with prior art, there is advantages that a kind of band feed-forward capacitance and positive incentive circuit
High speed signal level translator, and this circuit has certain current driving ability, and it can realize high speed signal level from one
Individual relatively low/higher common mode voltage level is converted to higher/relatively low common mode electrical level circuit, it make use of electric capacity at height
Low impedance characteristic under Pin, can be transmitted directly to transmitting terminal by high speed signal, it is provided that an effective DC common mode, and
And the high speed signal of ultra wide bandwidth can be provided on the premise of low-power consumption, described low-power consumption is only about 600uA, described ultra broadband
Wide up to 50GHZ even 100GHZ.It addition, this circuit provides current driving ability, can effectively drive a current loading,
Particularly during the BJT input in driving BCD technique, need the situation of certain base current.
Accompanying drawing explanation
Fig. 1 is difference RC high pass filter；
Fig. 2 is active signal level shifting circuit (resistance is load)；
Fig. 3 is active signal level shifting circuit (electric current is load)；
Fig. 4 is the integrated circuit structure chart of embodiment 1；
Fig. 5 is the integrated circuit structure chart of embodiment 2；
Fig. 6 is the integrated circuit structure chart of embodiment 3；
Fig. 7 is the common active level shifting circuit of embodiment 4 (CMOS source follower)；
Fig. 8 is the ac gain curve chart of common level shifting circuit；
Fig. 9 is the level shifting circuit of embodiment 5 band feed-forward capacitance；
Figure 10 is the level shifting circuit output AC gain curve figure of band feed-forward capacitance；
Figure 11 is the level shifting circuit of embodiment 6 band feedforward excitation (KICKER)；
Figure 12 is the gain curve figure of band feedforward excitation (KICKER) level shifting circuit；
Figure 13 is integrated circuit gain curve figure；
Figure 14 is that embodiment 7 high level is converted to low-level circuit.
Detailed description of the invention
Below in conjunction with accompanying drawing, present invention is described further.
It show the integrated circuit structure chart of the present invention in conjunction with Fig. 4 to Figure 14, is exemplified below:
Embodiment one:
Such as Fig. 4, circuit forms: bias current I0；PMOS the second metal-oxide-semiconductor P2, the 3rd metal-oxide-semiconductor P3, the 4th metal-oxide-semiconductor P4 group
The current mirror become, provides bias current to circuit, and the size of current that the 3rd metal-oxide-semiconductor P3 and the 4th metal-oxide-semiconductor P4 flows through is with output VOP
Increase with VON current loading and increase；P5 and P6PMOS pipe is for KICKER circuit bias, with resistance R2/R3, electric capacity C2/
C3, and electric capacity C4 is collectively forming KICKER core circuit, this circuit needs a DC offset voltage VBIAS1 to ensure electricity
Road PMOS P5 and P6 DC operation state when is operated in saturation region；PMOS P1 and P2 are used for forming common source and follow
Device forms a level shifting circuit together with resistance R1/R2, and the common mode electrical level of input signal is brought up to VCMIN+VGS+
IR exports, and wherein I is the electric current flowing through resistance, and VGS is the gate source voltage of PMOS P1 and P2, and VCMIN is common mode input
Its value is (VIP+VIN)/2；First electric capacity C1 and the second electric capacity C2 forms feed-forward capacitance circuit.
Specifically include the first metal-oxide-semiconductor P1, the second metal-oxide-semiconductor P2, the 3rd metal-oxide-semiconductor P3, the 4th metal-oxide-semiconductor P4, the 5th metal-oxide-semiconductor P5,
6th metal-oxide-semiconductor P6, the 7th metal-oxide-semiconductor P7, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity
C5, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4 and bias current IO；Described first metal-oxide-semiconductor P1's
Grounded drain, the source electrode of described first metal-oxide-semiconductor P1 accesses the drain electrode of the 5th metal-oxide-semiconductor P5, a described MOS by the first resistance R1
The grid of pipe P1 accesses the drain electrode of the 5th metal-oxide-semiconductor P5 by the first electric capacity C1 respectively and accesses the 6th MOS by the 4th electric capacity C4
The grid of pipe P6；In like manner, the second metal-oxide-semiconductor P2 grounded drain, the source class of the second metal-oxide-semiconductor P2 passes through the second resistance R2 and the second electric capacity
C2 accesses the drain electrode of the 6th metal-oxide-semiconductor P6, and the grid of the second metal-oxide-semiconductor P2 accesses the grid of the 5th metal-oxide-semiconductor P5 by the 3rd electric capacity C3.
The grid of described 5th metal-oxide-semiconductor P5 accesses the 6th metal-oxide-semiconductor P6's by the 4th resistance R4 and the 3rd resistance R3 respectively
Grid, it is bias voltage that the 3rd resistance R3 and the 4th resistance R4 shares end VBIAS1, and the 7th metal-oxide-semiconductor P7 is electric current telescope, passes through
Third and fourth metal-oxide-semiconductor provides current to the 5th and the 6th metal-oxide-semiconductor respectively, and the drain electrode of the third and fourth metal-oxide-semiconductor is respectively connected to
The source electrode of the five and the 6th metal-oxide-semiconductor, the 5th is connected together by the 4th electric capacity C4 with the source electrode of the 6th metal-oxide-semiconductor；Described 7th MOS
The drain electrode of pipe P7 is by bias current ground connection；
Described 5th metal-oxide-semiconductor P5 and the 6th metal-oxide-semiconductor P6 is used for KICKER circuit bias, with the second resistance R2, the 3rd resistance
R3, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 form KICKER core circuit, described first metal-oxide-semiconductor P1, second
Metal-oxide-semiconductor P2, the first resistance R1 and the second resistance R2 form level shifting circuit, described second electric capacity C2 and the first electric capacity C1 and are formed
Feed-forward capacitance circuit, described 3rd electric capacity C3 and the 4th resistance R4, the 3rd resistance R3's and the 4th electric capacity C4 and the 5th metal-oxide-semiconductor P5
A high pass circuit is formed between the grid of grid and the 6th metal-oxide-semiconductor.
Further, the drain electrode of described 7th metal-oxide-semiconductor P7 is by bias current IO ground connection, the grid of described 7th metal-oxide-semiconductor P7
Pole, it is sequentially connected between the grid of the 3rd metal-oxide-semiconductor P3 and the grid of the 4th metal-oxide-semiconductor P4, the source electrode of described 7th metal-oxide-semiconductor P7,
Being sequentially connected between source electrode and the source electrode of the 4th metal-oxide-semiconductor P4 of three metal-oxide-semiconductor P3, the drain electrode of described 3rd metal-oxide-semiconductor P3 is also by
Four electric capacity C4 access the drain electrode of the 4th metal-oxide-semiconductor P4.
Embodiment two:
The first resistance R1 and the second resistance R2 in Fig. 4 circuit can be replaced into NMOS, PMOS, DIODE, PNP or NPN simultaneously
To reach the purpose of level conversion, shown in the instruction of below figure 5 arrow.
Embodiment three:
Current mirror the 3rd metal-oxide-semiconductor P3, the 4th metal-oxide-semiconductor P4 and the 5th metal-oxide-semiconductor P5, can be in the case of power ratio is higher simultaneously
It is replaced into 2 cascades or PNP forms current mirror, and for input to pipe, the first metal-oxide-semiconductor P1 and the second metal-oxide-semiconductor P2 can change into
PNP pipe is to improve its craft precision, as shown in Figure 6.And if it is desired to obtain higher output level, its resistance, MOS can be selected
Pipe or DIODE or BJT pipe carry out various combination and export in cascaded fashion.
Embodiment four:
First, discounting for by electric capacity the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4 and
Five electric capacity C5, and the second resistance R2 and the 3rd resistance R3, this circuit result is as shown in Figure 7.This circuit is a common level
Change-over circuit, i.e. CMOS source follower, its circuit is low-frequency channel structure, and it is input to output bandwidth and is illustrated in fig. 8 shown below.This electricity
Road design wastage in bulk or weight electric current be 600uA, Fig. 8 it can be seen that its characteristic is a low-pass characteristic ,-3dB Frequency point is about at 1Ghz
Near.It can not transmit the 5G even signal of more than 10G.
Embodiment five:
Secondly, if feedforward the first electric capacity C1 added on circuit in figure 4 above and the second electric capacity C2, its structure such as Fig. 9 institute
Show.Its corresponding ac gain curve chart is as shown in Figure 10.It can be seen that this circuit achieves ultra wide bandwidth substantially in Figure 10
The ac gain of gain, but, at Mid Frequency, due in the gain of the common level shifting circuit path in Figure 10 and Fig. 9
The gain of the first electric capacity C1 and the second electric capacity C2 path of feedovering defines 2 paths, causes Mid Frequency gain and is formed wavy,
Its peak value and trough difference have a 83mdB, and this circuit causes gain at 100Ghz apparently higher than gain at low frequency.
Embodiment six:
If this circuit only retains electric capacity the second electric capacity C2, the 3rd electric capacity C3, the of feedforward excitation (KICKER) part
Four electric capacity C4, and the second resistance R2 and the 3rd resistance R3, its circuit is as shown in figure 11；For the second electric capacity C2 and the 3rd electric capacity
C3, and the second resistance R2 and the 3rd resistance R3, its 3rd resistance R3 and the second electric capacity C2, the second resistance R2 and the 3rd electric capacity C3
For signal to the 5th metal-oxide-semiconductor P5 and the gate vias of the 6th metal-oxide-semiconductor P6, which form a high pass characteristic.Its role is to,
When signal inputs from input, it is assumed that now be turn over from 01 a differential signal, then, VIP rising edge arrive time,
VIN now trailing edge arrives, and now the grid voltage of the 5th metal-oxide-semiconductor P5 is affected by the AC electric current of the second electric capacity C2, has a wink
The process that state is drop-down, and the grid voltage of the 6th metal-oxide-semiconductor P6 is affected by the 3rd electric capacity C3, has the process that a transient state rises,
5th metal-oxide-semiconductor P5 is due to the reduction of grid voltage, thus the transient state causing the gate source voltage of the 5th metal-oxide-semiconductor P5 increases, due to
The existence of the 4th electric capacity C4, forms the current path of a low impedance at high frequency so that flows through the 5th metal-oxide-semiconductor P5 transient current and increases
Greatly, and the transient current flowing through the 6th metal-oxide-semiconductor P6 reduces, thus adds the high-frequency gain of now circuit.
This circuit is carried out ac gain analysis, it can be seen that its gain curve is as shown in figure 12；Can from Figure 12
Going out, Figure 11 circuit significantly improves the bandwidth of the circuit in Fig. 4.Simultaneously as fast path (KICKER) and slow path (common source
Follower) existence, introduce zero point in circuit, cause the part that ratio of gains DC current gain is big, adjust KICKER part
The scale parameter of circuit, can effectively regulate the zero pole point position of gain, to compensate the wave gain section in Figure 10, reduces it
The change of wave gain section.Figure 13 is the gain curve figure of integrated circuit.
Figure 13 can be seen that, although gain also has wave-like, but its peakedness ratio DC current gain only increases
10mdB, and trough is than DC current gain, merely reduces-4.3mdB, the change of whole gain only 14.3mdB, only can introduce defeated
Enter 0.165% change of signal, reach the most complete negligible change.And from direct current to 100G
In the range of, whole gain all tends to be steady.And whole circuit consumption current only 600uA.
Embodiment seven:
This circuit is the process that a low common-mode voltage converts toward high common-mode voltage, it is also possible to formed past from high common-mode voltage
The process of low common-mode voltage conversion.As shown in figure 14.Its principle is as Fig. 4.Its device can also be with Fig. 4 side of replacement accordingly
Case is replaced.
The foregoing is only the preferred embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization
Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or it is relevant to be directly or indirectly used in other
Technical field, be the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. a high speed signal level switching circuit with low-power consumption ultra wide bandwidth, it is characterised in that include the first metal-oxide-semiconductor,
Second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the first electric capacity, the second electricity
Appearance, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first resistance, the second resistance, the 3rd resistance, the 4th resistance and bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the leakage of the 5th metal-oxide-semiconductor by the first resistance
Pole, the grid of described first metal-oxide-semiconductor accesses the drain electrode of the 5th metal-oxide-semiconductor by the first electric capacity respectively and accesses the by the 4th electric capacity
The grid of six metal-oxide-semiconductors；In like manner, the second metal-oxide-semiconductor grounded drain, the source electrode of the second metal-oxide-semiconductor is connect by the second resistance and the second electric capacity
Entering the drain electrode of the 6th metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor accesses the grid of the 5th metal-oxide-semiconductor by the 3rd electric capacity；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the 3rd resistance respectively by the 4th resistance and the 3rd resistance
Sharing end VBIAS1 with the 4th resistance is bias voltage, and the 7th metal-oxide-semiconductor is electric current telescope, by the third and fourth metal-oxide-semiconductor respectively
Providing current to the 5th and the 6th metal-oxide-semiconductor, the grid of the 7th metal-oxide-semiconductor is connected with drain electrode, and the source electrode of the 5th and the 6th metal-oxide-semiconductor passes through
4th electric capacity connects together；The drain electrode of described 7th metal-oxide-semiconductor is by bias current ground connection；
Described 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor for KICKER circuit bias, with the second resistance, the 3rd resistance, the second electric capacity,
3rd electric capacity and the 4th electric capacity form KICKER core circuit, described first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance and the second electricity
Resistance forms level shifting circuit, described second electric capacity and the first electric capacity and forms feed-forward capacitance circuit, described 3rd electric capacity and the 4th
Resistance, forms a high energising between the 3rd resistance and the 4th electric capacity and the grid of the 5th metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor
Road.
A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth the most according to claim 1, its feature
It is: the drain electrode of described 7th metal-oxide-semiconductor is by bias current ground connection, the grid of described 7th metal-oxide-semiconductor, the grid of the 3rd metal-oxide-semiconductor
And the 4th metal-oxide-semiconductor grid between be sequentially connected, source electrode, the source electrode of the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor of described 7th metal-oxide-semiconductor
Source electrode between be sequentially connected and access power supply, the drain electrode of described 3rd metal-oxide-semiconductor accesses the 4th metal-oxide-semiconductor also by the 4th electric capacity
Drain electrode.
A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth the most according to claim 1 and 2, it is special
Levying and be, described first resistance and the second resistance can be replaced into NMOS, PMOS, DIODE, PNP or NPN simultaneously turn to reach level
The purpose changed.
A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth the most according to claim 1 and 2, it is special
Levy and be, described second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor can be replaced into 2 cascades simultaneously or PNP forms current mirror,
And for input to pipe, the first metal-oxide-semiconductor and the second metal-oxide-semiconductor can change PNP pipe into improve its craft precision.
A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth the most according to claim 4, its feature
Being, specifically include the first audion and the second audion after replacement, the emitter stage of described first audion passes through the 4th resistance
Accessing the drain electrode of the 5th metal-oxide-semiconductor, the base stage of described first audion is respectively connected to one end and the one of the 5th electric capacity of the second electric capacity
End, the grounded collector of described first audion.
A kind of high speed signal level switching circuit with low-power consumption ultra wide bandwidth the most according to claim 5, its feature
Being, the emitter stage of described second audion accesses the drain electrode of the 6th metal-oxide-semiconductor, the collection of described second audion by the first resistance
Electrode ground connection, the base stage of described second audion accesses the grid of the 5th metal-oxide-semiconductor and by the first electricity by the 3rd electric capacity respectively
Hold the drain electrode accessing the 6th metal-oxide-semiconductor.
7. a high speed signal level switching circuit with low-power consumption ultra wide bandwidth, it is characterised in that include the first metal-oxide-semiconductor,
Second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the first resistance, the second resistance
And bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the leakage of the 5th metal-oxide-semiconductor by the first resistance
Pole；In like manner, the second metal-oxide-semiconductor grounded drain, the source electrode of the second metal-oxide-semiconductor accesses the drain electrode of the 6th metal-oxide-semiconductor by the second resistance；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor altogether
Being bias voltage with end VBIAS1, the 7th metal-oxide-semiconductor is electric current telescope, provides current to the respectively by the third and fourth metal-oxide-semiconductor
Five and the 6th metal-oxide-semiconductor, the grid of the 7th metal-oxide-semiconductor accesses the grid of the third and fourth metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor drain electrode and the 5th MOS
The source electrode of pipe is connected, and the 4th metal-oxide-semiconductor drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor, and biased electrical is passed through in the drain electrode of described 7th metal-oxide-semiconductor
Stream ground connection.
8. a high speed signal level switching circuit with low-power consumption ultra wide bandwidth, it is characterised in that include the first metal-oxide-semiconductor,
Second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the first electric capacity, the second electricity
Appearance, the first resistance, the second resistance and bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the leakage of the 5th metal-oxide-semiconductor by the first resistance
Pole, the grid access differential signal anode of described first metal-oxide-semiconductor；In like manner, the second metal-oxide-semiconductor grounded drain, the source electrode of the second metal-oxide-semiconductor
By the drain electrode of the second resistance the 6th metal-oxide-semiconductor, the grid access differential signal negative terminal of the second metal-oxide-semiconductor, the two of described first electric capacity
End is respectively connected to grid and the drain electrode of the 5th metal-oxide-semiconductor of the first metal-oxide-semiconductor, and the two ends of described second electric capacity are respectively connected to the 2nd MOS
The grid of pipe and the drain electrode of the 6th metal-oxide-semiconductor；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the grid of the 6th metal-oxide-semiconductor altogether
Being bias voltage with end VBIAS1, the 7th metal-oxide-semiconductor is electric current telescope, provides current to the respectively by the third and fourth metal-oxide-semiconductor
Five and the 6th metal-oxide-semiconductor, the grid of the 7th metal-oxide-semiconductor accesses the grid of the third and fourth metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor drain electrode and the 5th MOS
The source electrode of pipe is connected, and the 4th metal-oxide-semiconductor drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor, and biased electrical is passed through in the drain electrode of described 7th metal-oxide-semiconductor
Stream ground connection.
9. a high speed signal level switching circuit with low-power consumption ultra wide bandwidth, it is characterised in that include the first metal-oxide-semiconductor,
Second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 3rd electric capacity, the 4th electricity
Appearance, the 5th electric capacity, the first resistance, the second resistance, the 3rd resistance, the 4th resistance and bias current；
The grounded drain of described first metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the leakage of the 5th metal-oxide-semiconductor by the first resistance
Pole, the grid of described first metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor by the 4th electric capacity；In like manner, the second metal-oxide-semiconductor grounded drain,
The source electrode of the second metal-oxide-semiconductor accesses the drain electrode of the 6th metal-oxide-semiconductor by the second resistance, and the grid of the second metal-oxide-semiconductor is connect by the 3rd electric capacity
Enter the grid of the 5th metal-oxide-semiconductor；
The grid of described 5th metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor, the 3rd resistance respectively by the 4th resistance and the 3rd resistance
Sharing end VBIAS1 with the 4th resistance is bias voltage, and the 7th metal-oxide-semiconductor is electric current telescope, by the third and fourth metal-oxide-semiconductor respectively
Providing current to the 5th and the 6th metal-oxide-semiconductor, the grid of the 7th metal-oxide-semiconductor accesses the grid of the third and fourth metal-oxide-semiconductor, the 5th and the 6th
The source electrode of metal-oxide-semiconductor is connected by the 5th electric capacity；3rd metal-oxide-semiconductor drain electrode be connected with the 5th metal-oxide-semiconductor source electrode, the 4th metal-oxide-semiconductor drain electrode and
6th metal-oxide-semiconductor source electrode is connected, and the grid of described 7th metal-oxide-semiconductor is connected with drain electrode, and bias current is passed through in the drain electrode of the 7th metal-oxide-semiconductor
Ground connection.
10. a high speed signal level switching circuit with low-power consumption ultra wide bandwidth, it is characterised in that include the first metal-oxide-semiconductor,
Second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 3rd electric capacity, the 4th electricity
Appearance, the 5th electric capacity, the first resistance, the second resistance, the 3rd resistance, the 4th resistance and bias current；
The drain electrode of described first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor are all connected with supply voltage, and the grid of described first metal-oxide-semiconductor leads to
Crossing the first electric capacity and access the drain electrode of the 5th metal-oxide-semiconductor, the source electrode of described first metal-oxide-semiconductor accesses the 5th metal-oxide-semiconductor by the first resistance
Drain electrode, the grid of described first metal-oxide-semiconductor accesses the grid of the 6th metal-oxide-semiconductor by the 4th electric capacity, and the grid of described second metal-oxide-semiconductor divides
Tong Guo not access the drain electrode of the 6th metal-oxide-semiconductor and accessed the grid of the 5th metal-oxide-semiconductor by the 3rd electric capacity by the second electric capacity；
The source electrode of described second metal-oxide-semiconductor accesses the drain electrode of the 6th metal-oxide-semiconductor by the second resistance, and the grid of described 5th metal-oxide-semiconductor leads to
Crossing the 4th resistance and the grid of the 3rd resistance access the 6th metal-oxide-semiconductor, described 3rd resistance and the 4th resistance share end VBIAS1 and are
Bias voltage, the source electrode of described 5th metal-oxide-semiconductor accesses the drain electrode of the 3rd metal-oxide-semiconductor, and the source electrode of described 6th metal-oxide-semiconductor accesses the 4th
The drain electrode of metal-oxide-semiconductor, is connected by the 4th electric capacity between source electrode and the source electrode of the 6th metal-oxide-semiconductor of described 5th metal-oxide-semiconductor；Described 7th
The grid of metal-oxide-semiconductor is respectively connected to the 3rd metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, the drain electrode of described 7th metal-oxide-semiconductor and the 7th metal-oxide-semiconductor
Grid be connected, and by bias current access power supply, the source electrode of described 3rd metal-oxide-semiconductor, the source electrode and the 7th of the 4th metal-oxide-semiconductor
The source grounding of metal-oxide-semiconductor.
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