CN103888093B - Common-mode level reset circuit for differential signals - Google Patents
Common-mode level reset circuit for differential signals Download PDFInfo
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- CN103888093B CN103888093B CN201410153587.XA CN201410153587A CN103888093B CN 103888093 B CN103888093 B CN 103888093B CN 201410153587 A CN201410153587 A CN 201410153587A CN 103888093 B CN103888093 B CN 103888093B
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Abstract
The invention discloses a common-mode level reset circuit for differential signals. The common-mode level reset circuit comprises a source follow circuit, a voltage-current conversion circuit, a current output circuit and a common-mode reset circuit, wherein the source follow circuit, the voltage-current conversion circuit, the current output circuit and the common-mode reset circuit are sequentially connected. The common-mode level reset circuit can achieve level resetting of output common-mode points, meet the requirement of the next stage input common-mode points, and maintain high differential linearity. The source follow device circuit of a PMOS tube enables the VTH of the input common-mode points to be increased, and the input common-mode points are connected with an NMOS of a following form to form the voltage-current conversion circuit, the input voltage linearity is converted into the current signals, the current signals are transmitted to the current output circuit through image currents, the common-mode level of the current output circuit is reset through the common-mode reset circuit, and finally the common-mode level of the output level VOUT and the VREF are identical. The common-mode level reset circuit achieves resetting of the differential signal common-mode level, maintains the differential linearity of the signals to the maximum degree, and is suitable for the differential signals with the medium amplitude.
Description
Technical field
The present invention relates to a kind of common mode electrical level reset circuit of differential signal, particular for modular circuit in integrated circuit it
Between interconnect level conversion.
Background technology
Integrated circuit quickly grows in recent years, and manufacturing process and integrated level are improved rapidly, the species sum of integrated circuit
Amount is more and more, and function is stronger and stronger, and wherein analog circuit species and function are in rising trend all the time.In Analogous Integrated Electronic Circuits
Differential signal is conventional small signal process, transmission mode, using it to becoming second nature, can effectively reduce interference.
In integrated circuit, difference MOS is the mode of common process differential signal to pipe, when being made the difference using NMOS and PMOS
When dividing to pipe, optimal common mode voltage may be different, in addition the different signal processing mode demand such as voltage/current, high resistant/low-resistance
Common-mode voltage also differ, therefore in order to pursue during the factors such as optimal performance, power consumption, area, the difference of disparate modules circuit
The common-mode voltage of sub-signal there may be difference.
In integrated circuits, the common-mode voltage for requiring when common-mode voltage and the next stage input circuit of output module circuit is not
When consistent, ordinary circumstance can not be cascaded directly, otherwise may not normal work, or the problems such as there is abnormal dissipation, therefore
Resets circuit is needed to realize the transfer of common-mode voltage.Common mode carry circuit has many kinds, by diode or is connected as
The MOS device of diode can realize the transfer of level with reference to resistance, but its driving force can not meet subordinate sometimes
Needs, and level shift with VT as base unit, it is impossible to the arbitrary syntype bias voltage of flexible modulation.
Sometimes the requirement shifted to the level of syntype bias voltage is harsher, such as possess certain isolation, input
Resistance is as high as possible（Up to a megohm magnitude）, output possess certain carrying load ability, while distortion can not be occurred, this is just to electricity
The higher requirement that the design of level shifter is proposed, will consider the characteristics such as linear, power consumption, conversion speed.
The content of the invention
It is an object of the invention to overcome the problem above that prior art is present, there is provided a kind of common mode electrical level of differential signal
Reset circuit, realizes the replacement of differential signal common mode electrical level, and the differential linearity of signal is maintained to greatest extent, is particularly suited for width
The common mode electrical level of the medium differential signal of degree resets.
To realize above-mentioned technical purpose, above-mentioned technique effect is reached, the present invention is achieved through the following technical solutions：
A kind of common mode electrical level reset circuit of differential signal, turns including the source follower, voltage-to-current being sequentially connected
Change circuit, current output circuit and common mode reset circuit.
Further, the source follower adopts pmos source series resistor, PMOS grids to be directly connected to input letter
Number, PMOS drain electrode connections ground, source electrode are connected to power supply by resistance.
Further, the current/charge-voltage convertor adopts the source follower of NMOS, nmos source to pass through resistance
Ground connection, the PMOS of drain circuit connection grid leak short circuit are loaded.
Further, the current output circuit is exported using the drain electrode of high resistant, the grid of MOS and coupled similar
MOS constitutes current mirroring circuit.
Further, the common mode reset circuit and output stage constitute the negative-feedback circuit of common mode electrical level, identical with two
Resistance obtain the common mode electrical level of output stage, realize the comparison of common mode electrical level and VREF with PMOS differential pair pipe, adjust electric current logical
The NMOS for crossing grid leak short circuit is supplied to the biasing of output stage NMOS.
Preferably, the common mode reset circuit is also equipped with the biasing circuit of itself, the biased electrical routing resistance and one group
PMOS current mirrors are constituted.
The invention has the beneficial effects as follows:
1st, the present invention can realize that the level of output common mode point resets, and reach the requirement that next stage is input into common-mode point, while
Keep higher differential linearity.Input common-mode point is set to improve VTH by the source follower circuit of PMOS, then by being connected as
The NMOS for following form constitutes current/charge-voltage convertor, is current signal input voltage linear transformation, eventually passes mirror image
Electric current is transferred to current output circuit, and the common mode electrical level of current output circuit is reset by common mode reset circuit, final defeated
The common mode electrical level for going out level VOUT is consistent with VREF.Present invention achieves the replacement of differential signal common mode electrical level, protects to greatest extent
The differential linearity of signal is held, the common mode electrical level for being suitable to the medium differential signal of amplitude resets.
2nd, source follower possesses preferable voltage follow characteristic, and using PMOS source follower part is done, and possesses high
Input resistance, gain is approximately 1, possesses preferably linear, and output source electrode is connected to power supply by resistance, and resistance is provided just
The biasing and constant load of often work.Voltage signal is input into from the grid of PMOS, and homophase, the voltage of constant amplitude are exported from source electrode,
This source follower plays two major functions, and one is buffer action, and two is to improve common mode electrical level VT, it is ensured that subordinate's circuit is normal
Work.
3rd, current/charge-voltage convertor is input into using the NMOS that source electrode is followed, and the source voltage of NMOS follows grid electricity
Pressure, voltage reduces VT, therefore the source voltage of NMOS follows the input voltage vin of circuit completely the same with upper level source, so
The electric current for flowing through source resistance is exactly Vin/R, realizes the Voltage-current conversion of input voltage, and the electric current of linear transformation is entered
It is connected as the PMOS of current mirror input.
4th, output circuit adopts the drain electrode output form of high resistant, the wherein grid of MOS and coupled similar MOS compositions
Current mirroring circuit, the electric current after such superior voltage-electric current conversion is exported by output circuit, due to two concatenation electricity of subordinate
Resistance is loaded, therefore voltage signal is converted to herein.
5th, common mode reset circuit can reset to the common-mode point of output circuit, and its central principle is the negative of common mode electrical level
Feedback circuit, with two identical resistance the common mode electrical level of output stage is obtained, while as the load of output current, it is poor with PMOS
Divide the comparison that common mode electrical level and VREF are realized to pipe, adjust electric current and the inclined of output stage NMOS is supplied to by the NMOS of grid leak short circuit
Put.When output common mode level is higher than VREF, P8 conductings plus heavy current increase, and N5 electric currents are also increased, on output circuit NMOS
Pull-down current is increased, and reduces output common mode level, conversely, increase output common mode level, the common mode electricity of final output level VOUT
It is flat consistent with VREF.Common mode reset circuit is also equipped with the biasing circuit of itself, is made up of resistance and one group of PMOS current mirror.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after.
The specific embodiment of the present invention is shown in detail in by following examples and its accompanying drawing.
Description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this
Bright schematic description and description does not constitute inappropriate limitation of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is the common mode electrical level reset circuit figure of differential signal；
Fig. 2 is source follower；
Fig. 3 is current/charge-voltage convertor；
Fig. 4 is current output circuit；
Fig. 5 is common mode reset circuit.
Specific embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments describing the present invention in detail.
With reference to shown in Fig. 1, the common mode electrical level reset circuit of a kind of differential signal, including the source follower being sequentially connected
1st, current/charge-voltage convertor 2, current output circuit 3 and common mode reset circuit 4.
With reference to shown in Fig. 2, the source follower 1 adopts a pair of PMOSs P1, P2, and P1, P2 grid is directly connected to defeated
Enter signal, drain electrode connection ground, source electrode is connected to power supply by resistance R1, R2 respectively.Source follower 1 must in implementation process
Must possess preferable voltage follow characteristic, therefore source follower part PMOS therein must take enough sizes, its is equivalent
Transconductance value is significantly larger than the inverse of its source load resistance, and the substrate connection source electrode of PMOS, in addition to keeping preferable
Symmetry, wherein the device parameters on positive and negative two branch roads are completely the same.
With reference to shown in Fig. 3, the current/charge-voltage convertor 2 adopts a pair of NMOS tubes N1, N2, N1, N2 source electrode to lead to respectively
Resistance R3, R4 ground connection is crossed, a pair of PMOSs P3, P4 of drain circuit connection grid leak short circuit are loaded.Current/charge-voltage convertor
2 NMOS followed using source electrode are input into, and because technique is limited, during without depth N well nmos devices, can adopt common NMOS devices
Part, now substrate can not connect source electrode, can be grounded.For the purposes of ensureing good voltage follow characteristic, the breadth length ratio of NMOS must
Must be sufficiently large, also much larger than the inverse of its source load resistance, what its drain electrode was even exported is the electricity of voltage conversion to equivalent transconductance value
Stream, connects the PMOS into current mirror input, and the overdrive voltage of PMOS can be adjusted between 0.1-0.2V according to size
Section.
With reference to shown in Fig. 4, the current output circuit 3 adopts the drain electrode output form of high resistant, the grid of NMOS tube N3, N4
Be connected with the grid of NMOS tube N5 in the common mode reset circuit 4, the grid of PMOS P5, P6 respectively with the electric piezo-electric
The grid of P4, P3 in stream change-over circuit 2 is connected, and the electric current after such superior voltage-electric current conversion is exported by output circuit,
Because two series resistors of subordinate are loaded, therefore voltage signal is converted to herein.The ratio of mirror currents can be
1:1, it is also possible to be adjusted as needed.
With reference to shown in Fig. 5, the common mode reset circuit 4 constitutes the negative-feedback circuit of common mode electrical level, common mode weight with output stage
Circuits 4 can reset to the common-mode point of output circuit, and with two identical resistance the common mode electrical level of output stage is obtained, and use
PMOS differential pair pipe P9, P10 realize the comparison of common mode electrical level and VREF, and the resistance of resistance can be with the source of Voltage-current conversion
Pole load resistance is identical, and now integrated circuit gain is 1, can need the appropriate resistance of resistance herein and output electricity according to gain
The ratio of current mirror in road.VREF is provided by subordinate's circuit, can suitably add capacitor filter.Adjust electric current and pass through grid leak short circuit
NMOS be supplied to the biasing of output stage NMOS.
The common mode reset circuit 4 is also equipped with the biasing circuit of itself, and the biased electrical routing resistance and one group of PMOS are electric
Stream microscope group into.To ensure relatively low power consumption, the other resistance of hundred K ohm levels can be taken.The selection of biasing resistor also determines N5 and N4/
The current ratio of the current mirror of N3 compositions, generally, it is ensured that the electric current of N3, N4 and the basic phase of the common mode current of P5, P6
When while in order to realize higher common-mode voltage precision, the size of two PMOS devices of P7, P8 is suitable, can pass through circuit
Emulation is determined.
The present invention can realize that the level of output common mode point resets, and reach the requirement that next stage is input into common-mode point, while protecting
Hold higher differential linearity.Input common-mode point is set to improve VTH by the source follower circuit 1 of PMOS, then by being connected as
The NMOS for following form constitutes current/charge-voltage convertor 2, is current signal input voltage linear transformation, eventually passes mirror
Image current is transferred to current output circuit 3, and the common mode electrical level of current output circuit 3 is reset by common mode reset circuit, most
The common mode electrical level of whole output level VOUT is consistent with VREF.Present invention achieves the replacement of differential signal common mode electrical level, maximum limit
Degree maintains the differential linearity of signal, and the common mode electrical level for being suitable to the medium differential signal of amplitude resets.
The preferred embodiments of the present invention are the foregoing is only, the present invention is not limited to, for the skill of this area
For art personnel, the present invention can have various modifications and variations.It is all within the spirit and principles in the present invention, made any repair
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (4)
1. the common mode electrical level reset circuit of a kind of differential signal, it is characterised in that：Including the source follower being sequentially connected
（1）, current/charge-voltage convertor（2）, current output circuit（3）With common mode reset circuit（4）, the common mode reset circuit（4）
With the negative-feedback circuit that output stage constitutes common mode electrical level, including the 5th resistance of two parallel connections（R5）, the 6th resistance（R6）Obtain
The common mode electrical level of output stage, with the 7th PMOS（P7）With the 8th PMOS（P8）Differential pair tube realizes common mode electrical level and VREF's
Relatively, fiveth NMOS tube of the electric current by grid leak short circuit is adjusted（N5）It is supplied to the biasing of output stage NMOS, the common mode to reset
Circuit（4）The biasing circuit of itself is also equipped with, the biasing circuit includes the 7th PMOS（P7）With the 8th PMOS（P8）'s
Sources connected in parallel is in the 9th PMOS（P9）In drain electrode, the 9th PMOS（P9）With the tenth PMOS（P10）Grid, source electrode are connected,
Tenth PMOS（P10）Drain electrode and its grid short circuit, the tenth PMOS（P10）Drain electrode passes through the 7th resistance（R7）With the 5th NMOS
Pipe（N5）Source electrode be connected.
2. common mode electrical level reset circuit according to claim 1, it is characterised in that：The source follower（1）Using
Pmos source series resistor, PMOS grids are directly connected to input signal, and PMOS drain electrode connections ground, source electrode are connected to electricity by resistance
Source.
3. common mode electrical level reset circuit according to claim 1, it is characterised in that：The current/charge-voltage convertor（2）
Using the source follower of NMOS, nmos source is loaded by the PMOS that resistance eutral grounding, drain circuit connect grid leak short circuit.
4. common mode electrical level reset circuit according to claim 1, it is characterised in that：The current output circuit（3）Using
The drain electrode output of high resistant, including the 5th PMOS（P5）, the 6th PMOS（P6）, the 5th PMOS（P5）, the 6th PMOS
Pipe（P6）Grid and the current/charge-voltage convertor（2）It is connected to form current mirroring circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410153587.XA CN103888093B (en) | 2014-04-17 | 2014-04-17 | Common-mode level reset circuit for differential signals |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153587.XA CN103888093B (en) | 2014-04-17 | 2014-04-17 | Common-mode level reset circuit for differential signals |
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| CN103888093A CN103888093A (en) | 2014-06-25 |
| CN103888093B true CN103888093B (en) | 2017-04-19 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9438188B2 (en) * | 2014-09-15 | 2016-09-06 | Qualcomm Incorporated | Common-gate amplifier for high-speed DC-coupling communications |
| CN106130536B (en) * | 2016-06-20 | 2019-06-14 | 华为技术有限公司 | Level shifting circuit and electronic equipment |
| CN107749709B (en) * | 2017-12-06 | 2023-07-07 | 西安智多晶微电子有限公司 | Charge pump for FPGA chip |
| CN109039327A (en) * | 2018-10-18 | 2018-12-18 | 上海艾为电子技术股份有限公司 | A kind of level shifting circuit |
| CN111061333B (en) * | 2020-03-18 | 2021-02-12 | 南京华瑞微集成电路有限公司 | Reference comparison circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226413A (en) * | 2008-01-22 | 2008-07-23 | 无锡硅动力微电子股份有限公司 | Reference circuit for restraining misadjusted CMOS energy gap |
| CN101951227A (en) * | 2010-09-30 | 2011-01-19 | 上海贝岭股份有限公司 | Amplifier circuit |
| CN102412824A (en) * | 2011-12-02 | 2012-04-11 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN203326961U (en) * | 2012-12-24 | 2013-12-04 | 苏州硅智源微电子有限公司 | Electrical level switching circuit with high gain |
-
2014
- 2014-04-17 CN CN201410153587.XA patent/CN103888093B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226413A (en) * | 2008-01-22 | 2008-07-23 | 无锡硅动力微电子股份有限公司 | Reference circuit for restraining misadjusted CMOS energy gap |
| CN101951227A (en) * | 2010-09-30 | 2011-01-19 | 上海贝岭股份有限公司 | Amplifier circuit |
| CN102412824A (en) * | 2011-12-02 | 2012-04-11 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN203326961U (en) * | 2012-12-24 | 2013-12-04 | 苏州硅智源微电子有限公司 | Electrical level switching circuit with high gain |
Non-Patent Citations (2)
| Title |
|---|
| 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology;J. Francisco Duque-Carrillo，et al.;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20000131;第35卷(第1期);33-44 * |
| 基于共模电平偏移电路新型CMOS低电压满幅度运放设计;林越，等.;《半导体学报》;20020531;第23卷(第5期);529-534 * |
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