CN107749709B - Charge pump for FPGA chip - Google Patents
Charge pump for FPGA chip Download PDFInfo
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- CN107749709B CN107749709B CN201711275968.5A CN201711275968A CN107749709B CN 107749709 B CN107749709 B CN 107749709B CN 201711275968 A CN201711275968 A CN 201711275968A CN 107749709 B CN107749709 B CN 107749709B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a charge pump for an FPGA chip, which comprises a differential input circuit, a common mode negative feedback circuit, a current mismatch correction circuit, an output differential mode zero clearing circuit and a differential output circuit, wherein the differential input circuit is connected with the common mode negative feedback circuit; the differential input circuit is connected with the differential output circuit and is used for generating the final output voltage of the charge pump; the differential output circuit comprises two output ends which are respectively connected with a common mode negative feedback circuit and a current mismatch correction circuit and is used for respectively providing a common mode detection level for the common mode negative feedback circuit and a current mismatch detection level for the current mismatch correction circuit; the common mode negative feedback circuit is connected with the differential input circuit and is used for compensating the common mode detection level to the output end of the differential input circuit; the current mismatch correction circuit is connected with the differential output circuit and is used for correspondingly compensating two differential outputs according to the detected current mismatch detection level of the differential output. The invention improves the linearity of the charge pump.
Description
Technical Field
The invention belongs to the field of clock control, and particularly relates to a charge pump for an FPGA chip.
Background
FPGAs (Field-Programmable Gate Array, field programmable gate arrays) are logic devices made up of a number of logic cells, including gates, look-up tables and flip-flops, which have rich hardware resources, powerful parallel processing capabilities and flexible reconfigurable capabilities, and are becoming increasingly widely used in many fields such as data processing, communications, networking, etc. Inside the FPGA there are typically a plurality of PLLs (Phase Locked Loop, phase locked loops). The PLL is used inside the FPGA to generate a high quality clock. PLL is typically composed of a phase detector, a charge pump, a filter, a voltage controlled oscillator, and a frequency divider. The charge pump is an important component of the PLL in the FPGA.
The charge pump generally has the problems of charge-discharge current mismatch, capacitor leakage, limited saturated output voltage and the like in design. In one prior art embodiment, referring to fig. 1 and 2, the charge pump is operated in three states: lead, lag, lock. The concrete working process is as follows: up=1 and dn=0 at the lead time; up=0 and dn=1 at hysteresis; when locked up=0 and dn=0. The signals upb and dnb are inversions of up and dn, respectively. Mn6 is conducted in advance, mn3 is conducted, the output node outn discharges to the ground, and the potential of the outn is reduced; mn5 is disconnected, mn4 is disconnected, the output node is charged by Mp1, and the outp potential is raised. Mn6 is disconnected during hysteresis, mn3 is disconnected, the output node outn is charged by Mp2, and the potential is increased; mn5 is conducted, mn4 is conducted, the output node outp discharges to the ground, and the potential is reduced. Mn6 is disconnected during locking, mn3 is conducted, current of MP2 flows into the ground through Mn2, and the potential of the outn is kept unchanged; mn5 is conducted, mn4 is disconnected, current of Mp1 flows into the ground through Mn1, and the outp potential is kept unchanged.
However, the prior proposal can lead to uncontrolled common mode range of the output voltage due to the adoption of differential output, and the circuit can fail when the common mode voltage is biased to the power supply voltage or the ground voltage, so that the circuit can not work normally; in addition, the current mirror adopts a single-tube structure, the output impedance is lower, and the charge and discharge of the MOS tube are unequal due to the difference of common mode points; in addition to matching factors, common mode level shifting can also be caused by load capacitance leakage of the charge pump.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a charge pump for FPGA chips. The technical problems to be solved by the invention are realized by the following technical scheme:
a charge pump for FPGA chip comprises a differential input circuit, a common mode negative feedback circuit, a current mismatch correction circuit, an output differential mode zero clearing circuit and a differential output circuit;
the differential input circuit is connected with the differential output circuit and is used for generating the final output voltage of the charge pump;
the differential output circuit comprises two output ends which are respectively connected with a common mode negative feedback circuit and a current mismatch correction circuit and is used for respectively providing a common mode detection level for the common mode negative feedback circuit and a current mismatch detection level for the current mismatch correction circuit;
The common mode negative feedback circuit is connected with the differential input circuit and is used for compensating the common mode detection level to the output end of the differential input circuit so as to stabilize a common mode signal of the output end of the differential input circuit;
the current mismatch correction circuit is connected with the differential output circuit and is used for correspondingly compensating two differential outputs according to the detected current mismatch detection level of the differential outputs so that the two differential outputs can respectively ensure that the respective charging and discharging currents are matched;
the output differential mode zero clearing circuit is connected with the differential output circuit and is used for clearing differential mode signals output by the differential pair transistors of the differential output circuit when the circuit starts to work.
Further, the circuit also comprises a bias circuit, wherein the bias circuit is connected with the current mismatch correction circuit and is used for providing bias current for the current mismatch correction circuit so as to enhance the matching of output charging and discharging currents.
Further, the phase-locked loop further comprises an enabling switch, wherein the enabling switch is connected with the biasing circuit and the common-mode negative feedback circuit and is used for controlling the common-mode negative feedback direct current detection voltage of the charge pump to be conducted or disconnected from a voltage source to a grounding end so as to reduce static power consumption when the phase-locked loop is not enabled.
Further, the differential input circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first port, a second port, a third port, and a fourth port; wherein,,
the first transistor gate is connected with a first port, the first transistor source is connected with the second transistor source and the third transistor drain, and the first transistor drain is connected with the differential output circuit;
the grid electrode of the second transistor is connected with a second port, and the drain electrode of the second transistor is connected with the differential output circuit;
the grid electrode of the third transistor is connected with the bias circuit and the grid electrode of the fourth transistor, and the source electrode of the third transistor is connected with the drain electrode of the fifth transistor;
the grid electrode of the fourth transistor is connected with the bias circuit, the source electrode of the fourth transistor is connected with the drain electrode of the sixth transistor, and the drain electrode of the fourth transistor is connected with the source electrode of the seventh transistor and the source electrode of the eighth transistor;
the grid electrode of the fifth transistor is connected with the bias circuit and the grid electrode of the sixth transistor, and the source electrode of the fifth transistor is connected with the ground terminal;
the grid electrode of the sixth transistor is connected with the bias circuit, and the source electrode of the sixth transistor is connected with the ground terminal;
The grid electrode of the seventh transistor is connected with the third port, and the drain electrode of the seventh transistor is connected with the differential output circuit;
the grid electrode of the eighth transistor is connected with the fourth port, and the drain electrode of the eighth transistor is connected with the differential output circuit.
Further, the current mismatch correction circuit includes: a first operational amplifier, a second operational amplifier, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a forty-first transistor, a forty-fourth transistor, a forty-fifth transistor; wherein,,
the non-inverting input end of the first operational amplifier is connected with the drain electrode of the forty transistor and the drain electrode of the ninth transistor, the inverting input end of the first operational amplifier is connected with the differential output circuit, the output end of the first operational amplifier is connected with the grid electrode of the tenth transistor, and the source electrode of the forty transistor is connected with the drain electrode of the forty-fourth transistor; the source electrode of the ninth transistor is connected with the drain electrode of the tenth transistor, and the grid electrode of the ninth transistor is connected with the grid electrode of the eleventh transistor and the bias circuit; the source electrode of the tenth transistor is connected with the power supply end, and the grid electrode of the tenth transistor is also connected with the grid electrode of the twelfth transistor; the eleventh transistor drain is connected with the differential output circuit, the eleventh transistor source is connected with the twelfth transistor drain, and the eleventh transistor gate is connected with the thirteenth transistor gate; the source electrode of the twelfth transistor is connected with the power supply end; the thirteenth transistor gate is connected with the fourteenth transistor gate, the thirteenth transistor source is connected with the fifteenth transistor drain, the thirteenth transistor drain is connected with the second operational amplifier non-inverting input end and the forty-first transistor drain, and the forty-first transistor source is connected with the forty-fifth transistor drain; the inverting input end of the second operational amplifier is connected with the differential output circuit; the gate of the fourteenth transistor is connected with the bias circuit, the source of the fourteenth transistor is connected with the drain of the sixteenth transistor, and the drain of the fourteenth transistor is connected with the differential output circuit; the fifteenth transistor gate is connected with the second operational amplifier output end and the sixteenth transistor gate, and the fifteenth transistor source and the sixteenth transistor source are both connected with a power supply end.
Further, the bias circuit includes: twenty-fifth, thirty-fourth, thirty-fifth, thirty-sixth, thirty-eighth, thirty-ninth, forty-fourth, forty-third, forty-sixth transistors; wherein,,
the twenty-fifth transistor gate is connected with the fourth transistor gate, the twenty-fifth transistor source is connected with the thirty-fourth transistor drain, and the twenty-fifth transistor drain is connected with a fifth port and the output differential mode zero clearing circuit;
a thirty-fourth transistor gate connected to the sixth transistor gate;
the thirty-fifth transistor source is connected with the thirty-sixth transistor drain, and the thirty-fifth transistor drain is connected with a sixth port and the output differential mode zero clearing circuit;
the thirty-eighth transistor gate is connected with the thirty-eighth transistor drain, the thirty-ninth transistor gate, the fortieth transistor gate and the fortieth-first transistor gate, and the thirty-eighth transistor source is connected with the fortieth transistor source, the fortieth-third transistor source, the fortieth-fourth transistor source, the fortieth-fifth transistor source and the ground voltage terminal; the drain electrode of the thirty-eighth transistor is connected with the output end of the first current source;
The thirty-ninth transistor source is connected to the thirteenth transistor drain, and the thirty-ninth transistor drain is connected to the forty-sixth transistor drain;
the fourth twelve transistor gate is connected with the fourth thirteenth transistor gate and connected with the forty-fourth transistor gate and the forty-fifth transistor gate, and the fourth twelve transistor drain is connected with the second current source output end;
the forty-sixth transistor gate is connected with the forty-sixth transistor drain and the ninth transistor gate, and the forty-sixth transistor source is connected with the first current source input end, the second current source input end and the power supply end.
Further, the differential output circuit includes: a thirty-third transistor and a thirty-seventh transistor;
the grid electrode of the thirteenth transistor is connected with the grid electrode of the thirty-seventh transistor, and the drain electrode of the thirteenth transistor is connected with the fifth port and the drain electrode of the eleventh transistor;
the thirty-seventh transistor drain is connected to the fourteenth transistor drain, the sixth port.
Further, the common mode negative feedback circuit includes: seventeenth transistor, eighteenth transistor, nineteenth transistor, twentieth transistor, twenty-first transistor, twenty-second transistor, twenty-third transistor, twenty-fourth transistor, twenty-seventh transistor, twenty-eighth transistor, twenty-ninth transistor, thirty-first transistor, thirty-second transistor, first resistor, second resistor; wherein,,
The seventeenth transistor gate is connected with the fifth port, the seventeenth transistor source is connected with the eighteenth transistor source and the nineteenth transistor drain, and the seventeenth transistor drain is connected with the twentieth transistor drain, the twenty first transistor drain and the twenty first transistor gate;
the gate of the eighteenth transistor is connected with the twelfth transistor, one end of a first resistor, one end of a second resistor, the positive electrode of a first capacitor and the voltage division end of a power supply, the other end of the second resistor is connected with the power supply end, and the drain of the eighteenth transistor is connected with the drain of the twenty-second transistor, the drain of the twenty-third transistor and the gate of the twenty-fourth transistor;
the nineteenth transistor gate is connected with the twenty-fifth transistor gate and the twenty-sixth transistor gate, and the nineteenth transistor source is connected with the twenty-seventh transistor drain;
the grid electrode of the twentieth transistor is connected with a sixth port, and the source electrode of the twentieth transistor is connected with the source electrode of the twenty-second transistor and the drain electrode of the twenty-sixth transistor;
the twenty-first transistor source is connected with a twenty-ninth transistor source, a thirty-fourth transistor source, the twenty-fourth transistor source and the power supply end;
The source electrode of the twenty-second transistor is connected with the drain electrode of the twenty-sixth transistor;
a thirteenth transistor gate is connected with the fourteenth transistor gate and a thirteenth transistor gate, and a source electrode of the thirteenth transistor is connected with the twenty-fourth transistor drain electrode;
the twenty-fourth transistor gate is connected to the twenty-ninth transistor gate;
the twenty-sixth transistor gate is connected with the thirty-fifth transistor gate, and the twenty-sixth transistor source is connected with the thirty-second transistor drain;
the twenty-seventh transistor gate is connected with the thirty-second transistor gate and the thirty-fourth transistor gate, and the twenty-seventh transistor source is connected with the thirty-fourth transistor source, the thirty-second transistor source, the thirty-sixth transistor source, the twenty-eighth transistor source, the first capacitor cathode and the ground voltage end;
the grid electrode of the twenty-eighth transistor is connected with the drain electrode of the twenty-eighth transistor and the other end of the first resistor;
the twenty-ninth transistor gate is connected with the thirty-third transistor gate, and the twenty-ninth transistor drain is connected with the thirteenth transistor source, the eighth transistor drain and the second transistor drain;
The thirty-sixth transistor drain is connected with the thirty-sixth transistor source, the first transistor drain and the seventh transistor drain;
the thirty-second transistor gate is connected to the thirty-sixth transistor gate.
Further, the enabling switch comprises a first enabling switch, a second enabling switch and a third enabling switch;
the first enabling switch is connected between the power end and the second resistor and used for controlling the connection or disconnection of the power end and the second resistor path;
the second enabling switch is connected between the grid electrode of the fourth twelve transistor and the ground voltage end;
the third enable switch is connected between the thirty-eighth transistor gate and the ground voltage terminal.
Further, the first enabling switch, the second enabling switch and the third enabling switch are transistor switches.
Compared with the prior art, the invention has the beneficial effects that:
according to the charge pump for the FPGA chip, the common mode voltage of the differential output circuit is monitored through the designed common mode negative feedback circuit, so that the current is dynamically adjusted, the final output of the charge pump is ensured to always trend to the set voltage, and the normal operation of the circuit is ensured; in addition, the invention is beneficial to solving the problem of electric leakage of the large-size capacitor of the post-stage filter; meanwhile, due to the fact that the unmatched current correction circuit is introduced, when the output voltage is at any value, matching performance of charging current and discharging current of the output end is improved, the fact that a charge pump has a linear single-step voltage step in a large-range output voltage is guaranteed, and linearity of the charge pump is further improved.
Drawings
Fig. 1 is a schematic diagram of a prior art charge pump circuit.
Fig. 2 is a circuit diagram of a charge pump in one specific application of the prior art.
Fig. 3 is a block diagram of a charge pump module for an FPGA chip of the present invention.
Fig. 4 is a block diagram of a charge pump module for an FPGA chip in another embodiment of the invention.
Fig. 5 is a circuit diagram of a charge pump for an FPGA chip in one embodiment of the invention.
Fig. 6 is a schematic diagram of a charge pump in advanced operating conditions according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a charge pump hysteresis operating condition in one embodiment of the present invention.
Fig. 8 is a schematic diagram of a charge pump in a locked operating state according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1:
fig. 3 is a block diagram of a charge pump module for an FPGA chip according to an embodiment of the present invention, including a differential input circuit 1, a common mode negative feedback circuit 2, a current mismatch correction circuit 3, an output differential mode clear circuit 4, and a differential output circuit 5;
the differential input circuit 1 is connected with the differential output circuit 5 and is used for generating the final output voltage of the charge pump;
The differential output circuit 5 comprises two output ends which are respectively connected with the common mode negative feedback circuit 2 and the current mismatch correction circuit 3 and are used for respectively providing a common mode detection level for the common mode negative feedback circuit 2 and a current mismatch detection level for the current mismatch correction circuit 3;
the common mode negative feedback circuit 2 is connected with the differential input circuit 1 and is used for compensating the common mode detection level to the output end of the differential input circuit 1 so as to stabilize a common mode signal of the output end of the differential input circuit 1;
the current mismatch correction circuit 3 is connected with the differential output circuit 5 and is used for correspondingly compensating two differential outputs according to the detected current mismatch detection level of the differential outputs so that the two differential outputs can respectively ensure that the respective charging and discharging currents are matched;
the output differential mode zero clearing circuit 4 is connected with the differential output circuit 5 and is used for clearing differential mode signals output by the differential pair transistors of the differential output circuit 5 when the circuit starts to work.
The charge pump provided by the invention weakens the influence of common mode change of output voltage on current matching, enhances the matching of respective charging current and discharging current of two output branches under different output voltages, and improves the linearity of the charge pump.
In a specific embodiment, referring to fig. 4, the circuit further comprises a bias circuit 6, wherein the bias circuit 6 is connected with the current mismatch correction circuit 3 and is used for providing bias current to the current mismatch correction circuit 3 so as to enhance matching of output charging and discharging currents. ,
in a specific embodiment, the circuit further includes an enable switch 7, where the enable switch 7 is connected to the bias circuit 6 and the common mode negative feedback circuit 2, and is used to control the connection or disconnection of the common mode negative feedback dc detection voltage of the charge pump from the voltage source to the ground, so as to reduce the static power consumption when the phase-locked loop is not enabled.
This implementation provides a specific example to better describe the concept of the present invention, see the circuit diagram shown in fig. 5. The differential input circuit 1 includes: a first transistor xi7, a second transistor xi6, a third transistor xi5, a fourth transistor xi2, a fifth transistor xi4, a sixth transistor xi3, a seventh transistor xi0, an eighth transistor xi1, a first port dnb, a second port dn, a third port up, a fourth port upb; wherein,,
the grid electrode of the first transistor xi7 is connected with the first port dnb, the source electrode of the first transistor xi7 is connected with the source electrode of the second transistor xi6 and the drain electrode of the third transistor xi5, and the drain electrode of the first transistor xi7 is connected with the differential output circuit 5;
The grid electrode of the second transistor xi6 is connected with the second port dn, and the drain electrode of the second transistor xi6 is connected with the differential output circuit 5;
the grid electrode of the third transistor xi5 is connected with the grid electrodes of the bias circuit 6 and the fourth transistor xi2, and the source electrode of the third transistor xi5 is connected with the drain electrode of the fifth transistor xi 4;
the grid electrode of the fourth transistor xi2 is connected with the bias circuit 6, the source electrode of the fourth transistor xi2 is connected with the drain electrode of the sixth transistor xi3, and the drain electrode of the fourth transistor xi2 is connected with the source electrode of the seventh transistor xi0 and the source electrode of the eighth transistor xi 1;
the grid electrode of the fifth transistor xi4 is connected with the bias circuit 6 and the grid electrode of the sixth transistor xi3, and the source electrode of the fifth transistor xi4 is connected with the ground terminal;
the grid electrode of the sixth transistor xi3 is connected with the bias circuit 6, and the source electrode of the sixth transistor xi3 is connected with the ground terminal;
the grid electrode of the seventh transistor xi0 is connected with the third port up, and the drain electrode of the seventh transistor xi0 is connected with the differential output circuit 5;
the gate of the eighth transistor xi1 is connected to the fourth port upb, and the drain of the eighth transistor xi1 is connected to the differential output circuit 5.
The current mismatch correction circuit 3 includes: the first operational amplifier I11, the second operational amplifier I12, the ninth transistor M3, the tenth transistor M2, the eleventh transistor M5, the twelfth transistor M6, the thirteenth transistor M11, the fourteenth transistor M10, the fifteenth transistor M13, the sixteenth transistor M12, the fortieth transistor M1, the fortieth transistor M9, the fortieth transistor M0, the fortieth transistor M8; wherein,,
The non-inverting input end of the first operational amplifier I11 is connected with the drain electrode of the forty transistor M1 and the drain electrode of the ninth transistor M3, the inverting input end of the first operational amplifier I11 is connected with the differential output circuit 5, the output end of the first operational amplifier I11 is connected with the grid electrode of the tenth transistor M2, and the source electrode of the forty transistor M1 is connected with the drain electrode of the forty-four transistor M0; the source electrode of the ninth transistor M3 is connected to the drain electrode of the tenth transistor M2, and the gate electrode of the ninth transistor M3 is connected to the gate electrode of the eleventh transistor M5, and the bias circuit 6; the source electrode of the tenth transistor M2 is connected with the power supply end, and the grid electrode of the tenth transistor M2 is also connected with the grid electrode of the twelfth transistor M6; the drain electrode of the eleventh transistor M5 is connected to the differential output circuit 5, the source electrode of the eleventh transistor M5 is connected to the drain electrode of the twelfth transistor M6, and the gate electrode of the eleventh transistor M5 is connected to the gate electrode of the thirteenth transistor M11; the source electrode of the twelfth transistor M6 is connected with the power supply end; the gate of the thirteenth transistor M11 is connected to the gate of the fourteenth transistor M10, the source of the thirteenth transistor M11 is connected to the drain of the fifteenth transistor M13, the drain of the thirteenth transistor M11 is connected to the non-inverting input terminal of the second operational amplifier I12, the drain of the forty-first transistor M9, and the source of the forty-first transistor M9 is connected to the drain of the forty-fifth transistor M8; the inverting input end of the second operational amplifier I12 is connected with the differential output circuit 5; the grid electrode of the fourteenth transistor M10 is connected with the bias circuit 6, the source electrode of the fourteenth transistor M10 is connected with the drain electrode of the sixteenth transistor M12, and the drain electrode of the fourteenth transistor M10 is connected with the differential output circuit 5; the grid electrode of the fifteenth transistor M13 is connected with the output end of the second operational amplifier I12 and the grid electrode of the sixteenth transistor M12, and the source electrode of the fifteenth transistor M13 and the source electrode of the sixteenth transistor M12 are both connected with a power supply end.
The bias circuit 6 includes: twenty-fifth transistor xi8, thirty-fourth transistor xi9, thirty-fifth transistor xi11, thirty-sixth transistor xi10, thirty-eighth transistor xi56, thirty-ninth transistor xi44, forty-second transistor M4, forty-third transistor xi45, forty-sixth transistor xi43; wherein,,
the grid electrode of the twenty-fifth transistor xi8 is connected with the grid electrode of the fourth transistor xi2, the source electrode of the twenty-fifth transistor xi8 is connected with the drain electrode of the thirty-fourth transistor xi9, and the drain electrode of the twenty-fifth transistor xi8 is connected with a fifth port cpi_p and the output differential mode zero clearing circuit 4;
a thirty-fourth transistor xi9 gate is connected to the sixth transistor xi3 gate;
the source electrode of the thirty-fifth transistor xi11 is connected with the drain electrode of the thirty-sixth transistor xi10, and the drain electrode of the thirty-fifth transistor xi11 is connected with a sixth port cpi_n and the output differential mode zero clearing circuit 4;
the thirty-eighth transistor xi56 gate is connected with the thirty-eighth transistor xi56 drain, the thirty-ninth transistor xi44 gate, the forty-first transistor M1 gate and the forty-first transistor M9 gate, and the thirty-eighth transistor xi56 source is connected with the forty-second transistor M4 source, the forty-third transistor xi45 source, the forty-fourth transistor M0 source, the forty-fifth transistor M8 source and the ground voltage terminal; the drain electrode of the thirty-eighth transistor xi56 is connected with the output end of the first current source I6;
The source of the thirty-ninth transistor xi44 is connected with the drain of the thirteenth transistor xi45, and the drain of the thirty-ninth transistor xi44 is connected with the drain of the forty-sixth transistor xi 43;
the grid electrode of the forty-third transistor M4 is connected with the grid electrode of the forty-third transistor xi45 and is connected with the grid electrode of the forty-fourth transistor M0 and the grid electrode of the forty-fifth transistor M8, and the drain electrode of the forty-third transistor M4 is connected with the output end of the second current source I5;
the grid electrode of the forty-sixth transistor xi43 is connected with the drain electrode of the forty-sixth transistor xi43 and the grid electrode of the ninth transistor M3, and the source electrode of the forty-sixth transistor xi43 is connected with the input end of the first current source I6, the input end of the second current source I5 and the power supply end.
The differential output circuit 5 includes: thirty-third transistor xi13, thirty-seventh transistor xi12;
the gate of the thirty-third transistor xi13 is connected with the gate of the thirty-seventh transistor xi12, and the drain of the thirty-third transistor xi13 is connected with the fifth port cpi_p and the drain of the eleventh transistor M5;
the drain of the thirty-seventh transistor xi12 is connected to the drain of the fourteenth transistor M10 and the sixth port cpi_n.
The common mode negative feedback circuit 2 includes: seventeenth transistor xi42, eighteenth transistor xi41, nineteenth transistor xi38, twentieth transistor xi39, twenty first transistor xi47, twenty second transistor xi40, twenty third transistor xi48, twenty fourth transistor xi49, twenty seventh transistor xi37, twenty eighth transistor xi112, twenty ninth transistor xi14, thirty first transistor xi15, thirty second transistor xi36, first resistor xi109, second resistor xi105; wherein,,
The gate of the seventeenth transistor xi42 is connected with the fifth port cpi_p, the source of the seventeenth transistor xi42 is connected with the source of the eighteenth transistor xi41 and the drain of the nineteenth transistor xi38, and the drain of the seventeenth transistor xi42 is connected with the drain of the twentieth transistor xi39, the drain of the twenty-first transistor xi47 and the gate of the twenty-first transistor xi 47;
the gate of the eighteenth transistor xi41 is connected with the twenty-second transistor xi40, one end of the first resistor xi109, one end of the second resistor xi105, the positive electrode of the first capacitor xi96 and the voltage division end vcom of the power supply, the other end of the second resistor xi105 is connected with the power supply end, and the drain of the eighteenth transistor xi41 is connected with the drain of the twenty-second transistor xi40, the drain of the twenty-third transistor xi48 and the gate of the twenty-fourth transistor xi 49;
the grid electrode of the nineteenth transistor xi38 is connected with the grid electrode of the twenty-fifth transistor xi8 and the grid electrode of the twenty-sixth transistor xi35, and the source electrode of the nineteenth transistor xi38 is connected with the drain electrode of the twenty-seventh transistor xi 37;
the grid electrode of the twentieth transistor xi39 is connected with a sixth port cpi_n, and the source electrode of the twentieth transistor xi39 is connected with the source electrode of the twenty-second transistor xi40 and the drain electrode of the twenty-sixth transistor xi 35;
The source electrode of the twenty-first transistor xi47 is connected with the source electrode of the twenty-ninth transistor xi14, the source electrode of the thirty-fourth transistor xi15, the source electrode of the twenty-fourth transistor xi49 and the power supply end;
the source electrode of the twenty-sixth transistor xi40 is connected with the drain electrode of the twenty-sixth transistor xi 35;
a gate of the twenty-third transistor xi48 is connected to a gate of the fourteenth transistor M10 and a gate of the thirty-third transistor xi13, and a source of the twenty-third transistor xi48 is connected to a drain of the twenty-fourth transistor xi 49;
the grid electrode of the twenty-fourth transistor xi49 is connected with the grid electrode of the twenty-ninth transistor xi 14;
the grid electrode of the twenty-sixth transistor xi35 is connected with the grid electrode of the thirty-fifth transistor xi11, and the source electrode of the twenty-sixth transistor xi35 is connected with the drain electrode of the thirty-second transistor xi 36;
the twenty-seventh transistor xi37 grid electrode is connected with the thirty-second transistor xi36 grid electrode and the thirty-fourth transistor xi9 grid electrode, the twenty-seventh transistor xi37 source electrode is connected with the thirty-fourth transistor xi9 source electrode, the thirty-second transistor xi36 source electrode, the thirty-sixth transistor xi10 source electrode, the twenty-eighth transistor xi112 source electrode, the first capacitor xi96 cathode electrode and the ground voltage end;
The grid electrode of the twenty-eighth transistor xi112 is connected with the drain electrode of the twenty-eighth transistor xi112 and the other end of the first resistor xi 109;
the grid electrode of the twenty-ninth transistor xi14 is connected with the grid electrode of the thirty-third transistor xi15, and the drain electrode of the twenty-ninth transistor xi14 is connected with the source electrode of the thirteenth transistor xi13, the drain electrode of the eighth transistor xi1 and the drain electrode of the second transistor xi 6;
the drain electrode of the thirty-sixth transistor xi15 is connected with the source electrode of the thirty-sixth transistor xi12, the drain electrode of the first transistor xi7 and the drain electrode of the seventh transistor xi 0;
the thirty-sixth transistor xi10 gate is connected to the thirty-sixth transistor xi36 gate.
In a specific embodiment, the enabling switch 7 includes a first enabling switch xi29, a second enabling switch M7, and a third enabling switch xi77;
the first enabling switch xi29 is connected between the power end and the second resistor xi105 and is used for controlling the connection or disconnection of the power end and the second resistor xi 105;
the second enabling switch M7 is connected between the grid electrode of the forty-second transistor M4 and the ground voltage end;
the third enable switch xi77 is connected between the thirty-eighth transistor xi56 gate and the ground voltage terminal.
Preferably, the first enabling switch xi29, the second enabling switch M7 and the third enabling switch xi77 are all transistor switches.
The working principle of the charge pump is described below with respect to the specific circuit diagram, before the charge pump works, the charge pump controls the I8 transmission gate to short the cpi_p and the cpi_n ports through the cp_rst port, and the differential mode signal of differential output is cleared, so that the starting error of the charge pump is ensured to be zero.
As shown in fig. 6-8, three operating states of the charge pump correspond in sequence: up (advance), dn (retard), idle (idle, locked). The voltage of (icp+iup_adj) > Icn, cpi_p rises at the time of advance; (icp+idn_adj) < (idnb+iup+icn), cpi_n voltage drops. Hysteresis (icp+iup_adj) < (idn+iupb+icn), cpi_p voltage drops; (icp+idn_adj) > Icn, cpi_n voltage rises. When locked (icp+iup_adj) = (iupb+icn), the cpi_p voltage is unchanged; (icp+idn_adj) = (idnb+icn), the cpi_n voltage is unchanged. Icn in fig. 6 is xi9 and xi10 in the schematic. The capacitance in the dashed box is part of the next stage of the module low pass filter of the charge pump.
Specifically, vcom is a divided voltage of the power supply voltage, and the power supply voltage is fixed, so vcom is a fixed voltage value set. Differential pair xi 39-xi 42 monitors the common mode voltages at outputs cpi_p and cpi_n. vcom voltage is compared to the common mode voltage, and at common mode voltages below vcom, the current of xi37 and xi36 increases mostly through xi40 and xi41, i.e., xi 49. While xi14 and xi15 currents are proportional to xi49 currents, so that the currents flowing through the output terminals cpi_p and cpi_n are larger than the pull-down currents of xi9 and xi10, the common-mode voltages of cpi_p and cpi_n rise until the common-mode voltages of cpi_p and cpi_n are equal, and the adjustment is stopped. The negative feedback circuit can stabilize the output common-mode voltage so that the final output common-mode voltage is equal to the vcom voltage selected by the design. When the charge pump detects that two input clocks of a PLL (phase locked loop) have a frequency difference or a phase difference, voltages of the output cpi_p and the output cpi_n of the charge pump circuit respectively move to a power supply voltage and a ground voltage, in order to ensure that when the frequencies or the phases of the two input clocks of the PLL have abrupt changes, a large signal response of the circuit has enough margin, so that the cpi_p and the cpi_n cannot be flung to the power supply voltage and the ground voltage to generate nonlinear distortion. When the differential output is not in the middle of the output common mode range, the charge and discharge branches of the charge pump can cause circuit mismatch due to limited output impedance. Meanwhile, the sleeve current mirror in the circuit increases the output impedance of the output end, so that the output current is weakly related to the output voltage, and the consistency of the current at different output voltages is ensured. The voltage dividing branch and the current source branch are affected by xi29, M7 and xi77, the pwdnbb of the circuit controls the three MOS tubes, the passage from the power supply to the ground of the charge pump circuit is closed, and the static power consumption of the charge pump circuit is eliminated.
According to the charge pump for the FPGA chip, the common mode voltage of the differential output circuit is monitored through the designed common mode negative feedback circuit, so that the current is dynamically adjusted, the final output of the charge pump is ensured to always trend to the set voltage, and the normal operation of the circuit is ensured; in addition, the invention is beneficial to solving the problem of electric leakage of the large-size capacitor of the post-stage filter; meanwhile, due to the fact that the unmatched current correction circuit is introduced, when the output voltage is at any value, matching performance of charging current and discharging current of the output end is improved, the fact that a charge pump has a linear single-step voltage step in a large-range output voltage is guaranteed, and linearity of the charge pump is further improved.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (4)
1. The charge pump for the FPGA chip is characterized by comprising a differential input circuit (1), a common mode negative feedback circuit (2), a current mismatch correction circuit (3), an output differential mode zero clearing circuit (4), a differential output circuit (5) and a bias circuit (6);
The differential input circuit (1) is connected with the differential output circuit (5) and is used for generating the final output voltage of the charge pump;
the differential output circuit (5) comprises two output ends which are respectively connected with the common-mode negative feedback circuit (2) and the current mismatch correction circuit (3) and is used for respectively providing a common-mode detection level for the common-mode negative feedback circuit (2) and a current mismatch detection level for the current mismatch correction circuit (3);
the common mode negative feedback circuit (2) is connected with the differential input circuit (1) and is used for compensating the common mode detection level to the output end of the differential input circuit (1) so as to stabilize a common mode signal of the output end of the differential input circuit (1);
the current mismatch correction circuit (3) is connected with the differential output circuit (5) and is used for correspondingly compensating two differential outputs according to the detected current mismatch detection level of the differential outputs so that the two differential outputs can respectively ensure that the respective charging and discharging currents are matched;
the output differential mode zero clearing circuit (4) is connected with the differential output circuit (5) and is used for clearing differential mode signals output by the differential pair transistors of the differential output circuit (5) when the circuit starts to work;
the bias circuit (6) is connected with the current mismatch correction circuit (3) and is used for providing bias current for the current mismatch correction circuit (3) so as to enhance the matching of output charging and discharging currents;
The differential input circuit (1) includes: a first transistor (xi 7), a second transistor (xi 6), a third transistor (xi 5), a fourth transistor (xi 2), a fifth transistor (xi 4), a sixth transistor (xi 3), a seventh transistor (xi 0), an eighth transistor (xi 1), a first port (dnb), a second port (dn), a third port (up), a fourth port (upb); wherein,,
the grid electrode of the first transistor (xi 7) is connected with a first port (dnb), the source electrode of the first transistor (xi 7) is connected with the source electrode of the second transistor (xi 6) and the drain electrode of the third transistor (xi 5), and the drain electrode of the first transistor (xi 7) is connected with the differential output circuit (5);
the grid electrode of the second transistor (xi 6) is connected with a second port (dn), and the drain electrode of the second transistor (xi 6) is connected with the differential output circuit (5);
the grid electrode of the third transistor (xi 5) is connected with the grid electrodes of the bias circuit (6) and the fourth transistor (xi 2), and the source electrode of the third transistor (xi 5) is connected with the drain electrode of the fifth transistor (xi 4);
the grid electrode of the fourth transistor (xi 2) is connected with the bias circuit (6), the source electrode of the fourth transistor (xi 2) is connected with the drain electrode of the sixth transistor (xi 3), and the drain electrode of the fourth transistor (xi 2) is connected with the source electrode of the seventh transistor (xi 0) and the source electrode of the eighth transistor (xi 1);
The grid electrode of the fifth transistor (xi 4) is connected with the bias circuit (6) and the grid electrode of the sixth transistor (xi 3), and the source electrode of the fifth transistor (xi 4) is connected with the ground terminal;
the grid electrode of the sixth transistor (xi 3) is connected with the bias circuit (6), and the source electrode of the sixth transistor (xi 3) is connected with the ground terminal;
-the seventh transistor (xi 0) has a gate connected to the third port (up), and the seventh transistor (xi 0) has a drain connected to the differential output circuit (5);
the grid electrode of the eighth transistor (xi 1) is connected with the fourth port (upb), and the drain electrode of the eighth transistor (xi 1) is connected with the differential output circuit (5);
the current mismatch correction circuit (3) includes: a first operational amplifier (I11), a second operational amplifier (I12), a ninth transistor (M3), a tenth transistor (M2), an eleventh transistor (M5), a twelfth transistor (M6), a thirteenth transistor (M11), a fourteenth transistor (M10), a fifteenth transistor (M13), a sixteenth transistor (M12), a fortieth transistor (M1), a fortieth-first transistor (M9), a fortieth-fourth transistor (M0), a fortieth-fifth transistor (M8); wherein,,
the non-inverting input end of the first operational amplifier (I11) is connected with the drain electrode of the forty transistor (M1) and the drain electrode of the ninth transistor (M3), the inverting input end of the first operational amplifier (I11) is connected with the differential output circuit (5), the output end of the first operational amplifier (I11) is connected with the grid electrode of the forty transistor (M2), and the source electrode of the forty transistor (M1) is connected with the drain electrode of the forty transistor (M0); the source electrode of the ninth transistor (M3) is connected with the drain electrode of the tenth transistor (M2), and the grid electrode of the ninth transistor (M3) is connected with the grid electrode of the eleventh transistor (M5) and the bias circuit (6); the source electrode of the tenth transistor (M2) is connected with the power supply end, and the grid electrode of the tenth transistor (M2) is also connected with the grid electrode of the twelfth transistor (M6); the drain electrode of the eleventh transistor (M5) is connected with the differential output circuit (5), the source electrode of the eleventh transistor (M5) is connected with the drain electrode of the twelfth transistor (M6), and the grid electrode of the eleventh transistor (M5) is connected with the grid electrode of the thirteenth transistor (M11); the source electrode of the twelfth transistor (M6) is connected with the power supply end; the gate of the thirteenth transistor (M11) is connected with the gate of the fourteenth transistor (M10), the source of the thirteenth transistor (M11) is connected with the drain of the fifteenth transistor (M13), the drain of the thirteenth transistor (M11) is connected with the non-inverting input end of the second operational amplifier (I12) and the drain of the forty-first transistor (M9), and the source of the forty-first transistor (M9) is connected with the drain of the forty-fifth transistor (M8); the inverting input end of the second operational amplifier (I12) is connected with the differential output circuit (5); the grid electrode of the fourteenth transistor (M10) is connected with the bias circuit (6), the source electrode of the fourteenth transistor (M10) is connected with the drain electrode of the sixteenth transistor (M12), and the drain electrode of the fourteenth transistor (M10) is connected with the differential output circuit (5); the grid electrode of the fifteenth transistor (M13) is connected with the output end of the second operational amplifier (I12) and the grid electrode of the sixteenth transistor (M12), and the source electrode of the fifteenth transistor (M13) and the source electrode of the sixteenth transistor (M12) are connected with a power supply end;
The bias circuit (6) includes: a twenty-fifth transistor (xi 8), a thirty-fourth transistor (xi 9), a thirty-fifth transistor (xi 11), a thirty-sixth transistor (xi 10), a thirty-eighth transistor (xi 56), a thirty-ninth transistor (xi 44), a fortieth transistor (M4), a fortieth transistor (xi 45), a fortieth transistor (xi 43); wherein,,
the grid electrode of the twenty-fifth transistor (xi 8) is connected with the grid electrode of the fourth transistor (xi 2), the source electrode of the twenty-fifth transistor (xi 8) is connected with the drain electrode of the thirty-fourth transistor (xi 9), and the drain electrode of the twenty-fifth transistor (xi 8) is connected with a fifth port (cpi_p) and the output differential mode zero clearing circuit (4);
a thirty-fourth transistor (xi 9) gate connected to the sixth transistor (xi 3) gate;
the source electrode of the thirty-fifth transistor (xi 11) is connected with the drain electrode of the thirty-sixth transistor (xi 10), and the drain electrode of the thirty-fifth transistor (xi 11) is connected with a sixth port (cpi_n) and the output differential mode zero clearing circuit (4);
the thirty-eighth transistor (xi 56) gate is connected with the thirty-eighth transistor (xi 56) drain, the thirty-ninth transistor (xi 44) gate, the fortieth transistor (M1) gate and the fortieth-first transistor (M9) gate, and the thirty-eighth transistor (xi 56) source is connected with the fortieth transistor (M4) source, the fortieth-third transistor (xi 45) source, the fortieth-fourth transistor (M0) source, the fortieth-fifth transistor (M8) source and the ground voltage terminal; the drain electrode of the thirty-eighth transistor (xi 56) is connected with the output end of the first current source (I6);
The source of the thirty-ninth transistor (xi 44) is connected with the drain of the thirteenth transistor (xi 45), and the drain of the thirty-ninth transistor (xi 44) is connected with the drain of the forty-sixth transistor (xi 43);
the grid electrode of the forty-third transistor (M4) is connected with the grid electrode of the forty-third transistor (xi 45) and is connected with the grid electrode of the forty-fourth transistor (M0) and the grid electrode of the forty-fifth transistor (M8), and the drain electrode of the forty-third transistor (M4) is connected with the output end of the second current source (I5);
the grid electrode of the forty-sixth transistor (xi 43) is connected with the drain electrode of the forty-sixth transistor (xi 43) and the grid electrode of the ninth transistor (M3), and the source electrode of the forty-sixth transistor (xi 43) is connected with the input end of the first current source (I6), the input end of the second current source (I5) and the power supply end;
the differential output circuit (5) includes: a thirty-third transistor (xi 13), a thirty-seventh transistor (xi 12);
the grid electrode of the thirty-third transistor (xi 13) is connected with the grid electrode of a thirty-seventh transistor (xi 12), and the drain electrode of the thirty-third transistor (xi 13) is connected with the fifth port (cpi_p) and the drain electrode of the eleventh transistor (M5);
-the thirty-seventh transistor (xi 12) drain is connected to the fourteenth transistor (M10) drain, the sixth port (cpi_n);
The common mode negative feedback circuit (2) comprises: seventeenth transistor (xi 42), eighteenth transistor (xi 41), nineteenth transistor (xi 38), twentieth transistor (xi 39), twenty first transistor (xi 47), twenty second transistor (xi 40), twenty third transistor (xi 48), twenty fourth transistor (xi 49), twenty seventh transistor (xi 37), twenty eighth transistor (xi 112), twenty ninth transistor (xi 14), thirty second transistor (xi 15), thirty second transistor (xi 36), first resistor (xi 109), second resistor (xi 105), wherein,
the grid electrode of the seventeenth transistor (xi 42) is connected with the fifth port (cpi_p), the source electrode of the seventeenth transistor (xi 42) is connected with the source electrode of the eighteenth transistor (xi 41) and the drain electrode of the nineteenth transistor (xi 38), and the drain electrode of the seventeenth transistor (xi 42) is connected with the drain electrode of the twentieth transistor (xi 39), the drain electrode of the twenty first transistor (xi 47) and the grid electrode of the twenty first transistor (xi 47);
the grid electrode of the eighteenth transistor (xi 41) is connected with the drain electrode of the twenty-second transistor (xi 40), one end of a first resistor (xi 109), one end of a second resistor (xi 105), the positive electrode of a first capacitor (xi 96) and a power supply voltage division end (vcom), the other end of the second resistor (xi 105) is connected with the power supply end, and the drain electrode of the eighteenth transistor (xi 41) is connected with the drain electrode of the twenty-second transistor (xi 40), the drain electrode of a twenty-third transistor (xi 48) and the grid electrode of a twenty-fourth transistor (xi 49);
The grid electrode of the nineteenth transistor (xi 38) is connected with the grid electrode of a twenty-fifth transistor (xi 8) and the grid electrode of a twenty-sixth transistor (xi 35), and the source electrode of the nineteenth transistor (xi 38) is connected with the drain electrode of a twenty-seventh transistor (xi 37);
-the twentieth transistor (xi 39) gate is connected to the sixth port (cpi_n), the twentieth transistor (xi 39) source is connected to the twenty-second transistor (xi 40) source, the twenty-sixth transistor (xi 35) drain;
the source of the twenty-first transistor (xi 47) is connected with the source of the twenty-ninth transistor (xi 14), the source of the thirty-fourth transistor (xi 15), the source of the twenty-fourth transistor (xi 49) and the power supply end;
the source of the twenty-sixth transistor (xi 40) is connected with the drain of the twenty-sixth transistor (xi 35);
a twenty-third transistor (xi 48) gate is connected to the fourteenth transistor (M10) gate and a thirty-third transistor (xi 13) gate, and a twenty-third transistor (xi 48) source is connected to the twenty-fourth transistor (xi 49) drain;
-the twenty-fourth transistor (xi 49) gate is connected to the twenty-ninth transistor (xi 14) gate;
the grid electrode of the twenty-sixth transistor (xi 35) is connected with the grid electrode of the thirty-fifth transistor (xi 11), and the source electrode of the twenty-sixth transistor (xi 35) is connected with the drain electrode of the thirty-second transistor (xi 36);
The twenty-seventh transistor (xi 37) gate is connected with the gate of the thirty-second transistor (xi 36) and the gate of the thirty-fourth transistor (xi 9), the twenty-seventh transistor (xi 37) source is connected with the source of the thirty-fourth transistor (xi 9), the source of the thirty-second transistor (xi 36), the source of the thirty-sixth transistor (xi 10), the source of the twenty-eighth transistor (xi 112), the negative electrode of the first capacitor (xi 96) and the ground voltage end;
the grid electrode of the twenty-eighth transistor (xi 112) is connected with the drain electrode of the twenty-eighth transistor (xi 112) and the other end of the first resistor (xi 109);
the grid electrode of the twenty-ninth transistor (xi 14) is connected with the grid electrode of the thirty-third transistor (xi 15), and the drain electrode of the twenty-ninth transistor (xi 14) is connected with the source electrode of the thirteenth-third transistor (xi 13), the drain electrode of the eighth transistor (xi 1) and the drain electrode of the second transistor (xi 6);
-the thirty-sixth transistor (xi 12) source, the first transistor (xi 7) drain, the seventh transistor (xi 0) drain are connected to the thirty-sixth transistor (xi 15) drain;
a thirty-sixth transistor (xi 36) gate is connected to the thirty-sixth transistor (xi 10) gate.
2. The charge pump for FPGA chips of claim 1, further comprising an enable switch (7), the enable switch (7) connecting the bias circuit (6) and the common mode negative feedback circuit (2) for controlling the on or off of the common mode negative feedback dc detection voltage of the charge pump from a voltage source to ground to reduce static power consumption when the phase locked loop is not enabled.
3. Charge pump for FPGA chips according to claim 2, characterized in that the enabling switch (7) comprises a first enabling switch (xi 29), a second enabling switch (M7), a third enabling switch (xi 77);
the first enabling switch (xi 29) is connected between the power end and the second resistor (xi 105) and is used for controlling the connection or disconnection of the power end and the second resistor (xi 105);
the second enabling switch (M7) is connected between the grid electrode of the fourth twelve transistor (M4) and the ground voltage end;
the third enable switch (xi 77) is connected between the thirty-eighth transistor (xi 56) gate and the ground voltage terminal.
4. A charge pump for FPGA chips according to claim 3, characterized in that the first enabling switch (xi 29), the second enabling switch (M7), the third enabling switch (xi 77) are all transistor switches.
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| CN110491333B (en) | 2019-10-15 | 2020-01-21 | 上海视欧光电科技有限公司 | Interpolation operational amplifier circuit and display panel |
| CN111064358B (en) * | 2019-11-25 | 2021-09-21 | 北京时代民芯科技有限公司 | Charge pump circuit with self-calibration function and programmable current |
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| CN103888093A (en) * | 2014-04-17 | 2014-06-25 | 苏州坤信微电子科技有限公司 | Common-mode level reset circuit for differential signals |
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| CN106026997A (en) * | 2016-06-21 | 2016-10-12 | 四川和芯微电子股份有限公司 | Differential comparator |
| CN207573238U (en) * | 2017-12-06 | 2018-07-03 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
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| US6275097B1 (en) * | 1999-04-02 | 2001-08-14 | S3 Incorporated, Inc. | Differential charge pump with low voltage common mode feedback circuit |
| TW531965B (en) * | 2001-12-07 | 2003-05-11 | Mediatek Inc | Differential charge pump |
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| KR20030028312A (en) * | 2001-09-29 | 2003-04-08 | 주식회사 스텔시스텔레콤 | Charge Pump Circuit for PLL |
| CN103888093A (en) * | 2014-04-17 | 2014-06-25 | 苏州坤信微电子科技有限公司 | Common-mode level reset circuit for differential signals |
| CN103956982A (en) * | 2014-05-05 | 2014-07-30 | 华侨大学 | Common-mode feedback circuit for duration of two-stage differential amplifier |
| CN106026997A (en) * | 2016-06-21 | 2016-10-12 | 四川和芯微电子股份有限公司 | Differential comparator |
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