CN107749709A - A kind of charge pump for fpga chip - Google Patents
A kind of charge pump for fpga chip Download PDFInfo
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- CN107749709A CN107749709A CN201711275968.5A CN201711275968A CN107749709A CN 107749709 A CN107749709 A CN 107749709A CN 201711275968 A CN201711275968 A CN 201711275968A CN 107749709 A CN107749709 A CN 107749709A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a kind of charge pump for fpga chip, including Differential input circuit, Commom-mode feedback circuit, electric current to mismatch correcting circuit, output differential mode clear circuit, differential output circuit；The Differential input circuit connects the differential output circuit, for producing the final output voltage of charge pump；The differential output circuit includes two output ends, Commom-mode feedback circuit is connected respectively and electric current mismatches correcting circuit, and detection level is mismatched for providing common mode detection level to the Commom-mode feedback circuit respectively, providing electric current to electric current mismatch correcting circuit；The Commom-mode feedback circuit connects Differential input circuit, for the common mode to be detected into level compensation to the output end of Differential input circuit；The electric current mismatches correcting circuit and connects the differential output circuit, for mismatching detection level two difference outputs of corresponding compensation according to the electric current of the difference output detected.The present invention improves the charge pump linearity.
Description
Technical field
The invention belongs to clock control field, and in particular to a kind of charge pump for fpga chip.
Background technology
FPGA (Field-Programmable Gate Array, field programmable gate array) is by the logic list of many
The logical device that member is formed, wherein logic unit includes door, look-up table and trigger, it have enrich hardware resource, it is powerful simultaneously
Row disposal ability and flexible reconfigurable ability, obtained in many fields such as data processing, communication, network increasing wide
General application.Generally there are multiple PLL (Phase Locked Loop, phaselocked loop) inside FPGA.PLL is used to generate inside FPGA
The clock of high-quality.PLL is generally made up of phase discriminator, charge pump, wave filter, voltage controlled oscillator, frequency divider.Charge pump is FPGA
Middle PLL important component.
Generally there is charging and discharging currents mismatch in charge pump, capacitor element electric leakage, saturation output voltage are limited in the design
The problems such as.In a kind of existing embodiment, referring to Fig. 1 and Fig. 2, three kinds of working conditions of charge pump：In advance, lag, locking.
Its specific work process is：Up=1, dn=0 when advanced；Up=0 during hysteresis, dn=1；Up=0 during locking, dn=0.Signal
Upb and dnb is the anti-phase of up and dn respectively.Mn6 is turned on when advanced, and Mn3 conductings, output node outn discharges over the ground, outn electricity
Potential drop is low；Mn5 disconnects, and Mn4 disconnects, and output node is charged by Mp1, the rise of outp current potentials.Mn6 disconnects during hysteresis, and Mn3 disconnects,
Output node outn is charged by Mp2, current potential rise；Mn5 is turned on, and Mn4 conductings, output node outp discharges over the ground, and current potential reduces.
Mn6 disconnects during locking, Mn3 conductings, and Mp2 electric current all flows into ground through Mn2, and outn current potentials keep constant；Mn5 is turned on, and Mn4 breaks
Open, Mp1 electric current all flows into ground through Mn1, and outp current potentials keep constant.
However, existing such scheme can cause the common mode range of its output voltage not due to using difference output reason
Controlled, circuit can fail when common-mode voltage is biased to supply voltage or ground voltage, it is impossible to normal work；In addition, current mirror is using single
Tubular construction, output impedance is relatively low, due to the difference of common-mode point the discharge and recharge of metal-oxide-semiconductor can be caused unequal；Except matching factor, electric charge
The load capacitance electric leakage of pump can also cause common mode electrical level to drift about.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of electric charge for fpga chip
Pump.The technical problem to be solved in the present invention is achieved through the following technical solutions：
A kind of charge pump for fpga chip, including Differential input circuit, Commom-mode feedback circuit, electric current mismatch school
Positive circuit, output differential mode clear circuit, differential output circuit；
The Differential input circuit connects the differential output circuit, for producing the final output voltage of charge pump；
The differential output circuit includes two output ends, connects Commom-mode feedback circuit respectively and electric current mismatches correction
Circuit, carried for providing common mode detection level to the Commom-mode feedback circuit respectively, mismatching correcting circuit to the electric current
Power supply stream mismatches detection level；
The Commom-mode feedback circuit connects Differential input circuit, defeated to difference for the common mode to be detected into level compensation
Enter the output end of circuit, make the common-mode signal of the output end of Differential input circuit stable；
The electric current mismatches correcting circuit and connects the differential output circuit, for according to the difference output detected
Electric current mismatches detection level two difference outputs of corresponding compensation, so that two difference outputs can ensure respective charging respectively
Match with discharge current；
The output differential mode clear circuit connects the Commom-mode feedback circuit, for emptying institute when circuit start works
State the difference mode signal of Commom-mode feedback circuit differential pair tube output.
Further, in addition to biasing circuit, the biasing circuit connects the electric current and mismatches correcting circuit, for
The electric current mismatches correcting circuit and provides bias current, and the matching for being charged and discharged electric current is exported with enhancing.
Further, in addition to enabled switch, the enabled switch connect the biasing circuit and the Commom-mode feedback
Circuit, for controlling Commom-mode feedback direct current detection voltage back being turned on or off from voltage source to earth terminal of the charge pump,
To reduce the quiescent dissipation when phaselocked loop is not enabled.
Further, the Differential input circuit includes：The first transistor, second transistor, third transistor, the 4th crystalline substance
Body pipe, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, first port, second port, the 3rd port,
4th port；Wherein,
The first crystal tube grid connection first port, the first transistor source electrode connection second transistor source electrode,
Third transistor drains, and the first transistor drain electrode connects the differential output circuit；
The second transistor grid connects second port, and the second transistor drain electrode connects the difference output electricity
Road；
The third transistor grid connects the biasing circuit, the 4th transistor gate, the third transistor source electrode
Connect the 5th transistor drain；
4th transistor gate connects the biasing circuit, and the 4th transistor source connects the leakage of the 6th transistor
Pole, the 4th transistor drain connect the 7th transistor source, the 8th transistor source；
5th transistor gate connects the biasing circuit, the 6th transistor gate, the 5th transistor
Source electrode connects earth terminal；
6th transistor gate connects the biasing circuit, and the 6th transistor source connects earth terminal；
7th transistor gate connects the 3rd port, and the 7th transistor drain connects the difference output electricity
Road；
8th transistor gate connects the 4th port, and the 8th transistor drain connects the difference output electricity
Road.
Further, the electric current mismatches correcting circuit and included：First operational amplifier, the second operational amplifier,
Nine transistors, the tenth transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor, the 14th transistor, the tenth
Five transistors, the 16th transistor, the 40th transistor, the 41st transistor, the 44th transistor, the 45th crystal
Pipe；Wherein,
The first operational amplifier in-phase input end connects the 40th transistor drain, the 9th transistor drain,
The first operational amplifier inverting input connects the differential output circuit, the first operational amplifier output terminal connection
Tenth transistor gate, the 40th transistor source connect the 44th transistor drain；9th transistor
Source electrode connects the tenth transistor drain, and the 9th transistor gate connects the 11st transistor gate, the biased electrical
Road；The tenth transistor source connection power end, the tenth transistor gate are also connected with the tenth two-transistor grid；It is described
11st transistor drain connects the differential output circuit, and the 11st transistor source connects the tenth two-transistor
Drain electrode, the 11st transistor gate connect the 13rd transistor gate；The tenth two-transistor source electrode connects the electricity
Source；13rd transistor gate connects the 14th transistor gate, the 13rd transistor source connection the
15 transistors, the 13rd transistor drain connect the second operational amplifier in-phase input end, the 41st crystal
Pipe drains, and the 41st transistor source connects the 45th transistor drain；Second operational amplifier is anti-
Phase input connects the differential output circuit；The 14th transistor gate connection biasing circuit, the described 14th
Transistor source connects the 16th transistor drain, and the 14th transistor drain connects the differential output circuit；It is described
15th transistor gate connection, second operational amplifier output terminal, the 16th transistor gate, the described 15th
Transistor source, the 16th transistor source are all connected with power end.
Further, the biasing circuit includes：25th transistor, the 34th transistor, the 35th crystal
Pipe, the 36th transistor, the 38th transistor, the 39th transistor, the 40th two-transistor, the 43rd crystal
Pipe, the 46th transistor；Wherein,
25th transistor gate connects the 4th transistor, the 25th transistor source connection the
34 transistor drains, the 25th transistor drain connection fifth port, the output differential mode clear circuit；
34th transistor gate connects the 6th transistor gate；
35th transistor source connects the 36th transistor drain, the 35th transistor leakage
Pole connects the 6th port, the output differential mode clear circuit；
38th transistor gate connect the 38th transistor drain, the 39th transistor gate,
40th transistor gate, the 41st transistor gate, the 38th transistor source connection the described 42nd are brilliant
Body pipe source electrode, the 43rd transistor source, the 44th transistor source, the 45th transistor source, ground voltage end；The
38 transistor drains connect the first current source output；
39th transistor source connects the 43rd transistor drain, the 39th transistor leakage
Pole connects the 46th transistor drain；
The 40th two-transistor grid connects the 43rd transistor gate and connects the 44th crystal
Tube grid, the 45th transistor gate, the 40th two-transistor drain electrode second current source output of connection；
46th transistor gate connects the 46th transistor drain, the 9th transistor gate,
46th transistor source connects first current source output, the second current source output, the power end.
Further, the differential output circuit includes：33rd transistor, the 37th transistor；
33rd transistor gate connects the 37th transistor gate, and the 33rd transistor drain connects
Connect the fifth port, the 11st transistor drain；
37th transistor drain connects the 14th transistor drain, the 6th port.
Further, the Commom-mode feedback circuit includes：17th transistor, the 18th transistor, the 19th crystal
Pipe, the 20th transistor, the 21st transistor, the 20th two-transistor, the 23rd transistor, the 24th transistor,
27th transistor, the 28th transistor, the 29th transistor, the 30th transistor, the 30th two-transistor, first
Resistance, second resistance；Wherein,
17th transistor gate connects fifth port, and the 17th transistor source connects the 18th transistor
Source electrode, the 19th transistor drain, the 17th transistor drain connect the 20th transistor drain, the 21st transistor
Drain electrode, the 21st transistor gate；
18th transistor gate connects the 20th two-transistor, first resistor one end, second resistance one end, first
Capacitance cathode, power supply partial pressure end, the second resistance other end connect the power end, the 18th transistor drain connection
The 20th two-transistor drain electrode, the 23rd transistor drain, the 24th transistor gate；
19th transistor gate connects the 25th transistor gate, the 26th transistor gate, and described the
19 transistor sources connect the 27th transistor drain；
20th transistor gate connects the 6th port, the 20th transistor source connection the described 22nd
Transistor source, the 26th transistor drain；
21st transistor source connects the 29th transistor source, the 30th transistor source, described the
24 transistor sources, the power end；
The 20th two-transistor source electrode connects the 26th transistor drain；
23rd transistor gate connects the 14th transistor gate, the 33rd transistor gate, and described the
23 transistor sources connect the 24th transistor drain；
24th transistor gate connects the 29th transistor gate；
26th transistor gate connects the 35th transistor gate, and the 26th transistor source connects
Connect the 30th two-transistor drain electrode；
27th transistor gate connects the 30th two-transistor grid, the 34th transistor gate
Pole, the 27th transistor source connect the 34th transistor source, the 30th two-transistor source electrode, the
36 transistor sources, the 28th transistor source, the first electric capacity negative pole, the ground voltage end；
28th transistor gate connects the 28th transistor drain, the first resistor other end；
29th transistor gate connects the 30th transistor gate, the 29th transistor drain
Connect the 33rd transistor source, the 8th transistor drain, second transistor drain electrode；
30th transistor drain connects the 36th transistor source, the first transistor drain electrode, described the
Seven transistor drains；
30th two-transistor grid connects the 36th transistor gate.
Further, the enabled switch includes the first enabled switch, the second enabled switch, the 3rd enabled switch；
Described first enabled switch is connected between the power end and the second resistance, for controlling the power end
With being switched on or switched off for the second resistance path；
Described second enabled switch is connected between the 40th two-transistor grid and the ground voltage end；
Described 3rd enabled switch is connected between the 38th transistor gate and the ground voltage end.
Further, the described first enabled switch, the second enabled switch, the 3rd enabled switch are transistor
Switch.
Compared with prior art, beneficial effects of the present invention：
The charge pump for fpga chip of the present invention is utilized by the Commom-mode feedback circuit of design and monitors difference output
The common-mode voltage of circuit, dynamic adjust electric current, ensure that charge pump final output common-mode voltage is intended to the voltage of setting all the time, protect
Demonstrate,prove circuit normal work；In addition the present invention is benefited from, the electrical leakage problems of the large scale electric capacity of rear class filtering device are also addressed；Together
When due to mismatching the introducing of current correction circuit, output voltage in arbitrary value, output end charging current and discharge current
Matching is obtained for lifting, ensures the single step voltage step that charge pump is linear in a wide range of output voltage, further lifting
The linearity of charge pump.
Brief description of the drawings
Fig. 1 is charge pump circuit schematic diagram of the prior art.
Fig. 2 is the charge pump circuit figure in one concrete application of prior art.
Fig. 3 is the electric charge pump module block diagram for fpga chip of the present invention.
Fig. 4 is the electric charge pump module block diagram for fpga chip in another embodiment of the present invention.
Fig. 5 is the charge pump circuit figure for fpga chip in an embodiment of the invention.
Fig. 6 is the advanced working condition schematic diagram of charge pump in an embodiment of the invention.
Fig. 7 is charge pump hysteresis working condition schematic diagram in an embodiment of the invention.
Fig. 8 is charge pump locking working condition schematic diagram in an embodiment of the invention.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment 1：
Fig. 3 is the electric charge pump module block diagram for fpga chip of the embodiment of the present invention, including Differential input circuit 1, altogether
Mould negative-feedback circuit 2, electric current mismatch correcting circuit 3, output differential mode clear circuit 4, differential output circuit 5；
The Differential input circuit 1 connects the differential output circuit 5, for producing the final output voltage of charge pump；
The differential output circuit 5 includes two output ends, connects Commom-mode feedback circuit 2 respectively and electric current mismatches school
Positive circuit 3, for providing common mode detection level to the Commom-mode feedback circuit 2 respectively, correction electricity being mismatched to the electric current
Road 3 provides electric current and mismatches detection level；
The Commom-mode feedback circuit 2 connects Differential input circuit 1, for the common mode to be detected into level compensation to difference
The output end of input circuit 1, make the common-mode signal of the output end of Differential input circuit 1 stable；
The electric current mismatches correcting circuit 3 and connects the differential output circuit 5, for according to the difference output detected
Electric current mismatch detection level two difference outputs of corresponding compensation so that two difference outputs can ensure respective fill respectively
Electricity matches with discharge current；
The output differential mode clear circuit 4 connects the Commom-mode feedback circuit 2, for being emptied when circuit start works
The difference mode signal of the differential pair tube of Commom-mode feedback circuit 2 output.
The charge pump of the present invention weakens influence of the output voltage common mode variations to currents match, enhances two output branch
Road respective charging current and matching of discharge current under different output voltages, lift the charge pump linearity.
In a detailed embodiment, the electricity is connected referring to Fig. 4, in addition to biasing circuit 6, the biasing circuit 6
Stream mismatch correcting circuit 3, for the electric current mismatch correcting circuit 3 provide bias current, with enhancing output charging and
The matching of discharge current.,
In a detailed embodiment, in addition to enabled switch 7, the enabled switch 7 connect the He of biasing circuit 6
The Commom-mode feedback circuit 2, for controlling the Commom-mode feedback direct current detection voltage back of the charge pump from voltage source to ground connection
End is turned on or off, to reduce the quiescent dissipation when phaselocked loop is not enabled.
This implementation provides an instantiation, preferably to describe the design of the present invention, referring to the circuit shown in Fig. 5
Figure.The Differential input circuit 1 includes：The first transistor xi7, second transistor xi6, third transistor xi5, the 4th transistor
Xi2, the 5th transistor xi4, the 6th transistor xi3, the 7th transistor xi0, the 8th transistor xi1, first port dnb, second
Port dn, the 3rd port up, the 4th port upb；Wherein,
The first transistor xi7 grids connection first port dnb, the first transistor xi7 source electrodes connection second are brilliant
Body pipe xi6 source electrodes, third transistor xi5 drain electrodes, the first transistor xi7 drain electrodes connect the differential output circuit 5；
The second transistor xi6 grids connection second port dn, the second transistor xi6 drain electrodes connect the difference
Output circuit 5；
The third transistor xi5 grids connect the biasing circuit 6, the 4th transistor xi2 grids, the 3rd crystal
Pipe xi5 source electrodes connect the 5th transistor xi4 drain electrodes；
The 4th transistor xi2 grids connect the biasing circuit 6, the 4th transistor xi2 source electrodes connection the 6th
Transistor xi3 drains, the 7th transistor xi0 source electrodes of the 4th transistor xi2 drain electrodes connection, the 8th transistor xi1 source electrodes；
The 5th transistor xi4 grids connect the biasing circuit 6, the 6th transistor xi3 grids, and the described 5th
Transistor xi4 source electrodes connect earth terminal；
The 6th transistor xi3 grids connect the biasing circuit 6, the 6th transistor xi3 source electrodes connection ground connection
End；
The 7th transistor xi0 grids connect the 3rd port up, and the 7th transistor xi0 drain electrodes connect the difference
Output circuit 5；
The 8th transistor xi1 grids connect the 4th port upb, and the 8th transistor xi1 drain electrodes connect the difference
Divide output circuit 5.
The electric current, which mismatches correcting circuit 3, to be included：First operational amplifier I11, the second operational amplifier I12, the 9th
Transistor M3, the tenth transistor M2, the 11st transistor M5, the tenth two-transistor M6, the 13rd transistor M11, the 14th crystalline substance
Body pipe M10, the 15th transistor M13, the 16th transistor M12, the 40th transistor M1, the 41st transistor M9, the 4th
14 transistor M0, the 45th transistor M8；Wherein,
The first operational amplifier I11 in-phase input ends connect the 40th transistor M1 drain electrodes, the 9th transistor
M3 drains, and the first operational amplifier I11 inverting inputs connect the differential output circuit 5, first operation amplifier
Device I11 output ends connect the tenth transistor M2 grids, and the 40th transistor M1 source electrodes connect the 44th transistor
M0 drains；The 9th transistor M3 source electrodes connect the tenth transistor M2 drain electrodes, the 9th transistor M3 grids connection
11st transistor M5 grids, the biasing circuit 6；The tenth transistor M2 source electrodes connection power end, the tenth crystal
Pipe M2 grids are also connected with the tenth two-transistor M6 grids；The 11st transistor M5 drain electrodes connect the differential output circuit 5,
The 11st transistor M5 source electrodes connect the tenth two-transistor M6 drain electrodes, the 11st transistor M5 grids connection the
13 transistor M11 grids；The tenth two-transistor M6 source electrodes connect the power end；The 13rd transistor M11 grid
Pole connects the 14th transistor M10 grids, and the 13rd transistor M11 source electrodes connect the 15th transistor M13, described
The second operational amplifier I12 in-phase input ends of 13rd transistor M11 drain electrode connections, the 41st transistor M9 drain electrodes,
The 41st transistor M9 source electrodes connect the 45th transistor M8 drain electrodes；The second operational amplifier I12 is anti-
Phase input connects the differential output circuit 5；The 14th transistor M10 grids connect the biasing circuit 6, and described the
14 transistor M10 source electrodes connect the 16th transistor M12 drain electrodes, and the 14th transistor M10 drain electrodes connect the difference
Output circuit 5；The 15th transistor M13 grids connect the second operational amplifier I12 output ends, the 16th crystalline substance
Body pipe M12 grids, the 15th transistor M13 source electrodes, the 16th transistor M12 source electrodes are all connected with power end.
The biasing circuit 6 includes：25th transistor xi8, the 34th transistor xi9, the 35th transistor
Xi11, the 36th transistor xi10, the 38th transistor xi56, the 39th transistor xi44, the 40th two-transistor
M4, the 43rd transistor xi45, the 46th transistor xi43；Wherein,
The 25th transistor xi8 grids connect the 4th transistor xi2, the 25th transistor xi8
Source electrode connects the 34th transistor xi9 drain electrodes, the 25th transistor xi8 drain electrode connection fifth port cpi_p, described
Export differential mode clear circuit 4；
34th transistor xi9 grids connect the 6th transistor xi3 grids；
The 35th transistor xi11 source electrodes connect the 36th transistor xi10 and drained, and the described 35th
The 6th port cpi_n of transistor xi11 drain electrode connections, the output differential mode clear circuit 4；
The 38th transistor xi56 grids connect the 38th transistor xi56 drain electrodes, the 39th crystal
Pipe xi44 grids, the 40th transistor M1 grids, the 41st transistor M9 grids, the 38th transistor xi56 source electrodes
Connect the 40th two-transistor M4 source electrodes, the 43rd transistor xi45 source electrodes, the 44th transistor M0 source electrodes, the 4th
15 transistor M8 source electrodes, ground voltage end；38th transistor xi56 drain electrode the first current source I6 output ends of connection；
The 39th transistor xi44 source electrodes connect the 43rd transistor xi45 and drained, and the described 39th
Transistor xi44 drain electrode connection the 46th transistor xi43 drain electrodes；
The 40th two-transistor M4 grids connect the 43rd transistor xi45 grids connection the described 40th
Four transistor M0 grids, the 45th transistor M8 grids, the 40th two-transistor M4 drain electrodes second electric current of connection
Source I5 output ends；
The 46th transistor xi43 grids connect the 46th transistor xi43 drain electrodes, the 9th crystal
Pipe M3 grids, it is defeated that the 46th transistor xi43 source electrodes connect the first current source I6 inputs, the second current source I5
Enter end, the power end.
The differential output circuit 5 includes：33rd transistor xi13, the 37th transistor xi12；
The 33rd transistor xi13 grids connect the 37th transistor xi12 grids, the 33rd crystal
Pipe xi13 drain electrodes connect the fifth port cpi_p, the 11st transistor M5 drain electrode；
The 37th transistor xi12 drain electrodes connect the 14th transistor M10 drain electrodes, the 6th port
cpi_n。
The Commom-mode feedback circuit 2 includes：17th transistor xi42, the 18th transistor xi41, the 19th crystal
Pipe xi38, the 20th transistor xi39, the 21st transistor xi47, the 20th two-transistor xi40, the 23rd transistor
Xi48, the 24th transistor xi49, the 27th transistor xi37, the 28th transistor xi112, the 29th transistor
Xi14, the 30th transistor xi15, the 30th two-transistor xi36, first resistor xi109, second resistance xi105；Wherein,
The 17th transistor xi42 grids connect fifth port cpi_p, and the 17th transistor xi42 source electrodes connect
Connect the 18th transistor xi41 source electrodes, the 19th transistor xi38 drain electrodes, the 17th transistor xi42 drain electrodes connection second
Ten transistor xi39 drain electrodes, the 21st transistor xi47 drain electrodes, the 21st transistor xi47 grids；
The 18th transistor xi41 grids connect the 20th two-transistor xi40, first resistor xi109 one end, second
Resistance xi105 one end, the first electric capacity xi96 positive poles, power supply partial pressure end vcom, described in the second resistance xi105 other ends connection
Power end, the 18th transistor xi41 drain electrodes connect the 20th two-transistor xi40 drain electrodes, the 23rd transistor
Xi48 drain electrodes, the 24th transistor xi49 grids；
The 19th transistor xi38 grids connect the 25th transistor xi8 grids, the 26th transistor xi35
Grid, the 19th transistor xi38 source electrodes connect the 27th transistor xi37 drain electrodes；
The 20th transistor xi39 grids connect the 6th port cpi_n, and the 20th transistor xi39 source electrodes connect
Connect the 20th two-transistor xi40 source electrodes, the 26th transistor xi35 drain electrodes；
The 21st transistor xi47 source electrodes connect the 29th transistor xi14 source electrodes, the 30th transistor xi15
Source electrode, the 24th transistor xi49 source electrodes, the power end；
The 20th two-transistor xi40 source electrodes connect the 26th transistor xi35 drain electrodes；
23rd transistor xi48 grids connect the 14th transistor M10 grids, the 33rd transistor xi13
Grid, the 23rd transistor xi48 source electrodes connect the 24th transistor xi49 drain electrodes；
The 24th transistor xi49 grids connect the 29th transistor xi14 grids；
The 26th transistor xi35 grids connect the 35th transistor xi11 grids, the 26th crystal
Pipe xi35 source electrodes connect the 30th two-transistor xi36 drain electrodes；
The 27th transistor xi37 grids connect the 30th two-transistor xi36 grids, the described 34th
Transistor xi9 grids, the 27th transistor xi37 source electrodes connect the 34th transistor xi9 source electrodes, described the
30 two-transistor xi36 source electrodes, the 36th transistor xi10 source electrodes, the 28th transistor xi112 source electrodes, described first
Electric capacity xi96 negative poles, the ground voltage end；
The 28th transistor xi112 grids connect the 28th transistor xi112 drain electrodes, first electricity
Hinder the xi109 other ends；
The 29th transistor xi14 grids connect the 30th transistor xi15 grids, and the described 29th is brilliant
Body pipe xi14 drain electrodes connect the 33rd transistor xi13 source electrodes, the 8th transistor xi1 drain electrodes, second crystal
Pipe xi6 drains；
The 36th transistor xi12 source electrodes of the 30th transistor xi15 drain electrodes connection, the first transistor xi7
Drain electrode, the 7th transistor xi0 drain electrodes；
30th two-transistor xi36 grids connect the 36th transistor xi10 grids.
In a detailed embodiment, the enabled switch 7 includes the first enabled switch xi29, the second enabled switch
M7, the 3rd enabled switch xi77；
Described first enabled switch xi29 is connected between the power end and the second resistance xi105, for controlling
The power end is switched on or switched off with the second resistance xi105 paths；
Described second enabled switch M7 is connected between the 40th two-transistor M4 grids and the ground voltage end；
Described 3rd enabled switch xi77 be connected to the 38th transistor xi56 grids and the ground voltage end it
Between.
Preferably, the described first enabled switch xi29, the second enabled switch M7, the 3rd enabled switch xi77 are equal
For transistor switch.
The operation principle of the present invention is illustrated below for above-mentioned physical circuit figure, charge pump is logical first before work
Cp_rst port controlling I8 transmission gate short circuit cpi_p and cpi_n ports are crossed, empty the difference mode signal of difference output, ensure electric charge
Pump initial error is zero.
As Figure 6-Figure 8, three kinds of working conditions of charge pump are corresponding in turn to：Up (advanced), dn (hysteresis), idle are (empty
It is spare time, locked).When advanced (Icp+Iup_adj)>Icn, cpi_p voltage rise；(Icp+Idn_adj)<(Idnb+Iup+
Icn), cpi_n voltages decline.During hysteresis (Icp+Iup_adj)<(Idn+Iupb+Icn), cpi_p voltages decline；(Icp+Idn_
adj)>Icn, cpi_n voltage rise.(Icp+Iup_adj)=(Iupb+Icn), cpi_p voltages are constant during locking；(Icp+
Idn_adj)=(Idnb+Icn), cpi_n voltages are constant.Icn is the xi9 and xi10 in schematic diagram in Fig. 6.Electricity in dotted line frame
Appearance is a part for the next stage module low pass filter of charge pump.
Specifically, vcom is the partial pressure of supply voltage, supply voltage is fixed, so vcom is a fixed voltage of setting
Value.Differential pair xi39~xi42 monitoring outputs cpi_p and cpi_n common-mode voltage.Vcom voltages and common-mode voltage are made comparisons,
When common-mode voltage is less than vcom, xi37 and xi36 electric current are most of to be increased by xi40 and xi41, the i.e. electric current of xi49.And
Xi14 and xi15 electric currents are directly proportional to xi49 electric currents, and the electric current for making to flow through output end cpi_p and cpi_n is more than xi9's and xi10
Pull-down current, then cpi_p and cpi_n common-mode voltages rising, stops adjustment when cpi_p and cpi_n common-mode voltage is equal.
This negative-feedback circuit can stablize output common mode voltage, make final output common-mode voltage and the vcom voltage phases of design alternative
Deng.When charge pump detects that PLL (phaselocked loop) two input clocks have difference on the frequency or phase difference, charge pump circuit output
Cpi_p and cpi_n voltage moves to supply voltage and ground voltage respectively, in order to ensure the input clock frequencies of PLL two or phase
When having mutation, the big signal response of circuit can have enough nargin, be unlikely to cpi_p, cpi_n and be flushed to supply voltage and ground voltage
Non-linear distortion is produced, the present invention selects the half that vcom voltages are supply voltage.When difference output is not in output common mode scope
Between when, the charging and discharging branch road of charge pump can cause circuit to mismatch because output impedance is limited, and the present invention, which passes through, adds electricity
Stream mismatches correcting circuit by detecting cpi_p and cpi_n voltages respectively, dynamic compensate one part of current enter cpi_p and
Cpi_n ends, ensure have preferably linearly in whole voltage range.The sleeve current mirror in circuit increases output end simultaneously
Output impedance, make output current weak related to output voltage, ensure the uniformity of electric current during different output voltages.Partial pressure branch road and
Current source branch is influenceed by xi29, M7, xi77, the pwdnbb control above three metal-oxide-semiconductors of circuit, closes charge pump circuit from electricity
Source eliminates the quiescent dissipation of charge pump circuit to the path on ground.
The charge pump for fpga chip of the present invention is utilized by the Commom-mode feedback circuit of design and monitors difference output
The common-mode voltage of circuit, dynamic adjust electric current, ensure that charge pump final output common-mode voltage is intended to the voltage of setting all the time, protect
Demonstrate,prove circuit normal work；In addition the present invention is benefited from, the electrical leakage problems of the large scale electric capacity of rear class filtering device are also addressed；Together
When due to mismatching the introducing of current correction circuit, output voltage in arbitrary value, output end charging current and discharge current
Matching is obtained for lifting, ensures the single step voltage step that charge pump is linear in a wide range of output voltage, further lifting
The linearity of charge pump.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of charge pump for fpga chip, it is characterised in that including Differential input circuit (1), Commom-mode feedback circuit
(2), electric current mismatches correcting circuit (3), output differential mode clear circuit (4), differential output circuit (5)；
The Differential input circuit (1) connects the differential output circuit (5), for producing the final output voltage of charge pump；
The differential output circuit (5) includes two output ends, connects Commom-mode feedback circuit (2) respectively and electric current mismatches school
Positive circuit (3), for providing common mode detection level to the Commom-mode feedback circuit (2) respectively, mismatching school to the electric current
Positive circuit (3) provides electric current and mismatches detection level；
Commom-mode feedback circuit (2) the connection Differential input circuit (1), for the common mode to be detected into level compensation to difference
The output end of input circuit (1), make the common-mode signal of the output end of Differential input circuit (1) stable；
The electric current mismatches correcting circuit (3) and connects the differential output circuit (5), for according to the difference output detected
Electric current mismatch detection level two difference outputs of corresponding compensation so that two difference outputs can ensure respective fill respectively
Electricity matches with discharge current；
The output differential mode clear circuit (4) connects the Commom-mode feedback circuit (2), for being emptied when circuit start works
The difference mode signal of Commom-mode feedback circuit (2) the differential pair tube output.
2. the charge pump according to claim 1 for fpga chip, it is characterised in that also including biasing circuit (6), institute
State biasing circuit (6) and connect the electric current mismatch correcting circuit (3), carried for mismatching correcting circuit (3) to the electric current
For bias current, the matching for being charged and discharged electric current is exported with enhancing.
3. the charge pump according to claim 2 for fpga chip, it is characterised in that also include enabled switch (7), institute
State enabled switch (7) and connect the biasing circuit (6) and the Commom-mode feedback circuit (2), for controlling the charge pump
Commom-mode feedback direct current detection voltage back being turned on or off from voltage source to earth terminal, it is quiet when phaselocked loop is not enabled to reduce
State power consumption.
4. the charge pump according to claim 3 for fpga chip, it is characterised in that the Differential input circuit (1)
Including：The first transistor (xi7), second transistor (xi6), third transistor (xi5), the 4th transistor (xi2), the 5th crystal
Manage (xi4), the 6th transistor (xi3), the 7th transistor (xi0), the 8th transistor (xi1), first port (dnb), the second end
Mouth (dn), the 3rd port (up), the 4th port (upb)；Wherein,
The first transistor (xi7) the grid connection first port (dnb), the first transistor (xi7) the source electrode connection second
Transistor (xi6) source electrode, third transistor (xi5) drain electrode, the first transistor (xi7) drain electrode connect the difference output electricity
Road (5)；
Second transistor (xi6) the grid connection second port (dn), second transistor (xi6) drain electrode connect the difference
Divide output circuit (5)；
Third transistor (xi5) grid connects the biasing circuit (6), the 4th transistor (xi2) grid, and the described 3rd is brilliant
Body pipe (xi5) source electrode connects the drain electrode of the 5th transistor (xi4)；
4th transistor (xi2) grid connects the biasing circuit (6), the 4th transistor (xi2) the source electrode connection the
Six transistors (xi3) drain, the 7th transistor (xi0) source electrode of the 4th transistor (xi2) the drain electrode connection, the 8th transistor
(xi1) source electrode；
5th transistor (xi4) grid connects the biasing circuit (6), the 6th transistor (xi3) grid, and described the
Five transistors (xi4) source electrode connects earth terminal；
6th transistor (xi3) grid connects the biasing circuit (6), and the 6th transistor (xi3) source electrode connects
Ground terminal；
7th transistor (xi0) grid connects the 3rd port (up), and the 7th transistor (xi0) drain electrode connects the difference
Divide output circuit (5)；
8th transistor (xi1) grid connects the 4th port (upb), and the 8th transistor (xi1) drains described in connection
Differential output circuit (5).
5. the charge pump according to claim 4 for fpga chip, it is characterised in that the electric current mismatches correction electricity
Road (3) includes：First operational amplifier (I11), the second operational amplifier (I12), the 9th transistor (M3), the tenth transistor
(M2), the 11st transistor (M5), the tenth two-transistor (M6), the 13rd transistor (M11), the 14th transistor (M10),
15 transistors (M13), the 16th transistor (M12), the 40th transistor (M1), the 41st transistor (M9), the 40th
Four transistors (M0), the 45th transistor (M8)；Wherein,
First operational amplifier (I11) in-phase input end connects the 40th transistor (M1) drain electrode, the 9th transistor
(M3) drain, the first operational amplifier (I11) inverting input connects the differential output circuit (5), first fortune
Calculate amplifier (I11) output end and connect the tenth transistor (M2) grid, the 40th transistor (M1) source electrode connection described the
44 transistors (M0) drain；9th transistor (M3) source electrode connects the tenth transistor (M2) drain electrode, and described the
Nine transistors (M3) grid connects the 11st transistor (M5) grid, the biasing circuit (6)；Tenth transistor (M2) source
Pole connection power end, the tenth transistor (M2) grid are also connected with the tenth two-transistor (M6) grid；11st crystal
Manage (M5) drain electrode and connect the differential output circuit (5), the 11st transistor (M5) source electrode connects the 12nd crystal
(M6) drain electrode is managed, the 11st transistor (M5) grid connects the 13rd transistor (M11) grid；Tenth two-transistor
(M6) source electrode connects the power end；13rd transistor (M11) grid connects the 14th transistor (M10) grid
Pole, the 13rd transistor (M11) source electrode connect the 15th transistor (M13), and the 13rd transistor (M11) drain electrode connects
Connect the second operational amplifier (I12) in-phase input end, the 41st transistor (M9) drain electrode, the 41st transistor
(M9) source electrode connects the 45th transistor (M8) drain electrode；Second operational amplifier (I12) the inverting input connection
The differential output circuit (5)；14th transistor (M10) grid connects the biasing circuit (6), and the described 14th is brilliant
Body pipe (M10) source electrode connects the drain electrode of the 16th transistor (M12), and the 14th transistor (M10) drain electrode connects the difference
Output circuit (5)；15th transistor (M13) grid connects the second operational amplifier (I12) output end, described the
16 transistors (M12) grid, the 15th transistor (M13) source electrode, the 16th transistor (M12) source electrode are all connected with
Power end.
6. the charge pump according to claim 5 for fpga chip, it is characterised in that the biasing circuit (6) includes：
25th transistor (xi8), the 34th transistor (xi9), the 35th transistor (xi11), the 36th transistor
(xi10), the 38th transistor (xi56), the 39th transistor (xi44), the 40th two-transistor (M4), the 43rd
Transistor (xi45), the 46th transistor (xi43)；Wherein,
25th transistor (xi8) grid connects the 4th transistor (xi2), the 25th transistor
(xi8) source electrode connects the drain electrode of the 34th transistor (xi9), the 25th transistor (xi8) the drain electrode connection fifth port
(cpi_p), the output differential mode clear circuit (4)；
34th transistor (xi9) grid connects the 6th transistor (xi3) grid；
35th transistor (xi11) source electrode connects the 36th transistor (xi10) and drained, and the described 35th
The 6th port (cpi_n) of transistor (xi11) drain electrode connection, the output differential mode clear circuit (4)；
38th transistor (xi56) grid connects the 38th transistor (xi56) drain electrode, the 39th crystal
Manage (xi44) grid, the 40th transistor (M1) grid, the 41st transistor (M9) grid, the 38th transistor
(xi56) source electrode connects the 40th two-transistor (M4) source electrode, the 43rd transistor (xi45) source electrode, the 44th crystalline substance
Body pipe (M0) source electrode, the 45th transistor (M8) source electrode, ground voltage end；38th transistor (xi56) drain electrode connection first
Current source (I6) output end；
39th transistor (xi44) source electrode connects the 43rd transistor (xi45) and drained, and the described 39th
Transistor (xi44) drain electrode connection the 46th transistor (xi43) drain electrode；
40th two-transistor (M4) grid connects the 43rd transistor (xi45) the grid connection the described 40th
Four transistors (M0) grid, the 45th transistor (M8) grid, the 40th two-transistor (M4) drain electrode connection the
Two current sources (I5) output end；
46th transistor (xi43) grid connects the 46th transistor (xi43) drain electrode, the 9th crystal
(M3) grid is managed, the 46th transistor (xi43) source electrode connects the first current source (I6) input, the second electric current
Source (I5) input, the power end.
7. the charge pump according to claim 6 for fpga chip, it is characterised in that the differential output circuit (5)
Including：33rd transistor (xi13), the 37th transistor (xi12)；
33rd transistor (xi13) grid connects the 37th transistor (xi12) grid, the 33rd crystal
Manage (xi13) drain electrode and connect the fifth port (cpi_p), the 11st transistor (M5) drain electrode；
37th transistor (xi12) drain electrode connects the 14th transistor (M10) drain electrode, the 6th port
(cpi_n)。
8. the charge pump according to claim 7 for fpga chip, it is characterised in that the Commom-mode feedback circuit
(2) include：17th transistor (xi42), the 18th transistor (xi41), the 19th transistor (xi38), the 20th transistor
(xi39), the 21st transistor (xi47), the 20th two-transistor (xi40), the 23rd transistor (xi48), the 20th
Four transistors (xi49), the 27th transistor (xi37), the 28th transistor (xi112), the 29th transistor
(xi14), the 30th transistor (xi15), the 30th two-transistor (xi36), first resistor (xi109), second resistance
(xi105), wherein,
17th transistor (xi42) the grid connection fifth port (cpi_p), the 17th transistor (xi42) source electrode
Connect the 18th transistor (xi41) source electrode, the drain electrode of the 19th transistor (xi38), the 17th transistor (xi42) drain electrode
Connect the drain electrode of the 20th transistor (xi39), the drain electrode of the 21st transistor (xi47), the 21st transistor (xi47) grid；
18th transistor (xi41) grid connects the 20th two-transistor (xi40), first resistor (xi109) one end, the
Two resistance (xi105) one end, the first electric capacity (xi96) positive pole, power supply partial pressure end (vcom), the second resistance (xi105) are another
End connects the power end, the 18th transistor (xi41) drain electrode connects the 20th two-transistor (xi40) drain electrode,
The drain electrode of 23rd transistor (xi48), the 24th transistor (xi49) grid；
19th transistor (xi38) grid connects the 25th transistor (xi8) grid, the 26th transistor
(xi35) grid, the 19th transistor (xi38) source electrode connect the drain electrode of the 27th transistor (xi37)；
20th transistor (xi39) grid connects the 6th port (cpi_n), the 20th transistor (xi39) source electrode
Connect the 20th two-transistor (xi40) source electrode, the 26th transistor (xi35) drain electrode；
21st transistor (xi47) source electrode connects the 29th transistor (xi14) source electrode, the 30th transistor
(xi15) source electrode, the 24th transistor (xi49) source electrode, the power end；
20th two-transistor (xi40) source electrode connects the drain electrode of the 26th transistor (xi35)；
23rd transistor (xi48) grid connects the 14th transistor (M10) grid, the 33rd transistor
(xi13) grid, the 23rd transistor (xi48) source electrode connect the 24th transistor (xi49) drain electrode；
24th transistor (xi49) grid connects the 29th transistor (xi14) grid；
26th transistor (xi35) grid connects the 35th transistor (xi11) grid, the 26th crystal
Manage (xi35) source electrode and connect the 30th two-transistor (xi36) drain electrode；
27th transistor (xi37) grid connects the 30th two-transistor (xi36) grid, the described 34th
Transistor (xi9) grid, the 27th transistor (xi37) source electrode connect the 34th transistor (xi9) source electrode,
30th two-transistor (xi36) source electrode, the 36th transistor (xi10) source electrode, the 28th transistor (xi112) source
Pole, first electric capacity (xi96) negative pole, the ground voltage end；
28th transistor (xi112) grid connects the 28th transistor (xi112) drain electrode, first electricity
Hinder (xi109) other end；
29th transistor (xi14) grid connects the 30th transistor (xi15) grid, and the described 29th is brilliant
Body pipe (xi14) drain electrode connects the 33rd transistor (xi13) source electrode, the 8th transistor (xi1) drain electrode, described the
Two-transistor (xi6) drains；
The 36th transistor (xi12) source electrode of 30th transistor (xi15) the drain electrode connection, the first transistor
(xi7) drain electrode, the 7th transistor (xi0) drain electrode；
30th two-transistor (xi36) grid connects the 36th transistor (xi10) grid.
9. the charge pump according to claim 8 for fpga chip, it is characterised in that the enabled switch (7) includes
First enabled switch (xi29), the second enabled switch (M7), the 3rd enabled switch (xi77)；
Described first enabled switch (xi29) is connected between the power end and the second resistance (xi105), for controlling
The power end is switched on or switched off with the second resistance (xi105) path；
Described second enabled switch (M7) is connected between the 40th two-transistor (M4) grid and the ground voltage end；
Described 3rd enabled switch (xi77) be connected to the 38th transistor (xi56) grid and the ground voltage end it
Between.
10. the charge pump according to claim 9 for fpga chip, it is characterised in that the described first enabled switch
(xi29), the described second enabled switch (M7), the 3rd enabled switch (xi77) are transistor switch.
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| CN110491333A (en) * | 2019-10-15 | 2019-11-22 | 上海视欧光电科技有限公司 | A kind of interpolation operational amplifier circuit and display panel |
| CN111064358A (en) * | 2019-11-25 | 2020-04-24 | 北京时代民芯科技有限公司 | Charge pump circuit with self-calibration function and programmable current |
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| CN107749709B (en) | 2023-07-07 |
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