CN2519284Y - Mutual complementing differential peak value detecting circuit - Google Patents
Mutual complementing differential peak value detecting circuit Download PDFInfo
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- CN2519284Y CN2519284Y CN 01267474 CN01267474U CN2519284Y CN 2519284 Y CN2519284 Y CN 2519284Y CN 01267474 CN01267474 CN 01267474 CN 01267474 U CN01267474 U CN 01267474U CN 2519284 Y CN2519284 Y CN 2519284Y
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Abstract
A complementary detection circuit of difference peak values consists of at least a pair of complementary comparators, a pair of electrical level replacing followers, a pair of metal oxide semiconductor store capacitors, four MOS switches, a pair of discharge electric current sources, a pair of offset electric current sources and more than one divider resistors, wherein, When the input signal voltage VIN is more than or equal to the current voltage of the upper peak value VP, the charging switch is turned on, the MOS storage capacitor being charged, the voltage of an upper polar plate rising, which leads the value of VP increased until VP is equal to the VIN, completing the detection of the peak value; When the input signal voltage VIN of the upper peak value VIN is less than the current voltage of the upper peak value VP, charging switch is closed, the MOS store capacitor being slowly discharged, the voltage of the upper polar plate being reduced, which reduces the VP until VP is equal to VIN, thus completing the detection of the upper peak value; the same principle can be applied in the lower peak value. The circuit of the utility model not only can reduce the circuit alignments and the number of components, the area of integrated chips and the design complexity and power consumption of the circuits and at the same time can improve the stability and reliability of the complete circuit.
Description
Technical field
The utility model relates to the peak detection circuit technology, refers to that especially a kind of chip area dwindles and stability-enhanced complementary type difference peak detection circuit greatly.
Background of invention
Peak detection circuit is to be used for transmission interface circuit to carry out the important composition module that data are recovered, and its major function is to detect through the signal peak after balanced, so that produce the threshold voltage that data are recovered.Existing peak detection circuit mainly is made up of comparer, memory capacitance, switch and output follower circuit, and Fig. 1 is a kind of common peak detection circuit structure.
As shown in Figure 1, this circuit comprises at least with lower module: comparator C omp1, Comp2, output follower f1, f2, charging current source Ich1, Ich2, discharge current source Idch1, Idch2, memory capacitance C1, C2, switch S 1～S4 and divider resistance R1～R4; Wherein, VIN is an input signal, and COM is the common-mode signal of introducing, and VP, VN are respectively detected upper and lower peak value output.The concrete principle of work of this circuit is such: at first, input signal VIN compares with the output VP of f1, if VIN is big, and then switch S 1 work, charging current source Ich1 gives capacitor C 1 charging, the output voltage of f1 is risen, up to equating with VIN; If VIN is little, then switch S 3 work, discharge current source Idch1 gives capacitor C 1 discharge, the output voltage of f1 is descended, up to equating with VIN.Like this, the output of f1 promptly can equal the peak value of input signal, finishes the process that peak value detects.
Above described be the testing process of positive peak, the principle complete class of negative peak testing process with, just adopt comparator C omp2, output follower f2, charging current source Ich2, discharge current source Idch2, memory capacitance C2, switch S 2, S4 and divider resistance R1～R4 realize.Resistance R 1～R4 is used for finishing the dividing potential drop to crest voltage, produces to be used for the judgement voltage that data are recovered, and when R1=R2=R3=R4, judgement voltage is half of peak value.
This peak detection circuit is a kind of comparatively ripe circuit form, but still there is certain defective in it on circuit is realized, mainly show the following aspects:
1) the composition more complicated of circuit causes the area of integrated chip to increase;
2) need to introduce common mode voltage COM, cause unnecessary cabling;
3) need four switches and four road current sources, will inevitably introduce more biasing circuit;
4) since peak-to-peak value hour, the pressure reduction at electric capacity (C1, C2) two ends is little, thereby can not use the bigger metal-oxide semiconductor (MOS) of square capacitance (MOS) electric capacity;
5), the components and parts number in the circuit is increased, and there is the problem of stability in follower because comparer and follower are separate.
Summary of the invention
In view of this, fundamental purpose of the present utility model is to provide a kind of complementary type difference peak detection circuit, make it not only can reduce circuit trace and components and parts number, dwindle the integrated chip area, reduce complex circuit designs degree and power consumption, can improve the stability and the reliability of entire circuit simultaneously.
Since in peak detection circuit, detected peak value need be remained on certain amplitude, so the value of memory capacitance is all bigger, usually will be more than 40 pico farads.The square capacitance of currently used double-layered polycrystal electric capacity (poly-poly) generally has only 0.6ff/ μ m
2, and the square capacitance of metal-oxide semiconductor (MOS) (MOS) pipe is generally 2.5ff/ μ m
2, obviously, adopt mos capacitance can make chip area narrow down to original 1/4～1/3.Wherein, ff represents 10
-15Farad.Again because the two ends of mos capacitance need bigger pressure reduction, just can make capacitance stable, so an end of electric capacity does not meet common mode voltage COM in new circuit design, and direct ground connection, make memory capacitance in the sampled input signal Alternating Component, the common mode of also having sampled composition, so, just there is enough pressure reduction at the electric capacity two ends, make capacitance stable, saved common mode voltage signal simultaneously.
In order to follow the tracks of and keep the peak value of input signal, charging current Ich1, Ich2 are more a lot of greatly than discharge current Idch1, Idch2, generally more than 20 times, so, can save discharge current switch of the prior art, make the discharge current normal open, and not influence the detection of peak value.
Originally the duration of charging of electric capacity is to be controlled by charging current source Ich1, Ich2, in order further to dwindle chip area and to make control more flexible, can in new circuit design, the form with the RC time constant replace charging current source, the size that changes the MOS switch can change time constant, and this method is compared with easier, flexible with the current source charging.
According to above-mentioned analysis, the concrete technical scheme of the utility model is achieved in that
A kind of complementary type difference peak detection circuit comprises at least: a pair of complementary comparer, a pair of level shift follower, pair of metal oxide semiconductor (MOS) memory capacitance, four MOS switches, a pair of discharge current source, a pair of bias current sources and above divider resistances;
Wherein, the output of the first complementary comparer connects the source electrode of a MOS switch, and the grid of this MOS switch links to each other with power supply, and its drain electrode connects the top crown of a MOS memory capacitance; The input end of first bias current sources links to each other with power supply, its output connects the grid of the first level shift follower, the grounded drain of this follower, source electrode connects the top crown of a MOS memory capacitance, the output of first bias current sources connects first, second divider resistance simultaneously, this two resistance series connection; The one MOS memory capacitance bottom crown ground connection, the first discharge current source is in parallel with a MOS memory capacitance; The source electrode of the 3rd MOS switch connects first signal end, its grounded-grid, and drain electrode connects the top crown of a MOS memory capacitance;
The output of the second complementary comparer connects the source electrode of the 2nd MOS switch, the grounded-grid of this MOS switch, and its drain electrode connects the top crown of the 2nd MOS memory capacitance, the bottom crown ground connection of this MOS memory capacitance; The source electrode of the second level shift follower connects the top crown of the 2nd MOS memory capacitance, its drain electrode connects power supply, grid is connected to the input end of second bias current sources, the output ground connection of this bias current sources, the input end of second bias current sources connects the 3rd, the 4th divider resistance simultaneously, this two resistance series connection; The positive and negative two ends in the second discharge current source link to each other with the top crown of power supply with the 2nd MOS memory capacitance respectively; The source electrode of the 4th MOS switch connects first signal end, and its grid connects power supply, and drain electrode connects the top crown of the 2nd MOS memory capacitance;
The second, an end of the 4th divider resistance links to each other, and the negative input end of first, second complementary comparer links to each other, and connects an input signal simultaneously, and the positive input terminal of first, second complementary comparer connects the grid of first, second level shift follower respectively.
When applied signal voltage during more than or equal to current upward peak voltage, a MOS switch conduction, a MOS memory capacitance is recharged, and top crown voltage raises, and upward peak voltage raises, up to equaling applied signal voltage; When applied signal voltage during less than current upward peak voltage, a MOS switch closure, a MOS memory capacitance is slowly discharged, and top crown voltage reduces, and upward peak voltage reduces, until equaling applied signal voltage.
Described first comparer and second comparer are a pair of complementary differential pair tube.Described first comparer is the upward peak comparer, and second comparer is following peak comparator.The input difference of this first comparer is a pair of NMOS pipe to pipe, and the input difference of second comparer is a pair of PMOS pipe to pipe.Described comparer is the one-level differential amplifier, or two-stage amplifier, or common source and common grid amplifier.
Described MOS switch is a NMOS pipe switch, or switching pmos, or the CMOS complementary switch.Described follower is the follower that one-level or two-stage are followed stack.Described current source is the mirror-image constant flow source that draws electric current, or is the cascode constant current source that draws electric current, or is the mirror-image constant flow source of irritating electric current, or for irritating the cascode constant current source of electric current.
Resistance and the MOS memory capacitance parameter of the charge or discharge time of described MOS memory capacitance by the MOS switch drain-source two ends that link to each other with this electric capacity decides.The charging modes of this MOS memory capacitance can be controlled by constant current source.Described first signal and secondary signal are a pair of inversion signal.
The source gate voltage of described first follower is near 1 volt.The gate source voltage of described second follower is near 1 volt.
The peak-to-peak value voltage swing of described input signal is relevant with the attenuation degree of signal in transmission course, and it is big more to decay, and the peak-to-peak value of input signal is more little.The peak-to-peak value voltage V of described input signal
PpBetween 200 millivolts to 1.5 volts.
Described second divider resistance link to each other with the 4th divider resistance the end voltage be the common mode voltage of circuit.This common mode voltage is half of upward peak voltage and following crest voltage sum.The magnitude of voltage of this common mode voltage is between 1.5 volts to 2.5 volts.
By such scheme as can be seen, key of the present utility model is: need not be introduced separately into common mode voltage, but utilize the common mode voltage of exporting in the crest voltage up and down to become to assign to increase the voltage difference at electric capacity two ends, thereby make this circuit can adopt big but the mos capacitance that area dwindles greatly of two ends pressure reduction.
Therefore, complementary type difference peak detection circuit provided by the utility model has following characteristics and advantage:
1) owing to do not need to introduce the input of common mode voltage, simplified the cabling design of circuit; In addition, the mos capacitance that the utility model adopted is littler by 3/4 than the capacity area that adopts now, and has good reliability, therefore, circuit of the present utility model is when guaranteeing even improving reliability, reduce the design effort amount of circuit layout, reduced the usable floor area of integrated circuit (IC) chip.
2) the utility model adopts different charging modes to memory capacitance, has saved the biasing circuit in the constant-current source circuit, replace constant current source with the RC time constant and decide the duration of charging, and the size of the switching tube that adopts can be very little, and then reduce chip area.
3) in order to adopt compensation technique to eliminate to feed back in the follower instability that is caused, the utility model uses the level shift follower, i.e. source follower, and the labile factor of having avoided negative feedback to cause has guaranteed the reliability of entire circuit.
4) the utility model is on circuit design, saved discharge switch, and comparer and follower united two into one, therefore, reduce the use of a lot of electric components, thereby further dwindled chip area, simplified the complexity of circuit design, reduce power consumption, improved the reliability and stability of integrated circuit.
Description of drawings
Fig. 1 is the common peak detection circuit principle schematic of prior art kind;
Fig. 2 is a circuit theory synoptic diagram of the present utility model;
Fig. 3 is the emulation synoptic diagram of testing result behind employing the utility model circuit;
Fig. 4 is the circuit theory synoptic diagram of comparer one embodiment in the utility model;
Fig. 5 is the circuit theory synoptic diagram of another embodiment of comparer in the utility model;
Fig. 6 is the circuit theory synoptic diagram of the another embodiment of comparer in the utility model;
Fig. 7 is the circuit theory synoptic diagram of MOS switch one embodiment in the utility model;
Fig. 8 is the circuit theory synoptic diagram of follower one embodiment in the utility model;
Fig. 9 is the circuit theory synoptic diagram of current source first embodiment in the utility model;
Figure 10 is the circuit theory synoptic diagram of current source second embodiment in the utility model;
Figure 11 is the circuit theory synoptic diagram of current source the 3rd embodiment in the utility model;
Figure 12 is the circuit theory synoptic diagram of current source the 4th embodiment in the utility model.
Embodiment
Below in conjunction with drawings and the specific embodiments the utility model is further described in more detail.
As shown in Figure 2, peak detection circuit of the present utility model comprises at least with lower module: complementary comparator C omp21, Comp22, MOS memory capacitance C21, C22, MOS switch S 21, S22, S23, S24, discharge current source Idch21, Idch22, level shift follower f21, f22, bias current sources Ibias21, Ibias22, divider resistance R21～R24.Among the figure, VIN is an input signal, and VP, VN are respectively the upper and lower peak signals that detects, SET, SETB are a pair of anti-phase each other signal, in initial phase gauge tap S23, S24 conducting, initial voltage is set for capacitor C 21, C22, switch S 23, S24 end during operate as normal.
Wherein, complementary comparator C omp21, memory capacitance C21, MOS switch S 21 and S23, discharge current source Idch21, level shift follower f21 and bias current sources Ibias21 are used to detect upward peak.The output of complementary comparator C omp21 connects the source electrode of MOS switch S 21, and the grid of MOS switch S 21 links to each other with power supply Vdd, and the drain electrode of MOS switch S 21 connects the top crown of memory capacitance C21; The input end of bias current sources Ibias21 links to each other with power supply Vdd, its output terminal links to each other with the grid of level shift follower f21, the grounded drain of level shift follower f21, the source electrode of level shift follower f21 connects the top crown of memory capacitance C21, the output of bias current sources Ibias21 connects divider resistance R21, R22 simultaneously, and R21 connects with R22; The bottom crown ground connection of memory capacitance C21, the positive and negative two ends of discharge current source Idch21 link to each other with the upper and lower pole plate of memory capacitance C21 respectively; The source electrode of MOS switch S 23 connects signal SET, the grounded-grid of MOS switch S 23, and the drain electrode of MOS switch S 23 connects the top crown of memory capacitance C21.
Equally, complementary comparator C omp22, memory capacitance C22, MOS switch S 22 and S24, discharge current source Idch22, level shift follower f22 and bias current sources Ibias22 are used to detect down peak value.The output of complementary comparator C omp22 connects the source electrode of MOS switch S 22, the grounded-grid of MOS switch S 22, and the drain electrode of MOS switch S 22 connects the top crown of memory capacitance C22, the bottom crown ground connection of memory capacitance C22; The source electrode of level shift follower f22 connects the top crown of memory capacitance C22, and its drain electrode connects power supply Vdd, and grid is connected to the input end of bias current sources Ibias22; The output ground connection of bias current sources Ibias22, the input end of bias current sources Ibias22 connects divider resistance R23, R24 simultaneously, and R23 connects with R24; The positive and negative two ends of discharge current source Idch22 link to each other with the top crown of memory capacitance C22 with power supply Vdd respectively; The source electrode of MOS switch S 24 connects signal SETB, and the grid of MOS switch S 24 meets power supply Vdd, and the drain electrode of MOS switch S 24 connects the top crown of memory capacitance C22.The other end of divider resistance R22 links to each other with the other end of R24, complementary comparator C omp21 links to each other with the negative input end of complementary comparator C omp22, and connect input signal VIN simultaneously, the positive input terminal of complementary comparator C omp21 connects the grid of level shift follower f21, and the positive input terminal of complementary comparator C omp22 connects the grid of level shift follower f22.
For the sake of simplicity, be that example describes in detail with the testing process of upward peak, the testing process of following peak value and principle and its complete class with.The concrete principle of work of this circuit is such:
At first, input signal VIN and upward peak signal VP compare in comparator C omp21, when VIN 〉=VP, and switch S 21 conductings, mos capacitance C21 is recharged, and top crown voltage raises, and makes the value of VP raise, and up to VP=VIN, finishes the detection of upward peak.When VIN＜VP, switch S 21 is ended, and mos capacitance C21 is discharged, and top crown voltage reduces, and the value of VP is reduced, and until VP=VIN, finishes the detection of upward peak.Wherein, fill conducting resistance Ron and capacitor C 21 decisions of (putting) electricity time by switch S 21, when this conducting resistance Ron is meant switch S 21 conductings, be presented on the resistance at its drain-source two ends, this resistance fills (putting) electric time constant RC with capacitor C 21 decisions.And discharge current source Idch21 is a normal open state, guarantees that peak value has certain decay, and the order of magnitude of discharge current generally below 1 μ A, can be determined concrete numerical value according to the requirement of discharge time.
After upper and lower peak value detects and finishes, through resistance R 21～R24 dividing potential drop, produce common mode voltage COM, first peak value equals Vpp/2+COM, and second peak value equals-Vpp/2+COM, and wherein, COM voltage equates with the common mode voltage of input signal VIN.
If the voltage on C21, the C22 is respectively V
C21, V
C22, then have:
V
c21＝V
pp+COM-V
gsp (1)
V
C22=-V
Pp+ COM+V
Gsn(2) wherein, Vgsp and Vgsn are respectively the source gate voltage of follower f21 and the gate source voltage of follower f22.
In fact, COM is that the common mode voltage of peak value up and down equals (VP+VN)/2, and its algorithm is changeless, but the size of its value is different according to different supply voltages, and the value that generally requires COM is between 1.5V～2.5V.Vpp is the peak-to-peak value of input signal, and different Vpp are also different with the attenuation degree of signal in transmission course, and it is big more to decay, and Vpp is more little, and Vpp is generally between 200mV～1.5V.Vgsp, Vgsn are respectively the gate source voltage of follower f21, f22, the shift levels value of two followers just, and the size of Vgsp and Vgsn is generally about 1V.
According to above-mentioned analysis, when supply voltage Vdd=5V, COM can choose about 2.5V, and Vpp is 0.1V～1V, and Vgsp, Vgsn so, are not difficult to draw V from formula (1), formula (2) about 1V
C21At least more than 1.5V, and V
C22At least more than 2V, such voltage is enough to make the capacitance of mos capacitance stable, thereby has guaranteed to use the reliability and stability of mos capacitance.
Fig. 3 is for adopting the HspiceS simulation result synoptic diagram of the utility model peak detection circuit, shown in the left figure among Fig. 3, VIN is that High Density Bipolar 3 (HDB3) connects zero sign indicating number input signal, VP, VN are respectively the upper and lower peak signal of detection, can be clear that among the figure that VP, VN from initial voltage, follow the tracks of the process of the upper and lower peak value of VIN gradually.The right side figure of Fig. 3 is the partial enlarged drawing partly of drawing a circle among the left figure, can see the electric capacity charge and discharge process of amplification.This analogous diagram proves that circuit of the present utility model can reach the function of detection signal peak value fully.
Fig. 4 is the circuit theory diagrams of comparer, and as shown in Figure 4, this is the differential pair tube of a pair of complementation to comparer Comp21, Comp22, constitutes a pair of upper and lower peak follower with follower f21, f22.So-called complementation is meant: to pipe, import pipe with PMOS by following peak value with the NMOS input for the upward peak of this comparer.The gain of Comp21, Comp22 is generally 40～50dB.
Among Fig. 4, Comp21 is the upward peak comparer, and MN1, MN2 form the input difference of Comp21 to pipe, and MP1, MP2 are its current source loads, and Ibias1 is a bias current sources, and INP1, INN1 are respectively the positive and negative input end of Comp21, and VOUT1 is an output terminal; Comp22 is following peak comparator, and MP3, MP4 form the input difference of Comp22 to pipe, and MN3, MN4 are its current source loads, and Ibias2 is a bias current sources, and INP2, INN2 are respectively the positive and negative input end of Comp22, and VOUT2 is an output terminal.
Comparer of the present utility model adopts the superior part of complementary type differential pair tube to be: can avoid the super scope of input voltage.Because upward peak voltage is greater than common mode voltage, so import to managing, to avoid exceeding the input range of input to the pipe common mode voltage with the conduct of NMOS pipe; And crest voltage is imported pipe with the conduct of PMOS pipe less than common mode voltage down, to avoid exceeding the input range of input to the pipe common mode voltage.
Charging modes in the utility model circuit also can adopt various forms, such as: the mode with switch control constant current source is charged, and that is to say, different forms can be arranged for the mode of capacitor C 21, C22 charge/discharge.In addition, comparer also can adopt two-stage amplifier, as shown in Figure 5; Or the cascode structure for amplifying, as shown in Figure 6; Or other circuit structure with equal effect.The metal-oxide-semiconductor switch also can adopt the CMOS complementary switch, as shown in Figure 7.Follower can be followed overlaying structure with two-stage, as shown in Figure 8.Current source can adopt the mirror-image constant flow source that draws electric current, as shown in Figure 9; Or for drawing the cascode constant current source of electric current, as shown in figure 10; Or for irritating the mirror-image constant flow source of electric current, as shown in figure 11; Or for irritating the cascode constant current source of electric current, as shown in figure 12; Or other circuit structure with equal effect is realized.
The above circuit of introducing is applicable to that supply voltage is the design of the interface circuit chips such as E1, T1 of 5V, is used for the data recovery circuit of receiving end.This circuit also can be applicable in the design of other circuit chip that needs said function, as a peak detection unit, and, in the design of circuit structure itself, can adopt identical multi-form of effect.This circuit has reduced the area of integrated circuit (IC) chip greatly, bigger advantage is being arranged aspect high integration, the low-power consumption, more is applicable to the said function demand, and requires little circuit of area occupied or device.
In a word, the above is preferred embodiment of the present utility model only, is not to be used to limit protection domain of the present utility model.
Claims (12)
1, a kind of complementary type difference peak detection circuit is characterized in that: be made of a pair of complementary comparer, a pair of level shift follower, pair of metal oxide semiconductor (MOS) memory capacitance, four MOS switches, a pair of discharge current source, a pair of bias current sources and above divider resistances at least;
Wherein, the output of the first complementary comparer connects the source electrode of a MOS switch, and the grid of this MOS switch links to each other with power supply, and its drain electrode connects the top crown of a MOS memory capacitance; The input end of first bias current sources links to each other with power supply, its output connects the grid of the first level shift follower, the grounded drain of this follower, source electrode connects the top crown of a MOS memory capacitance, the output of first bias current sources connects first, second divider resistance simultaneously, this two resistance series connection; The one MOS memory capacitance bottom crown ground connection, the first discharge current source is in parallel with a MOS memory capacitance; The source electrode of the 3rd MOS switch connects first signal end, its grounded-grid, and drain electrode connects the top crown of a MOS memory capacitance;
The output of the second complementary comparer connects the source electrode of the 2nd MOS switch, the grounded-grid of this MOS switch, and its drain electrode connects the top crown of the 2nd MOS memory capacitance, the bottom crown ground connection of this MOS memory capacitance; The source electrode of the second level shift follower connects the top crown of the 2nd MOS memory capacitance, its drain electrode connects power supply, grid is connected to the input end of second bias current sources, the output ground connection of this bias current sources, the input end of second bias current sources connects the 3rd, the 4th divider resistance simultaneously, this two resistance series connection; The positive and negative two ends in the second discharge current source link to each other with the top crown of power supply with the 2nd MOS memory capacitance respectively; The source electrode of the 4th MOS switch connects the secondary signal end, and its grid connects power supply, and drain electrode connects the top crown of the 2nd MOS memory capacitance;
The second, an end of the 4th divider resistance links to each other, and the negative input end of first, second complementary comparer links to each other, and connects an input signal simultaneously, and the positive input terminal of first, second complementary comparer connects the grid of first, second level shift follower respectively.
2, complementary type difference peak detection circuit according to claim 1 is characterized in that: described first comparer and second comparer are a pair of complementary differential pair tube.
3, complementary type difference peak detection circuit according to claim 1, it is characterized in that: described first comparer is the upward peak comparer, second comparer is following peak comparator.
4, complementary type difference peak detection circuit according to claim 1 and 2 is characterized in that: the input difference of described first comparer is a pair of NMOS pipe to pipe, and the input difference of described second comparer is a pair of PMOS pipe to pipe.
5, complementary type difference peak detection circuit according to claim 1, it is characterized in that: described comparer is the one-level differential amplifier, or is two-stage amplifier, or is common source and common grid amplifier.
6, complementary type difference peak detection circuit according to claim 1 is characterized in that: described MOS switch is a NMOS pipe switch, or is switching pmos, or is the CMOS complementary switch.
7, complementary type difference peak detection circuit according to claim 1, it is characterized in that: described follower is the follower that one-level or two-stage are followed stack.
8, complementary type difference peak detection circuit according to claim 1, it is characterized in that: described current source is the mirror-image constant flow source that draws electric current, or be the cascode constant current source that draws electric current, or be the mirror-image constant flow source of irritating electric current, or for irritating the cascode constant current source of electric current.
9, complementary type difference peak detection circuit according to claim 1 is characterized in that: described second divider resistance link to each other with the 4th divider resistance the end voltage be the common mode voltage of circuit.
10, complementary type difference peak detection circuit according to claim 9 is characterized in that: described common mode voltage is half of upward peak voltage and following crest voltage sum.
11, complementary type difference peak detection circuit according to claim 1, it is characterized in that: described first signal and secondary signal are a pair of inversion signal.
12, complementary type difference peak detection circuit according to claim 1, it is characterized in that: the charging modes of described MOS memory capacitance can be controlled by constant current source.
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| CN 01267474 CN2519284Y (en) | 2001-10-11 | 2001-10-11 | Mutual complementing differential peak value detecting circuit |
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| CN 01267474 CN2519284Y (en) | 2001-10-11 | 2001-10-11 | Mutual complementing differential peak value detecting circuit |
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| CN100437127C (en) * | 2004-04-05 | 2008-11-26 | 爱特梅尔公司 | Detector of differential threshold voltage |
| CN101271142B (en) * | 2007-03-21 | 2010-05-19 | 中国科学院电子学研究所 | Peak detection circuit integrated on CMOS single chip |
| CN102735910A (en) * | 2011-04-08 | 2012-10-17 | 中山大学 | Maximum peak voltage detection circuit |
| CN103001610A (en) * | 2012-11-02 | 2013-03-27 | 长沙景嘉微电子股份有限公司 | Threshold-adjustable peak detection circuit |
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- 2001-10-11 CN CN 01267474 patent/CN2519284Y/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100437127C (en) * | 2004-04-05 | 2008-11-26 | 爱特梅尔公司 | Detector of differential threshold voltage |
| CN101271142B (en) * | 2007-03-21 | 2010-05-19 | 中国科学院电子学研究所 | Peak detection circuit integrated on CMOS single chip |
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