CN201319605Y - TTL signal switching piece of PECL electrical level light module - Google Patents
TTL signal switching piece of PECL electrical level light module Download PDFInfo
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- CN201319605Y CN201319605Y CNU2008201835751U CN200820183575U CN201319605Y CN 201319605 Y CN201319605 Y CN 201319605Y CN U2008201835751 U CNU2008201835751 U CN U2008201835751U CN 200820183575 U CN200820183575 U CN 200820183575U CN 201319605 Y CN201319605 Y CN 201319605Y
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Abstract
The utility model relates to a TTL signal switching piece of a PECL electrical level light module, in particular to a PECL electrical level light module fitting; a transmitting input unit of the PECL electrical level light module receives TTL electrical level signal and inputs T1 by a electrical level, and a receiving output unit of the PECL electrical level light module is connected with a comparator; a signal detecting unit of the PECL electrical level light module is connected with the comparator, and the comparator provides two circuits of TTL electrical level signal output externally. The TTL signal switching piece of the PECL electrical level light module realizes the connection of the PECL electrical level signal and the TTL electrical level signal by utilizing a comparator, a resistance and a capacitance, thereby reducing the equipment cost.
Description
Technical field
The utility model relates to PECL level optical module accessory, a kind of specifically TTL signal converting spare of PECL level optical module.
Background technology
Many employing Transistor-Transistor Logic levels in the design of low rate optical communication product such as PDH optical transceiver, but the optical module supplier of Transistor-Transistor Logic level is few, and supply cycle is long, is difficult to buy.Use the TTL optical module during low rate products such as so a large amount of production PDH optical transceivers, purchasing problem is very outstanding.The optical module of 1 * 9 encapsulation that present supplier provides mainly is a PECL level optical module, and uses PECL level optical module just to have the interconnection problems of PECL level signal and Transistor-Transistor Logic level signal.The adaptor of at present existing this interconnection of a plurality of manufacturer production.The most frequently used adaptor as shown in Figure 1.Chip IC 1 is finished the conversion of Transistor-Transistor Logic level signal to the PECL level signal, the PECL of IC1 exports the PECL input of the transmission input unit that connects PECL level optical module, and adopts R1, R2, R7, R8 to realize sending 50 ohm of terminations of input unit PECL input and importing direct current biasing.Chip IC 2 is finished the conversion of PECL level signal to the Transistor-Transistor Logic level signal, the PECL of the reception output unit of PECL level optical module output connects the PECL input of IC2, and adopts R3, R4, R9, R10 to realize the 50 ohm of terminations and the input direct current biasing of the PECL input of level translator IC2.In addition, the input PECL output SD signal of PECL level optical module connects the PECL input anode of IC2, and adopt R5, R11 to realize that the PECL of level translator IC2 imports 50 ohm of terminations of anode and imports direct current biasing, the PECL negative terminal of the corresponding SD input of IC2 is directly used resistance R6, the R12 termination.Therefore, this adaptor need be used two level transferring chip IC1 and IC2, and equipment cost is increased greatly.
The utility model content
At the defective that exists in the prior art, the purpose of this utility model is to provide a kind of TTL signal converting spare of PECL level optical module, the circuit that utilizes comparator, resistance, electric capacity to form is realized the interconnection of PECL level signal and Transistor-Transistor Logic level signal, thereby has been reduced equipment cost.
For reaching above purpose, the technical scheme that the utility model is taked is:
A kind of TTL signal converting spare of PECL level optical module, it is characterized in that: the TD+ pin of the transmission input unit of PECL level optical module receives Transistor-Transistor Logic level signal input T1 by resistance-capacitance circuit, the TD-pin is connected with an end of resistance R 2, an end of resistance R 8 respectively, another termination VCC of resistance R 2, the other end ground connection of resistance R 8; The RD+ pin of the reception output unit of PECL level optical module is connected with an end of resistance R 3, an end of resistance R 9, the A+ pin of comparator respectively, another termination VCC of resistance R 3, the other end ground connection of resistance R 9; The RD-pin is connected with an end of resistance R 4, an end of resistance R 10, the A-pin of comparator respectively, another termination VCC of resistance R 4, the other end ground connection of resistance R 10; The SD+ pin of the detecting signal unit of PECL level optical module is connected with an end of resistance R 5, an end of resistance R 11, the B+ pin of comparator respectively, another termination VCC of resistance R 5, the other end ground connection of resistance R 11; The B-pin of comparator is connected with an end of resistance R 6, an end of resistance R 12 respectively, another termination VCC of resistance R 6, the other end ground connection of resistance R 12; Comparator externally provides the output of two-way Transistor-Transistor Logic level signal.
On the basis of technique scheme, said resistance-capacitance circuit comprises the resistance R 13 and the capacitor C 1 of series connection, capacitor C 1 connects the input of Transistor-Transistor Logic level signal, resistance R 13 connects the TD+ pin of the transmission input unit of PECL level optical module, the common port of resistance R 13 and capacitor C 1 is connected with an end of resistance R 7, the other end ground connection of resistance R 7, the TD+ pin of the transmission input unit of a termination PECL level optical module of resistance R 1, another termination VCC terminal.
On the basis of technique scheme, the model of said comparator is DS26C32.
The TTL signal converting spare of PECL level optical module described in the utility model, the circuit that utilizes comparator, resistance, electric capacity to form is realized the interconnection of PECL level signal and Transistor-Transistor Logic level signal, thereby has been reduced equipment cost.
Description of drawings
The utility model has following accompanying drawing:
PECL level signal that Fig. 1 uses always and Transistor-Transistor Logic level signal interconnection method
Fig. 2 electrical block diagram of the present utility model
Fig. 3 circuit structure schematic diagram of the present utility model
The oscillogram of each point among Fig. 4 Fig. 3
Embodiment
Below in conjunction with accompanying drawing the utility model is described in further detail.
Fig. 2 is the electrical block diagram of the TTL signal converting spare of PECL level optical module described in the utility model, and as shown in the figure, the transmission input unit of PECL level optical module receives Transistor-Transistor Logic level signal input T1 by resistance-capacitance circuit; The reception output unit of PECL level optical module is connected with comparator; The detecting signal unit of PECL level optical module is connected with comparator; Comparator externally provides the output of two-way Transistor-Transistor Logic level signal.More particularly: the TD+ pin of the transmission input unit of PECL level optical module receives Transistor-Transistor Logic level signal input T1 by resistance-capacitance circuit, the TD-pin is connected with an end of resistance R 2, an end of resistance R 8 respectively, another termination VCC of resistance R 2, the other end ground connection of resistance R 8; The RD+ pin of the reception output unit of PECL level optical module is connected with an end of resistance R 3, an end of resistance R 9, the A+ pin of comparator respectively, another termination VCC of resistance R 3, the other end ground connection of resistance R 9; The RD-pin is connected with an end of resistance R 4, an end of resistance R 10, the A-pin of comparator respectively, another termination VCC of resistance R 4, the other end ground connection of resistance R 10; The SD+ pin of the detecting signal unit of PECL level optical module is connected with an end of resistance R 5, an end of resistance R 11, the B+ pin of comparator respectively, another termination VCC of resistance R 5, the other end ground connection of resistance R 11; The B-pin of comparator is connected with an end of resistance R 6, an end of resistance R 12 respectively, another termination VCC of resistance R 6, the other end ground connection of resistance R 12; Comparator externally provides the output of two-way Transistor-Transistor Logic level signal.
On the basis of technique scheme, as shown in Figure 3, said resistance-capacitance circuit comprises the resistance R 13 and the capacitor C 1 of series connection, capacitor C 1 connects the input of Transistor-Transistor Logic level signal, resistance R 13 connects the TD+ pin of the transmission input unit of PECL level optical module, and the common port of resistance R 13 and capacitor C 1 and an end of resistance R 7 are connected the other end ground connection of resistance R 7, the TD+ pin of the transmission input unit of one termination PECL level optical module of resistance R 1, another termination VCC terminal.Wherein, form of the conversion of PECL level signal by comparator IC1, R6, R12, R5, R11 to the Transistor-Transistor Logic level signal; Form of the conversion of Transistor-Transistor Logic level signal jointly by R1, R2, R8, R13, R7, C1 to the PECL level signal.
On the basis of technique scheme, the model of said comparator is DS26C32.
The course of work of the present utility model is as follows: the input of the transmission input unit of PECL level optical module receives the input of Transistor-Transistor Logic level signal by resistance-capacitance circuit, resistance-capacitance circuit comprises the resistance that connects optical module TD-, TD-is fixed on 2V, the resistance that connects optical module TD+ is realized the dead level of 2V, capacitor C 1 realizes AC coupled, the TTL signal fluctuates up and down at 2V through C1 coupling back, be higher than 2V during logical one, it then is the logical one of PECL, be lower than 2V during logical zero, then be the logical zero of PECL, thereby realize the conversion of TTL, satisfy the input requirement of the inner PECL emission driver of optical module to the PECL level.The output of the reception output unit of PECL level optical module is connected with comparator, comparator adopts DS26C32, DS26C32 has 4 groups of input and output, the output of the reception output unit of PECL level optical module is the PECL differential signal, connect one group of input of comparator, RD+ connects A+, RD-connects A-, characteristic V (A+)-V (A-)＞V (TH) by comparator, V (TH) is the reference level of comparator, comparator output logic " 1 " then, otherwise output logic " 0 ", realize the output of Transistor-Transistor Logic level signal, realize the 50 ohm of terminations and the direct current biasing of PECL input with resistance.As a same reason, the output SD signal of detecting signal unit connects the anode B+ of another group input B of DS26C32, negative terminal B-is fixed on 2V with resistance, it is 2.4V that light time SD signal is arranged, then by output logic " 1 " behind the comparator, the SD signal is 1.7V when unglazed, then by output logic " 0 " behind the comparator, realizes the Transistor-Transistor Logic level output of SD signal.Fig. 4 is the oscillogram of each point in Fig. 3 circuit.By Fig. 1 and Fig. 3 more as can be seen, the utility model utilizes comparator and resistance capacitance, has replaced two level transferring chip, cost greatly reduces, in production in enormous quantities, its economic benefit is very considerable.
Claims (3)
1. the TTL signal converting spare of a PECL level optical module, it is characterized in that: the TD+ pin of the transmission input unit of PECL level optical module receives Transistor-Transistor Logic level signal input T1 by resistance-capacitance circuit, the TD-pin is connected with an end of resistance R 2, an end of resistance R 8 respectively, another termination VCC of resistance R 2, the other end ground connection of resistance R 8; The RD+ pin of the reception output unit of PECL level optical module is connected with an end of resistance R 3, an end of resistance R 9, the A+ pin of comparator respectively, another termination VCC of resistance R 3, the other end ground connection of resistance R 9; The RD-pin is connected with an end of resistance R 4, an end of resistance R 10, the A-pin of comparator respectively, another termination VCC of resistance R 4, the other end ground connection of resistance R 10; The SD+ pin of the detecting signal unit of PECL level optical module is connected with an end of resistance R 5, an end of resistance R 11, the B+ pin of comparator respectively, another termination VCC of resistance R 5, the other end ground connection of resistance R 11; The B-pin of comparator is connected with an end of resistance R 6, an end of resistance R 12 respectively, another termination VCC of resistance R 6, the other end ground connection of resistance R 12; Comparator externally provides the output of two-way Transistor-Transistor Logic level signal.
2. the TTL signal converting spare of PECL level optical module as claimed in claim 1, it is characterized in that: said resistance-capacitance circuit comprises the resistance R 13 and the capacitor C 1 of series connection, capacitor C 1 connects the input of Transistor-Transistor Logic level signal, resistance R 13 connects the TD+ pin of the transmission input unit of PECL level optical module, the common port of resistance R 13 and capacitor C 1 is connected with an end of resistance R 7, the other end ground connection of resistance R 7, the TD+ pin of the transmission input unit of one termination PECL level optical module of resistance R 1, another termination VCC terminal.
3. the TTL signal converting spare of PECL level optical module as claimed in claim 1 or 2 is characterized in that: the model of said comparator is DS26C32.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201835751U CN201319605Y (en) | 2008-12-23 | 2008-12-23 | TTL signal switching piece of PECL electrical level light module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201835751U CN201319605Y (en) | 2008-12-23 | 2008-12-23 | TTL signal switching piece of PECL electrical level light module |
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| Publication Number | Publication Date |
|---|---|
| CN201319605Y true CN201319605Y (en) | 2009-09-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008201835751U Expired - Lifetime CN201319605Y (en) | 2008-12-23 | 2008-12-23 | TTL signal switching piece of PECL electrical level light module |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105141305A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Level conversion method and device |
| CN107465397A (en) * | 2017-08-08 | 2017-12-12 | 中国电子科技集团公司第二十九研究所 | A kind of LVPECL signal communications termination power and its selection control method |
| CN107786311A (en) * | 2016-08-26 | 2018-03-09 | 成都芯瑞科技股份有限公司 | Device for detecting code error |
-
2008
- 2008-12-23 CN CNU2008201835751U patent/CN201319605Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105141305A (en) * | 2015-09-11 | 2015-12-09 | 英特格灵芯片(天津)有限公司 | Level conversion method and device |
| CN105141305B (en) * | 2015-09-11 | 2018-06-15 | 英特格灵芯片(天津)有限公司 | A kind of method and device of level conversion |
| CN107786311A (en) * | 2016-08-26 | 2018-03-09 | 成都芯瑞科技股份有限公司 | Device for detecting code error |
| CN107465397A (en) * | 2017-08-08 | 2017-12-12 | 中国电子科技集团公司第二十九研究所 | A kind of LVPECL signal communications termination power and its selection control method |
| CN107465397B (en) * | 2017-08-08 | 2020-09-29 | 中国电子科技集团公司第二十九研究所 | LVPECL signal alternating-current coupling circuit and selection control method thereof |
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Legal Events
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170330 Address after: 430074 East Lake high tech Development Zone, Hubei Province, No. 6, No., high and new technology development zone, No. four Patentee after: Fenghuo Communication Science &. Technology Co., Ltd. Address before: East Lake high tech city of Wuhan province Hubei Dongxin road 430074 No. 5 East optical communication industry building in Wuhan Fenghuo Network Co Ltd Patentee before: Wuhan Fenghuo Network Co., Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090930 |