CN205232207U - Two bus data transmitting circuit - Google Patents
Two bus data transmitting circuit Download PDFInfo
- Publication number
- CN205232207U CN205232207U CN201521109284.4U CN201521109284U CN205232207U CN 205232207 U CN205232207 U CN 205232207U CN 201521109284 U CN201521109284 U CN 201521109284U CN 205232207 U CN205232207 U CN 205232207U
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- resistance
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- circuit
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- bus
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Abstract
The utility model relates to a two bus data transmitting circuit, by signal shaping circuit, switch drive circuit is managed to high -power MOS pipe, MOS, and the high power inductors in the bus constitutes, the high -low level signal that characterized by microprocessor produced through the plastic of signal shaping circuit limit for width, through MOS pipe switch drive circuit, drives high -power MOS pipe again, two total line voltages of control, and under high power inductors's the isolation, data can simultaneous transmission with the power in the bus.
Description
Technical field
The utility model relates to two line communication technical field, particularly relates to a kind of two lines bus data transmit circuit.
Background technology
Two lines bus data transmit circuit complicated structure traditional at present, driving force is poor, bus protection measure imperfection, high in cost of production.
Summary of the invention
Goal of the invention:
The weak point existed in background technology, the two lines bus data transmit circuit that design that a kind of circuit structure is simple, driving force is strong, there is stronger bus protection function.
Technical scheme:
The utility model is achieved through the following technical solutions:
A kind of two lines bus data transmit circuit, comprising: signal transformation circuit, high-power MOS tube, MOS switch driving circuit, the high-power inductance in bus.
In signal transformation circuit, microprocessor output pulse signal is to 2 pins of not gate U1A when sending out data, through exporting the contrary pulse signal of phase place with the pin 3 of non-U1A, through electric capacity C2, exporting at the pin 6 of NAND gate U1B and exporting the identical signal of impulse phase with microprocessor; Through triode Q2, the drive circuit driving high-power MOS tube of Q3, Q4 composition realizes the voltage control on two lines bus, and the data completed on two lines bus send; Due to the isolated DC effect of C2, pulse can be passed through, and when microprocessor breaks down, the pin 4,5 of NAND gate U1B reverts to low level, thus makes the pin 6 of NAND gate U1B export high level, makes metal-oxide-semiconductor remain off state; Wherein R2 and C2 forms resistance-capacitance type time constant circuit, realizes pulse duration restriction, is conducive to improving transmission speed, reduces metal-oxide-semiconductor power consumption.
In MOS switch driving circuit, metal-oxide-semiconductor adopts low-power consumption high-power MOS tube, bus adopts high-power inductance, allows to reach tens amperes by electric current, can for two lines bus providing very large driving force.
Advantage and effect:
The utility model is compared with background technology, and advantage is as follows: one is that power is large, and driving force is strong; Two is have pulse duration limitation function, effectively prevents bus short circuit; Three is that circuit structure is simple, and components and parts are few, and cost is low, and reliability is high.
Accompanying drawing illustrates:
A kind of two lines bus data transmit circuit of Fig. 1 structure chart.
Embodiment:
Below in conjunction with the drawings and specific embodiments, the present invention will be further described, and the utility model protection range is not only confined to the statement of following content.
As Fig. 1: comprise Microprocessor Interface C, signal transformation circuit, high-power MOS tube, MOS switch driving circuit and high-power inductance L1; Wherein said Microprocessor Interface C exports 2 pins of low and high level signal to signal transformation circuit U1A; Described signal transformation circuit comprises: NAND gate U1A, U1B, resistance R1, R2, electric capacity C1, C2; Wherein 1 pin contact resistance R1 one end of NAND gate U1A, the resistance R1 other end connects 5V power supply and electric capacity C1, electric capacity C1 other end ground connection; 3 pins of NAND gate U1A connect one end of electric capacity C2,4,5 pins of electric capacity C2 other end connecting resistance R2 and NAND gate U1B, wherein R2 other end ground connection; 6 pins of NAND gate U1B are signal transformation circuit output pin.
High-power inductance in described bus, for being connected in bus, can pass through D.C. high-current, and the high-power inductance L1 of isolation pulse signal.
Described MOS switch driving circuit comprises: resistance R3, R4, R5, R6, triode Q2, Q3, Q4; Wherein resistance R3 mono-termination signal transformation circuit output pin, another termination triode Q2 base stage and resistance R4, wherein R4 other end ground connection; Triode Q2 grounded emitter, the base stage of collector electrode connecting resistance R5 one end and Q3 and Q4; Another termination 5V power supply of resistance R5; The collector electrode of triode Q4 connects 5V power supply, and emitter connects one end of triode Q3 emitter and resistance R6, wherein triode Q3 grounded collector; Another termination high-power MOS tube of resistance R6 Q1 grid, wherein high-power MOS tube Q1 drain electrode connects two lines bus positive pole and inductance L 1, source ground.
Be understandable that, above about specific descriptions of the present utility model, the technical scheme described by the utility model embodiment is only not limited to for illustration of the utility model, those of ordinary skill in the art is to be understood that, still can modify to the utility model or equivalent replacement, to reach identical technique effect; Use needs as long as meet, all within protection range of the present utility model, the content be not described in detail in the utility model specification belongs to the known technology of those skilled in the art.
Claims (2)
1. a two lines bus data transmit circuit, comprising: signal transformation circuit, high-power MOS tube, MOS switch driving circuit, the high-power inductance in bus;
Described signal transformation circuit, comprising: NAND gate U1A, U1B, resistance R1, R2, electric capacity C1, C2; Wherein 1 pin contact resistance R1 one end of NAND gate U1A, the resistance R1 other end connects 5V power supply and electric capacity C1, electric capacity C1 other end ground connection; 3 pins of NAND gate U1A connect one end of electric capacity C2,4,5 pins of electric capacity C2 other end connecting resistance R2 and NAND gate U1B, wherein R2 other end ground connection; 6 pins of NAND gate U1B are signal transformation circuit output pin;
High-power inductance in described bus, for being connected in bus, can pass through D.C. high-current, and the high-power inductance L1 of isolation pulse signal;
Described MOS switch driving circuit comprises: resistance R3, R4, R5, R6, triode Q2, Q3, Q4; Wherein resistance R3 mono-termination signal transformation circuit output pin, another termination triode Q2 base stage and resistance R4, wherein R4 other end ground connection; Triode Q2 grounded emitter, the base stage of collector electrode connecting resistance R5 one end and Q3 and Q4; Another termination 5V power supply of resistance R5; The collector electrode of triode Q4 connects 5V power supply, and emitter connects one end of triode Q3 emitter and resistance R6, wherein triode Q3 grounded collector; Another termination high-power MOS tube of resistance R6 Q1 grid, wherein high-power MOS tube Q1 drain electrode is connected with two lines bus and inductance L 1, source ground.
2. a kind of two lines bus data transmit circuit according to claim 1, is characterized in that R2 and C2 forms the resistance-capacitance type time constant circuit of pulse-width restriction and short-circuit protection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521109284.4U CN205232207U (en) | 2015-12-29 | 2015-12-29 | Two bus data transmitting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521109284.4U CN205232207U (en) | 2015-12-29 | 2015-12-29 | Two bus data transmitting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205232207U true CN205232207U (en) | 2016-05-11 |
Family
ID=55907249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521109284.4U Withdrawn - After Issue CN205232207U (en) | 2015-12-29 | 2015-12-29 | Two bus data transmitting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205232207U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105429655A (en) * | 2015-12-29 | 2016-03-23 | 踪念品 | Two-bus data transmitting circuit |
-
2015
- 2015-12-29 CN CN201521109284.4U patent/CN205232207U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105429655A (en) * | 2015-12-29 | 2016-03-23 | 踪念品 | Two-bus data transmitting circuit |
| CN105429655B (en) * | 2015-12-29 | 2017-09-08 | 踪念品 | A kind of two lines bus data transtation mission circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20160511 Effective date of abandoning: 20170908 |