CN203151466U - Positive-negative logic level conversion switching circuit - Google Patents
Positive-negative logic level conversion switching circuit Download PDFInfo
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- CN203151466U CN203151466U CN 201220693844 CN201220693844U CN203151466U CN 203151466 U CN203151466 U CN 203151466U CN 201220693844 CN201220693844 CN 201220693844 CN 201220693844 U CN201220693844 U CN 201220693844U CN 203151466 U CN203151466 U CN 203151466U
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Abstract
本实用新型公开一种正负逻辑电平转换电路，其包括有：一负压转正压电路及一正压转负压电路，其中，当计算机向嵌入式设备发送数据时，该数据需通过负压转正压电路进行电压转换，将计算机所发出的RS232电平转换为TTL电平，且传输至嵌入式设备；当嵌入式设备向计算机发送数据时，该数据需通过正压转负压电路进行电压转换，将嵌入式设备所发出的TTL电平转换为RS232电平，且传输至计算机，从而实现了计算机与嵌入式设备的双工通讯。本实用新型相比现有技术而言，具有成本低以及应用灵活的优点。
The utility model discloses a positive and negative logic level conversion circuit, which comprises: a negative pressure to positive voltage circuit and a positive pressure to negative voltage circuit, wherein, when a computer sends data to an embedded device, the data needs to pass through The negative voltage to positive voltage circuit performs voltage conversion, converts the RS232 level sent by the computer to TTL level, and transmits it to the embedded device; when the embedded device sends data to the computer, the data needs to be converted from positive to negative. The circuit performs voltage conversion, converts the TTL level sent by the embedded device into the RS232 level, and transmits it to the computer, thereby realizing the duplex communication between the computer and the embedded device. Compared with the prior art, the utility model has the advantages of low cost and flexible application.
Description
Technical field
The utility model relates to computer and embedded device communication technique field, relates in particular to a kind of mixed logic level shifting circuit.
Background technology
Increasing along with the continuous development of electronic technology and electronic equipment, the information interaction between each equipment is also frequent day by day, and is also more and more higher to the requirement of electronic equipment interfaces technology simultaneously.So occurred various types of interfaces on the market, for example USB interface, serial ports, RS232 interface, RS485 interface and SPI interface etc.Wherein, the RS232 interface is one of personal computer communication interface, and also be reserved with asynchronous serial port in most of electronic equipment, the two is based on the asynchronous serial port agreement and realizes communication, so this interface mode can be used for the mutual communication between personal computer and the electronic equipment, thereby finish operations such as download, debugging and data upload.The asynchronous serial port of computer comprises Transistor-Transistor Logic level serial ports and RS232 level serial ports, in the duplex signaling of computer and embedded device, the asynchronous serial port of computer is output logic 0 and logical one in RS232 level mode usually, its voltage that reflects when logical zero is 3～15V, the voltage that reflects when logical one is-3～-15V, but the main Transistor-Transistor Logic level mode of using in the serial ports of embedded device, the voltage that reflects when transmission logic 0 and logical one is all more than 0V.Because there is negative voltage in the asynchronous serial port of computer, make directly communication between computer and the embedded device.
In existing scheme, mainly be to use RS232 level logic conversion chip, more typical chip is MAX232, this chip can be finished the conversion between RS232 level logic and the Transistor-Transistor Logic level logic.Though this logic level transition chip is comparatively ripe, it still has the higher defective of cost, and simultaneously, this logic level transition chip only can be applied in the RS232 communication modes, and application flexibility is relatively poor, is difficult to adapt in the communicating circuit of other types.
Therefore, existing logic level transition mode, it has the defective of cost height, application flexibility difference.
The utility model content
The technical problems to be solved in the utility model is, a kind of mixed logic level shifting circuit is provided, and this circuit has the advantage of the low and applying flexible of cost.
For solving the problems of the technologies described above, the utility model adopts following technical scheme.
A kind of mixed logic level shifting circuit, it includes: the negative pressure volt circuit of becoming a full member, the described negative pressure volt circuit of becoming a full member includes NPN pipe Q2, the base stage of described NPN pipe Q2 is by resistance R 7 ground connection, this base stage also connects resistance R 6, the other end of this resistance R 6 as negative pressure become a full member volt circuit input and be connected to the transmitting terminal PC-TXD of computer, the grounded emitter of described NPN pipe Q2, its collector electrode is connected to the power end VCC33 of embedded device by resistance R 8, this collector electrode also connects resistance R 5, the other end of this resistance R 5 as negative pressure become a full member volt circuit output and be connected to the receiving terminal UART-RXD of embedded device; One malleation is changeed the negative pressure circuit, described malleation is changeed the negative pressure circuit and is included PNP pipe Q1, the base stage of described PNP pipe Q1 is connected to capacitor C 1 by resistance R 1, the other end of this capacitor C 1 changes the input of negative pressure circuit as malleation and is connected to the transmitting terminal of embedded device, described resistance R 1 and the tie point of capacitor C 1 also are connected the anode of diode D1, the negative electrode of described diode D1 is connected to the emitter of PNP pipe Q1, link to each other by resistance R 2 between the base stage of this PNP pipe Q1 and the emitter, this emitter also is connected to the positive power source terminal 232VCC of computer, the collector electrode of described PNP pipe Q1 is connected to the negative power end 232VEE of computer by resistance R 3, this collector electrode also connects resistance R 4, and the other end of this resistance R 4 changes the output of negative pressure circuit as malleation and is connected to the receiving terminal PC-RXD of computer.
Preferably, described negative pressure is become a full member in the volt circuit, and the power end VCC33 of embedded device is also by capacitor C 5 and ground connection, and described resistance R 6 also is parallel with capacitor C 6.
Preferably, described malleation is changeed in the negative pressure circuit, and the negative power end 232VEE of computer is by capacitor C 3 ground connection, and the positive power source terminal 232VCC of computer is by capacitor C 4 ground connection, and described resistance R 1 is parallel with capacitor C 2.
In a kind of mixed logic level shifting circuit disclosed in the utility model, when computer sends data to embedded device, this data need to carry out voltage transitions by the negative pressure volt circuit of becoming a full member, and the RS232 level conversion that computer is sent is Transistor-Transistor Logic level, and transfers to embedded device; When embedded device sent data to computer, these data needed to change the negative pressure circuit by malleation and carry out voltage transitions, and the Transistor-Transistor Logic level that embedded device is sent is converted to the RS232 level, and transfers to computer.Thereby realized the duplex signaling of computer and embedded device, and substituted existing logic level transition chips such as MAX232.This circuit is made of common component, so its cost is lower, for the mass production of electronic equipment provides cost savings spending, simultaneously, because this mixed logic level shifting circuit can effectively be finished the mutual conversion between RS232 level and the Transistor-Transistor Logic level, therefore, this circuit can also be applied to have better flexibility in the communication modes of other types.
Description of drawings
Fig. 1 is the circuit block diagram of the mixed logic level shifting circuit that the utility model proposes.
Fig. 2 is the become a full member circuit theory diagrams of volt circuit of negative pressure.
Fig. 3 changes the circuit theory diagrams of negative pressure circuit for malleation.
Embodiment
Below in conjunction with drawings and Examples the utility model is done more detailed description.
The utility model discloses a kind of mixed logic level shifting circuit, and as shown in Figure 1, it includes: become a full member volt circuit 10 and a malleation of a negative pressure changeed negative pressure circuit 20, wherein:
In conjunction with Figure 1 and Figure 2, the described negative pressure volt circuit 10 of becoming a full member includes NPN pipe Q2, the base stage of described NPN pipe Q2 is by resistance R 7 ground connection, this base stage also connects resistance R 6, the other end of this resistance R 6 as negative pressure become a full member volt circuit 10 input and be connected to the transmitting terminal PC-TXD of computer 30, the grounded emitter of described NPN pipe Q2, its collector electrode is connected to the power end VCC33 of embedded device 40 by resistance R 8, this collector electrode also connects resistance R 5, the other end of this resistance R 5 as negative pressure become a full member volt circuit 10 output and be connected to the receiving terminal UART-RXD of embedded device 40.
Above-mentioned negative pressure is become a full member in the volt circuit 10, when the transmitting terminal PC-TXD of computer 30 output logic 0, its output level is 3V～15V, after this voltage passes through resistance R 6 and resistance R 7 dividing potential drops, make on the resistance R 7 and to produce the base stage that positive voltage and this voltage load on NPN pipe Q2, when the voltage on the resistance R 7 reaches 0.6V, NPN pipe Q2 conducting, because the receiving terminal UART-RXD of embedded device 40 is by resistance R 5 and NPN pipe Q2 ground connection, make that the voltage of receiving terminal UART-RXD of embedded device 40 is 0V, thereby make embedded device 40 receive logical zero; When the transmitting terminal PC-TXD of computer 30 output logic 1, its output level is-3V～-15V, after this voltage passes through resistance R 6 and resistance R 7 dividing potential drops, make on the resistance R 7 and to produce the base stage that negative voltage and this voltage load on NPN pipe Q2, at this moment, NPN pipe Q2 ends, because the receiving terminal UART-RXD of embedded device 40 is connected to the power end VCC33 of embedded device 40 by resistance R 5 and resistance R 6, make that the voltage of receiving terminal UART-RXD of embedded device 40 is high level voltage, thereby make embedded device 40 receive logical one.
In conjunction with Fig. 1 and shown in Figure 3, described malleation is changeed negative pressure circuit 20 and is included PNP pipe Q1, the base stage of described PNP pipe Q1 is connected to capacitor C 1 by resistance R 1, the other end of this capacitor C 1 changes the input of negative pressure circuit 20 as malleation and is connected to the transmitting terminal of embedded device 40, described resistance R 1 and the tie point of capacitor C 1 also are connected the anode of diode D1, the negative electrode of described diode D1 is connected to the emitter of PNP pipe Q1, link to each other by resistance R 2 between the base stage of this PNP pipe Q1 and the emitter, this emitter also is connected to the positive power source terminal 232VCC of computer 30, the collector electrode of described PNP pipe Q1 is connected to the negative power end 232VEE of computer 30 by resistance R 3, this collector electrode also connects resistance R 4, and the other end of this resistance R 4 changes the output of negative pressure circuit 20 as malleation and is connected to the receiving terminal PC-RXD of computer 30.
Above-mentioned malleation is changeed in the negative pressure circuit 20, and the output voltage of the positive power source terminal 232VCC of computer 30 is+8.5V that the output voltage of the negative power end 232VEE of computer 30 is-8.5V.Before embedded device 40 and computer 30 are set up communication, transmitting terminal UART-TXD output high level and this transmitting terminal UART-TXD and the capacitor C 1 of Schilling embedded device 40, resistance R 1, the positive power source terminal 232VCC of resistance R 2 and computer 30 constitutes the loop, capacitor C 1 begins charging until being full of, when the transmitting terminal UART-TXD of embedded device 40 output logic 0, the voltage that this transmitting terminal UART-TXD reflects is 0V, capacitor C 1 is discharge rapidly by the afterflow effect of diode D1, make the voltage of tie point of capacitor C 1 and resistance R 1 descend, at this moment, the positive power source terminal 232VCC of computer 30, resistance 2 and resistance R 1 constitute bigoted circuit, when the voltage of capacitor C 1 and resistance R 1 tie point drops to 0.6V, this voltage transfers to the base stage of PNP pipe Q1 by resistance R 1, PNP pipe Q1 conducting, and by drawing effect on the resistance R 4, the positive voltage of the positive power source terminal 232VCC of computer 30 output is transferred to the receiving terminal PC-RXD of computer 30, make this receiving terminal PC-RXD receive logical zero; When the transmitting terminal UART-TXD of embedded device 40 output logic 1, the voltage that this transmitting terminal UART-TXD exports is high level voltage, at this moment, because still conducting of PNP pipe Q1, so, the positive power source terminal 232VCC of computer 30 is by PNP pipe Q1 and resistance R 1 and to capacitor C 1 charging, it is equivalent to open circuit for direct current signal when capacitor C 1 is full of, no current flows through on the resistance R 2, PNP pipe Q1 ends, the negative voltage of the negative power end 232VEE of computer 30 output transfers to the receiving terminal PC-RXD of computer 30 by resistance R 3 and resistance R 4, makes this receiving terminal PC-RXD receive logical one.
As shown in Figure 2, described negative pressure is become a full member in the volt circuit 10, and the power end VCC33 of embedded device 40 is also by capacitor C 5 and ground connection, and described resistance R 6 also is parallel with capacitor C 6.Wherein, capacitor C 5 is used for the filtering noise jamming, and capacitor C 6 is used for improving the conducting speed of NPN pipe Q2 as speed-up capacitor.
As shown in Figure 3, described malleation is changeed in the negative pressure circuit 20, and the negative power end 232VEE of computer 30 is also by capacitor C 3 ground connection, and also by capacitor C 4 ground connection, described resistance R 1 also is parallel with capacitor C 2 to the positive power source terminal 232VCC of computer 30.Wherein, capacitor C 3 and capacitor C 4 are all for the filtering noise jamming, and capacitor C 2 is used for improving the conducting speed of PNP pipe Q1 as speed-up capacitor.
A kind of mixed logic level shifting circuit disclosed in the utility model, it can access following data by experiment:
On the basis of foregoing circuit principle, learn in conjunction with these data, when computer 30 sends data to embedded device 40, this data need to carry out voltage transitions by the negative pressure volt circuit 10 of becoming a full member, and the RS232 level conversion that computer 30 is sent is Transistor-Transistor Logic level, and transfers to embedded device 40; When embedded device 40 sent data to computer 30, these data needed to change negative pressure circuit 20 by malleation and carry out voltage transitions, and the Transistor-Transistor Logic level that embedded device 40 is sent is converted to the RS232 level, and transfers to computer 30.Thereby realized the duplex signaling of computer 30 and embedded device 40, and substituted existing logic level transition chip such as MAX232.This circuit is made of common component, so its cost is lower, for the mass production of electronic equipment provides cost savings spending, simultaneously, because this mixed logic level shifting circuit can effectively be finished the mutual conversion between RS232 level and the Transistor-Transistor Logic level, therefore, can also be applied to have had better flexibility in the communication modes of other types.
The above is the utility model preferred embodiment, is not limited to the utility model, all modifications of making in technical scope of the present utility model, is equal to and replaces or improvement etc., all should be included in the scope that the utility model protects.
Claims (3)
1. a mixed logic level shifting circuit is characterized in that, includes:
The one negative pressure volt circuit (10) of becoming a full member, the described negative pressure volt circuit (10) of becoming a full member includes NPN pipe Q2, the base stage of described NPN pipe Q2 is by resistance R 7 ground connection, this base stage also connects resistance R 6, the other end of this resistance R 6 as negative pressure become a full member volt circuit (10) input and be connected to the transmitting terminal PC-TXD of computer (30), the grounded emitter of described NPN pipe Q2, its collector electrode is connected to the power end VCC33 of embedded device (40) by resistance R 8, this collector electrode also connects resistance R 5, the other end of this resistance R 5 as negative pressure become a full member volt circuit (10) output and be connected to the receiving terminal UART-RXD of embedded device (40);
One malleation is changeed negative pressure circuit (20), described malleation is changeed negative pressure circuit (20) and is included PNP pipe Q1, the base stage of described PNP pipe Q1 is connected to capacitor C 1 by resistance R 1, the other end of this capacitor C 1 changes the input of negative pressure circuit (20) as malleation and is connected to the transmitting terminal of embedded device (40), described resistance R 1 and the tie point of capacitor C 1 also are connected the anode of diode D1, the negative electrode of described diode D1 is connected to the emitter of PNP pipe Q1, link to each other by resistance R 2 between the base stage of this PNP pipe Q1 and the emitter, this emitter also is connected to the positive power source terminal 232VCC of computer (30), the collector electrode of described PNP pipe Q1 is connected to the negative power end 232VEE of computer (30) by resistance R 3, this collector electrode also connects resistance R 4, and the other end of this resistance R 4 changes the output of negative pressure circuit (20) as malleation and is connected to the receiving terminal PC-RXD of computer (30).
2. mixed logic level shifting circuit as claimed in claim 1 is characterized in that, described negative pressure is become a full member in the volt circuit (10), and the power end VCC33 of embedded device (40) is also by capacitor C 5 and ground connection, and described resistance R 6 also is parallel with capacitor C 6.
3. mixed logic level shifting circuit as claimed in claim 1, it is characterized in that, described malleation is changeed in the negative pressure circuit (20), the negative power end 232VEE of computer (30) is by capacitor C 3 ground connection, the positive power source terminal 232VCC of computer (30) is by capacitor C 4 ground connection, and described resistance R 1 is parallel with capacitor C 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220693844 CN203151466U (en) | 2012-12-14 | 2012-12-14 | Positive-negative logic level conversion switching circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220693844 CN203151466U (en) | 2012-12-14 | 2012-12-14 | Positive-negative logic level conversion switching circuit |
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| CN203151466U true CN203151466U (en) | 2013-08-21 |
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| CN 201220693844 Expired - Fee Related CN203151466U (en) | 2012-12-14 | 2012-12-14 | Positive-negative logic level conversion switching circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066986A (en) * | 2012-12-14 | 2013-04-24 | 深圳市新国都技术股份有限公司 | Positive-negative logic level conversion switching circuit |
| CN115878539A (en) * | 2023-01-31 | 2023-03-31 | 北京智芯微电子科技有限公司 | Serial port self-adaptive circuit, electronic equipment and circuit board |
-
2012
- 2012-12-14 CN CN 201220693844 patent/CN203151466U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066986A (en) * | 2012-12-14 | 2013-04-24 | 深圳市新国都技术股份有限公司 | Positive-negative logic level conversion switching circuit |
| CN115878539A (en) * | 2023-01-31 | 2023-03-31 | 北京智芯微电子科技有限公司 | Serial port self-adaptive circuit, electronic equipment and circuit board |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130821 Termination date: 20191214 |