CN105471420A - Differential I2C bus communication interface circuit - Google Patents
Differential I2C bus communication interface circuit Download PDFInfo
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- CN105471420A CN105471420A CN201410423409.4A CN201410423409A CN105471420A CN 105471420 A CN105471420 A CN 105471420A CN 201410423409 A CN201410423409 A CN 201410423409A CN 105471420 A CN105471420 A CN 105471420A
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Abstract
The invention discloses a differential I2C bus communication interface circuit which comprises a data signal receiving/transmitting conversion module, a differential data signal transmission module, a clock signal receiving/transmitting conversion module and a differential clock signal transmission module. The differential I2C bus communication interface circuit converts TTL levels of a serial clock SCL and serial data SDA into differential signals to transmit by utilizing two RS485 interface chips, thereby solving the problems of poor anti-interference capability and short communication distance during communication of a conventional I2C bus, improving the anti-interference capability of the circuit, and realizing the long-distance bidirectional transmission communication.
Description
Technical field
The present invention relates to communication interface circuit technical field, particularly a kind of difference I2C bus communication interface circuit.
Background technology
I2C bus communication is a kind of two-wire system bidirectional linked list synchronous communication mode with how main arbitration mechanism that philips company releases, because I2C bus mainly adopts Transistor-Transistor Logic level signal to transmit, and this telecommunication circuit not only poor anti jamming capability utilizing Transistor-Transistor Logic level signal to carry out transmitting, and the communication of short-range can only be realized, usually the communication within the scope of same circuit board is only applicable to, or the communication between plates within the scope of same equipment, but and the communication be not suitable between electronic equipment.
Summary of the invention
The object of the present invention is to provide a kind of difference I2C bus communication interface circuit, be intended to solution and adopt Transistor-Transistor Logic level signal to carry out the telecommunication circuit transmitted, its poor anti jamming capability, the problem that communication distance is short for existing I2C bus.
The present invention is achieved in that a kind of difference I2C bus communication interface circuit, comprise data-signal to receive/send out modular converter, differential data signals transport module, modular converter and differential clock signal transport module are received/sent out to clock signal;
Described data-signal is received/is sent out modular converter and holds for the SDA receiving local I2C the Transistor-Transistor Logic level signal that sends and transmit, or receive the Transistor-Transistor Logic level signal that sends from described differential data signals transport module and be transferred to the SDA end of local I2C, meanwhile, for controlling a receipts/enabled state of described differential data signals transport module;
Described differential data signals transport module is received/sends out Transistor-Transistor Logic level signal that modular converter sends for receiving described data-signal and send to distal end I 2C after converting differential data signals to, or receives differential data signals that distally I2C sends and be sent to described data-signal after converting Transistor-Transistor Logic level signal to and receive/send out modular converter;
Described clock signal is received/is sent out modular converter and holds for the SCL receiving local I2C the Transistor-Transistor Logic level signal that sends and transmit, or receive the Transistor-Transistor Logic level signal that sends from described differential clock signal transport module and be transferred to the SCL end of local I2C, meanwhile, for controlling a receipts/enabled state of described differential clock signal transport module;
Described differential clock signal transport module is received/sends out Transistor-Transistor Logic level signal that modular converter sends for receiving described clock signal and send to distal end I 2C after converting differential clock signal to, or receives differential data signals that distally I2C sends and be sent to described clock signal after converting Transistor-Transistor Logic level signal to and receive/send out modular converter.
Described data-signal is received/is sent out modular converter and comprises Two-state door U1, NOR gate U2A and NOR gate U2B, wherein, described Two-state door U1 output connects the SDA end of local I2C and the first input end of NOR gate U2A, and described Two-state door U1 input is connected to the output of NOR gate U2B and second input of NOR gate U2A, described differential data signals transport module comprises a RS485 transceiver U3, resistance R1, R7, R8 and electric capacity C3, the reception output R of a described RS485 transceiver U3 connects first input end and second input of described NOR gate U2B, receive Enable Pin RE and the output driving Enable Pin DE to be connected described NOR gate U2A, input D is driven to connect the first input end of described NOR gate U2A and the output of described Two-state door U1, one end that anode A connects described resistance R8 is received/sent out to difference, the other end of described resistance R8 is connected to the SDA_485A of a described RS485 transceiver U3 differential bus, one end that negative terminal B connects described resistance R7 is received/sent out to difference, the other end of described resistance R7 is connected to the SDA_485B of a described RS485 transceiver U3 differential bus, the power positive end VCC of a described RS485 transceiver U3 connects+5V power supply, negative terminal GND ground connection, between the reception output R that described resistance R1 is connected to a described RS485 transceiver U3 and power positive end, between the power positive end that described electric capacity C3 is connected to a described RS485 transceiver and power supply negative terminal.
Further, described differential data signals transport module comprises resistance R2, R11 and/or R5, wherein said resistance R2 is connected to the power positive end of a described RS485 transceiver U3 and difference is received/send out between anode A, described resistance R11 is connected between two differential bus of a described RS485 transceiver U3, and the difference that described resistance R5 is connected to a described RS485 transceiver U3 is received/sent out between negative terminal B and ground.
Described clock signal is received/is sent out modular converter and comprises Two-state door U5, NOR gate U2D and NOR gate U2C, wherein, described Two-state door U5 output connects the SCL end of local I2C and the first input end of NOR gate U2D, and described Two-state door U5 input is connected to the output of NOR gate U2C and second input of NOR gate U2D, described differential clock signal transport module comprises the 2nd RS485 transceiver U4, resistance R3, R9, R10 and electric capacity C4, the reception output R of described 2nd RS485 transceiver U4 connects first input end and second input of described NOR gate U2C, receive Enable Pin RE and the output driving Enable Pin DE to be connected described NOR gate U2D, input D is driven to connect the first input end of described NOR gate U2D and the output of described Two-state door U5, one end that anode A connects described resistance R10 is received/sent out to difference, the other end of described resistance R10 is connected to the SCL_485A of described 2nd RS485 transceiver U4 differential bus, one end that negative terminal B connects described resistance R9 is received/sent out to difference, the other end of described resistance R9 is connected to the SCL_485B of described 2nd RS485 transceiver U4 differential bus, the power positive end VCC of described 2nd RS485 transceiver U4 connects+5V power supply, negative terminal GND ground connection, between the reception output R that described resistance R3 is connected to described 2nd RS485 transceiver U4 and power positive end, between the power positive end that described electric capacity C4 is connected to described 2nd RS485 transceiver and power supply negative terminal.
Further, described differential clock signal transport module comprises resistance R4, R12 and/or R6, wherein said resistance R4 is connected to the power positive end of described 2nd RS485 transceiver U4 and difference is received/send out between anode A, described resistance R12 is connected between two differential bus of described 2nd RS485 transceiver U4, and the difference that described resistance R6 is connected to described 2nd RS485 transceiver U4 is received/sent out between negative terminal B and ground.
Further, described differential data signals transport module is connected with electric capacity C2 by electric capacity C1 with differential clock signal transport module, and described electric capacity C1 and electric capacity C2 is connected respectively between the power supply negative terminal of described differential data signals transport module and the power positive end of described differential clock signal transport module.
Described data-signal is received/is sent out modular converter and comprises triode Q1, diode D1, metal-oxide-semiconductor Q2, resistance R21 and R24, wherein, the collector electrode of described triode Q1 connects local SDA and holds and described resistance R24 one end, the other end of described resistance R24 connects the grid of described metal-oxide-semiconductor Q2, the source ground of described metal-oxide-semiconductor Q2, the drain electrode of described metal-oxide-semiconductor Q2 connects the anode of described diode D1, the negative electrode of described diode D1 connects the emitter of described triode Q1, the base stage of described triode Q1 connects one end of described resistance R21, the other end of described resistance R21 connects+5V power supply, described differential data signals transport module comprises a RS485 transceiver U21, resistance R22, R32, R33 and electric capacity C21, the reception output R of a described RS485 transceiver U21 connects the emitter of described triode Q1 and the negative electrode of described diode D1, receive Enable Pin RE and be connected one end of described resistance R22 and the drain electrode of described metal-oxide-semiconductor Q2 with driving Enable Pin DE, input D is driven to connect the collector electrode of described triode Q1, one end that anode A connects described resistance R33 is received/sent out to difference, the other end of described resistance R33 is connected to the SDA_485A of a described RS485 transceiver U21 differential bus, one end that negative terminal B connects described resistance R32 is received/sent out to difference, the other end of described resistance R32 is connected to the SDA_485B of a described RS485 transceiver U21 differential bus, the power positive end VCC of a described RS485 transceiver U21 connects+5V power supply, negative terminal GND ground connection, the other end of described resistance R22 connects+5V power supply, described electric capacity C21 is connected between+5V VDD-to-VSS.
Further, described differential data signals transport module comprises resistance R23, R31 and/or R37, wherein, the difference that described resistance R23 is connected to a described RS485 transceiver U21 is received/sends out between anode A and+5V power supply, described resistance R31 is connected between two differential bus of a described RS485 transceiver U21, and the difference that described resistance R37 is connected to a described RS485 transceiver U21 is received/sent out between negative terminal B and ground.
Described clock signal is received/is sent out modular converter and comprises triode Q3, diode D2, metal-oxide-semiconductor Q4, resistance R25 and R28, wherein, the collector electrode of described triode Q3 connects local SCL and holds and described resistance R28 one end, the other end of described resistance R28 connects the grid of described metal-oxide-semiconductor Q4, the source ground of described metal-oxide-semiconductor Q4, the drain electrode of described metal-oxide-semiconductor Q4 connects the anode of described diode D2, the negative electrode of described diode D2 connects the emitter of described triode Q3, the base stage of described triode Q3 connects one end of described resistance R25, the other end of described resistance R25 connects+5V power supply, described differential clock signal transport module comprises the 2nd RS485 transceiver U22, resistance R26, R35, R36 and electric capacity C22, the reception output R of described 2nd RS485 transceiver U22 connects the emitter of described triode Q3 and the negative electrode of described diode D2, receive Enable Pin RE and be connected one end of described resistance R26 and the drain electrode of described metal-oxide-semiconductor Q4 with driving Enable Pin DE, input D is driven to connect the collector electrode of described triode Q3, one end that anode A connects described resistance R36 is received/sent out to difference, the other end of described resistance R36 is connected to the SCL_485A of described 2nd RS485 transceiver U22 differential bus, one end that negative terminal B connects described resistance R35 is received/sent out to difference, the other end of described resistance R35 is connected to the SCL_485B of described 2nd RS485 transceiver U22 differential bus, the power positive end VCC of described 2nd RS485 transceiver U22 connects+5V power supply, negative terminal GND ground connection, the other end of described resistance R26 connects+5V power supply, described electric capacity C22 is connected between+5V VDD-to-VSS.
Further, described differential clock signal transport module comprises resistance R27, R34 and/or R38, wherein, the difference that described resistance R27 is connected to described 2nd RS485 transceiver U22 is received/sends out between anode A and+5V power supply, described resistance R34 is connected between described 2nd RS485 transceiver U22 two differential bus, and the difference that described resistance R38 is connected to described 2nd RS485 transceiver U22 is received/sent out between negative terminal B and ground.
The invention has the beneficial effects as follows: compared with prior art, the Transistor-Transistor Logic level of serial clock SCL and serial data SDA is converted to differential signal transmission by utilizing two RS485 interface chips by difference I2C bus communication interface circuit of the present invention, the problem that poor anti jamming capability when solving existing I2C bus communication, communication distance are short, improve the antijamming capability of circuit, achieve remote two-way communication.
Accompanying drawing explanation
Fig. 1 is the module frame chart of the first embodiment of a kind of difference I2C bus communication interface circuit provided by the invention;
Fig. 2 is the circuit theory diagrams of the second embodiment of difference I2C bus communication interface circuit provided by the invention;
Fig. 3 is the circuit theory diagrams of the 3rd embodiment of difference I2C bus communication interface circuit provided by the invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Be illustrated in figure 1 the module frame chart of the first embodiment of a kind of difference I2C bus communication interface circuit provided by the invention, difference I2C bus communication interface circuit provided by the invention comprises data-signal and receives/send out modular converter 1, differential data signals transport module 2, modular converter 3 and differential clock signal transport module 4 are received/sent out to clock signal;
Data-signal is received/is sent out modular converter 1 and holds for the SDA receiving local I2C the Transistor-Transistor Logic level signal that sends and transmit, or receive from differential data signals transport module 2 send Transistor-Transistor Logic level signal and be transferred to local I2C SDA end, meanwhile, for controlling a receipts/enabled state of differential data signals transport module 2;
Differential data signals transport module 2 is for the Transistor-Transistor Logic level signal that receives data-signal and receive/send out modular converter 1 and send and send to distal end I 2C after converting differential data signals to, or receives differential data signals that distally I2C sends and be sent to data-signal after converting Transistor-Transistor Logic level signal to and receive/send out modular converter 1;
Clock signal is received/is sent out modular converter 3 and holds for the SCL receiving local I2C the Transistor-Transistor Logic level signal that sends and transmit, or receive from differential clock signal transport module 4 send Transistor-Transistor Logic level signal and be transferred to local I2C SCL end, meanwhile, for controlling a receipts/enabled state of differential clock signal transport module 4;
Differential clock signal transport module 4 is received/is sent out for receive clock signal Transistor-Transistor Logic level signal that modular converter 3 sends and sends to distal end I 2C after converting differential clock signal to, or receives differential data signals that distally I2C sends and be sent to clock signal after converting Transistor-Transistor Logic level signal to and receive/send out modular converter 3.
Fig. 2 is the circuit theory diagrams of the second embodiment of difference I2C bus communication interface circuit provided by the invention, the data-signal of this circuit is received/is sent out modular converter 1 and comprises Two-state door U1, NOR gate U2A and NOR gate U2B, wherein, Two-state door U1 output connects the SDA end of local I2C and the first input end of NOR gate U2A, and Two-state door U1 input is connected to the output of NOR gate U2B and second input of NOR gate U2A, differential data signals transport module 2 comprises a RS485 transceiver U3, resistance R1, R7, R8 and electric capacity C3, the reception output R of the one RS485 transceiver U3 connects first input end and second input of NOR gate U2B, receive Enable Pin RE and the output driving Enable Pin DE to be connected NOR gate U2A, input D is driven to connect the first input end of NOR gate U2A and the output of Two-state door U1, one end of anode A contact resistance R8 is received/sent out to difference, the other end of resistance R8 is connected to the SDA_485A of a RS485 transceiver U3 differential bus, one end of negative terminal B contact resistance R7 is received/sent out to difference, the other end of resistance R7 is connected to the SDA_485B of a RS485 transceiver U3 differential bus, the power positive end VCC of the one RS485 transceiver U3 connects+5V power supply, negative terminal GND ground connection, between the reception output R that resistance R1 is connected to a RS485 transceiver U3 and power positive end, between the power positive end that electric capacity C3 is connected to a RS485 transceiver and power supply negative terminal.
Differential data signals transport module 2 comprises resistance R2, R11 and/or R5 further, wherein resistance R2 is connected to the power positive end of a RS485 transceiver U3 and difference is received/send out between anode A, resistance R11 is connected between two differential bus of a RS485 transceiver U3, and the difference that resistance R5 is connected to a RS485 transceiver U3 is received/sent out between negative terminal B and ground.
Clock signal is received/is sent out modular converter 3 and comprises Two-state door U5, NOR gate U2D and NOR gate U2C, wherein, Two-state door U5 output connects the SCL end of local I2C and the first input end of NOR gate U2D, and Two-state door U5 input is connected to the output of NOR gate U2C and second input of NOR gate U2D, differential clock signal transport module 4 comprises the 2nd RS485 transceiver U4, resistance R3, R9, R10 and electric capacity C4, the reception output R of the 2nd RS485 transceiver U4 connects first input end and second input of NOR gate U2C, receive Enable Pin RE and the output driving Enable Pin DE to be connected NOR gate U2D, input D is driven to connect the first input end of NOR gate U2D and the output of Two-state door U5, one end of anode A contact resistance R10 is received/sent out to difference, the other end of resistance R10 is connected to the SCL_485A of the 2nd RS485 transceiver U4 differential bus, one end of negative terminal B contact resistance R9 is received/sent out to difference, the other end of resistance R9 is connected to the SCL_485B of the 2nd RS485 transceiver U4 differential bus, the power positive end VCC of the 2nd RS485 transceiver U4 connects+5V power supply, negative terminal GND ground connection, between the reception output R that resistance R3 is connected to the 2nd RS485 transceiver U4 and power positive end, between the power positive end that electric capacity C4 is connected to the 2nd RS485 transceiver and power supply negative terminal.
Differential clock signal transport module 4 comprises resistance R4, R12 and/or R6 further, wherein resistance R4 is connected to the power positive end of the 2nd RS485 transceiver U4 and difference is received/send out between anode A, resistance R12 is connected between two differential bus of the 2nd RS485 transceiver U4, and the difference that resistance R6 is connected to the 2nd RS485 transceiver U4 is received/sent out between negative terminal B and ground.
Above-mentioned differential data signals transport module 2 is connected with electric capacity C2 by electric capacity C1 with differential clock signal transport module 4, and electric capacity C1 and electric capacity C2 is connected respectively between the power supply negative terminal of differential data signals transport module 2 and the power positive end of differential clock signal transport module 4.
In the embodiment of the present invention, when the data wire SDA of local I2C does not have low level to send, SDA is high level, and the output SDA_DE of NOR gate U2A is low level, and therefore, RS485 chip U3 is in reception data mode.When the data wire SDA of distal end I 2C sends low level signal, SDA_485A is lower than SDA_485B, SDA_RXD is then low level, the output of NOR gate U2B is high level, the output SDA_DE of NOR gate U2A keeps low level, RS485 chip U3 keeps accepting state, and the output SDA of Two-state door U1 is low level, then the low level that the data wire SDA that the data wire SDA of local I2C receives distal end I 2C sends.When the data wire SDA of distal end I 2C sends high level, SDA_485A is higher than SDA_485B, SDA_RXD is then high level, the output of NOR gate U2B is low level, the output SDA of U1 is high-impedance state, and because the pull-up resistor R13 in SDA bus ensures high level, the output SDA_DE of NOR gate U2A still keeps low level, RS485 chip U3 still keeps accepting state, then the high level that the data wire SDA that local I2C data wire SDA receives distal end I 2C sends.
When the data wire SDA of local I2C has low level to send, SDA is low level, SDA_RXD is high level, and the output of NOR gate U2B is low level, and two inputs of NOR gate U2A are low level, it exports SDA_DE is high level, therefore, RS485 chip U3 is in transmission state, then RS485 chip U3 sends low level and makes SDA_485A ground connection, SDA_485B meets+5V, and the data wire SDA of distal end I 2C just receives the low level of the data wire SDA transmission of local I2C.
When the data wire SDA of local I2C and the data wire SDA of distal end I 2C is low level simultaneously, the reiving/transmitting state of RS485 chip is the state depending on eve, its follow-up receipts/hair-like state then depend on the data wire SDA of local I2C and distal end I 2C data wire SDA which side first cancel low level and transfer high level to, if the data wire SDA of local I2C first transfers high level to, so, the output SDA_DE of NOR gate U2A is low level, therefore, RS485 chip U3 is in accepting state, and the data wire SDA of local I2C receives the low level of the SDA of distal end I 2C data wire.Otherwise, if the data wire SDA of distal end I 2C first transfers high level to, receipts/hair-like the state of distal end I 2C then transfers accepting state to, if RS485 chip U3 is in accepting state this moment, SDA_RXD is high level, the output of NOR gate U2B is low level, two of NOR gate U2A is input as low level, then exporting SDA_DE is high level, therefore, RS485 chip U3 is in transmission state, if RS485 chip U3 is in transmission state this moment, then keep transmission state, what the data wire SDA of distal end I 2C then received is low level.
In the embodiment of the present invention, when the clock line SCL of local I2C does not have low level to send, SCL is high level, and the output SCL_DE of NOR gate U2D is low level, and therefore, RS485 chip U4 is in reception data mode.When the clock line SCL of distal end I 2C sends low level signal, SCL_485A is lower than SCL_485B, SCL_RXD is then low level, the output of NOR gate U2C is high level, the output SCL_DE of NOR gate U2D keeps low level, and therefore, RS485 chip U4 keeps accepting state, the output SCL of Two-state door U5 is low level, then the low level that the clock line SCL that the clock line SCL of local I2C receives distal end I 2C sends.When the clock line SCL of distal end I 2C sends high level, SCL_485A is higher than SCL_485B, SCL_RXD is then high level, the output of NOR gate U2C is low level, and the output SCL of U5 is high-impedance state, because the pull-up resistor R14 in SCL bus ensures high level, the output SCL_DE of NOR gate U2D still keeps low level, therefore, RS485 chip U4 still keeps accepting state, then the high level that the clock line SCL that local I2C clock line SCL receives distal end I 2C sends.
When the clock line SCL of local I2C has low level to send, SCL is low level, SCL_RXD is high level, and the output of NOR gate U2C is low level, and two inputs of NOR gate U2D are low level, it exports SCL_DE is high level, therefore, RS485 chip U4 is in transmission state, then RS485 chip U4 sends low level and makes SCL_485A ground connection, SCL_485B meets+5V, and the clock line SCL of distal end I 2C just receives the low level of the clock line SCL transmission of local I2C.
When the clock line SCL of local I2C and the clock line SSCL of distal end I 2C is low level simultaneously, the reiving/transmitting state of RS485 chip U4 is the state depending on eve, its follow-up receipts/hair-like state depend on the clock line SCL of local I2C and distal end I 2C clock line SCL which side first cancel low level and transfer high level to, if the clock line SCL of local I2C first transfers high level to, so, the output SCL_DE of NOR gate U2D is low level, therefore, RS485 chip U4 is in accepting state, the low level that the clock line SCL that the clock line SCL of local I2C receives distal end I 2C sends.Otherwise, if the clock line SCL of distal end I 2C first transfers high level to, receipts/hair-like the state of distal end I 2C then transfers accepting state to, if RS485 chip U4 is in accepting state this moment, SLC_RXD is high level, NOR gate U2C output low level, two inputs of NOR gate U2D are all low level, it exports SCL_DE is high level, and therefore, RS485 chip U4 is in transmission state; If RS485 chip U4 is in transmission state this moment, then keep transmission state, the clock line SCL of distal end I 2C then receives the low level of the clock line SCL transmission of local I2C.
Fig. 3 is the circuit theory diagrams of the 3rd embodiment of difference I2C bus communication interface circuit provided by the invention, the data-signal of this circuit is received/is sent out modular converter 1 and comprises triode Q1, diode D1, metal-oxide-semiconductor Q2, resistance R21 and R24, wherein, the collector electrode of triode Q1 connects local SDA and holds and resistance R24 one end, the other end of resistance R24 connects the grid of metal-oxide-semiconductor Q2, the source ground of metal-oxide-semiconductor Q2, the drain electrode of metal-oxide-semiconductor Q2 connects the anode of diode D1, the emitter of the negative electrode connecting triode Q1 of diode D1, one end of the base stage contact resistance R21 of triode Q1, the other end of resistance R21 connects+5V power supply, differential data signals transport module 2 comprises a RS485 transceiver U21, resistance R22, R32, R33 and electric capacity C21, the emitter of reception output R connecting triode Q1 of the one RS485 transceiver U21 and the negative electrode of diode D1, receive Enable Pin RE and drive one end of Enable Pin DE contact resistance R22 and the drain electrode of metal-oxide-semiconductor Q2, drive the collector electrode of input D connecting triode Q1, one end of anode A contact resistance R33 is received/sent out to difference, the other end of resistance R33 is connected to the SDA_485A of a RS485 transceiver U21 differential bus, one end of negative terminal B contact resistance R32 is received/sent out to difference, the other end of resistance R32 is connected to the SDA_485B of a RS485 transceiver U21 differential bus, the power positive end VCC of the one RS485 transceiver U21 connects+5V power supply, negative terminal GND ground connection, the other end of resistance R22 connects+5V power supply, electric capacity C21 is connected between+5V VDD-to-VSS.
Differential data signals transport module 2 comprises resistance R23, R31 and/or R37 further, wherein, the difference that resistance R23 is connected to a RS485 transceiver U21 is received/sends out between anode A and+5V power supply, resistance R31 is connected between two differential bus of a RS485 transceiver U21, and the difference that resistance R37 is connected to a RS485 transceiver U21 is received/sent out between negative terminal B and ground.
Clock signal is received/is sent out modular converter 3 and comprises triode Q3, diode D2, metal-oxide-semiconductor Q4, resistance R25 and R28, wherein, the collector electrode of triode Q3 connects local SCL and holds and resistance R28 one end, and the other end of resistance R28 connects the grid of metal-oxide-semiconductor Q4, the source ground of metal-oxide-semiconductor Q4, the drain electrode of metal-oxide-semiconductor Q4 connects the anode of diode D2, the emitter of the negative electrode connecting triode Q3 of diode D2, one end of the base stage contact resistance R25 of triode Q3, the other end of resistance R25 connects+5V power supply, differential clock signal transport module 4 comprises the 2nd RS485 transceiver U22, resistance R26, R35, R36 and electric capacity C22, the emitter of reception output R connecting triode Q3 of the 2nd RS485 transceiver U22 and the negative electrode of diode D2, receive Enable Pin RE and drive one end of Enable Pin DE contact resistance R26 and the drain electrode of metal-oxide-semiconductor Q4, drive the collector electrode of input D connecting triode Q3, one end of anode A contact resistance R36 is received/sent out to difference, the other end of resistance R36 is connected to the SCL_485A of the 2nd RS485 transceiver U22 differential bus, one end of negative terminal B contact resistance R35 is received/sent out to difference, the other end of resistance R35 is connected to the SCL_485B of the 2nd RS485 transceiver U22 differential bus, the power positive end VCC of the 2nd RS485 transceiver U22 connects+5V power supply, negative terminal GND ground connection, the other end of resistance R26 connects+5V power supply, electric capacity C22 is connected between+5V VDD-to-VSS.
Differential clock signal transport module 4 comprises resistance R27, R34 and/or R38 further, wherein, the difference that resistance R27 is connected to the 2nd RS485 transceiver U22 is received/sends out between anode A and+5V power supply, resistance R34 is connected between the 2nd RS485 transceiver U22 two differential bus, and the difference that resistance R38 is connected to the 2nd RS485 transceiver U22 is received/sent out between negative terminal B and ground.
In the embodiment of the present invention, when the data wire SDA of local I2C does not have low level to send, SDA is high level, and it is low level that the drain electrode of metal-oxide-semiconductor Q2 exports SDA_DE, and therefore, RS485 chip U21 is in reception data mode.When the data wire SDA of distal end I 2C sends low level signal, SDA_485A is lower than SDA_485B, SDA_RXD is then low level, diode D1 keeps SDA_DE to be low level, RS485 chip U21 keeps accepting state, it is low level that the collector electrode of triode Q1 exports SDA, then the low level that the data wire SDA that the data wire SDA of local I2C receives distal end I 2C sends.When the data wire SDA of distal end I 2C sends high level, SDA_485A is higher than SDA_485B, SDA_RXD is then high level, it is high-impedance state that the collector electrode of triode Q1 exports SDA, because the pull-up resistor R30 in SDA bus ensures high level, the output SDA_DE of metal-oxide-semiconductor Q2 still keeps low level, and RS485 chip U21 still keeps accepting state, then the high level that the data wire SDA that local I2C data wire SDA receives distal end I 2C sends.
When the data wire SDA of local I2C has low level to send, SDA is low level, it is high level that the drain electrode of metal-oxide-semiconductor Q2 exports SDA_DE, therefore, RS485 chip U21 is in transmission state, then RS485 chip U21 sends low level and makes SDA_485A ground connection, and SDA_485B meets+5V, and the data wire SDA of distal end I 2C just receives the low level of the data wire SDA transmission of local I2C.
When the data wire SDA of local I2C and the data wire SDA of distal end I 2C is low level simultaneously, receipts/hair-like the state of RS485 chip U21 depends on the receipts/transmission state of eve, its follow-up receipts/hair-like state then depend on the data wire SDA of local I2C and distal end I 2C data wire SDA which side first cancel low level and transfer high level to, if the data wire SDA of local I2C first transfers high level to, so, it is low level that the drain electrode of metal-oxide-semiconductor Q2 exports SDA_DE, therefore, RS485 chip U21 place and accepting state, the data wire SDA of local I2C receives the low level of the SDA of distal end I 2C data wire.Otherwise if the data wire SDA of distal end I 2C first transfers high level to, the data wire SDA of the I2C of far-end transfers accepting state to, if U21 is accepting state this moment, so SDA_RXD is high level, and the drain electrode of metal-oxide-semiconductor Q2 exports as high level, therefore, RS485 chip U21 is still in transmission state; If be transmission state this moment, so, keep transmission state, what the data wire SDA of distal end I 2C then received is low level.
In the embodiment of the present invention, when the clock line SCL of local I2C does not have low level to send, SCL is high level, and it is low level that the drain electrode of metal-oxide-semiconductor Q4 exports SCL_DE, and therefore, RS485 chip U22 is in reception data mode.When the clock line SCL of distal end I 2C sends low level signal, SCL_485A is lower than SCL_485B, SCL_RXD is then low level, diode D2 keeps SCL_DE to keep low level, therefore, RS485 chip U22 keeps accepting state, and it is low level that the collector electrode of triode Q3 exports SCL, then the low level that the clock line SCL that the clock line SCL of local I2C receives distal end I 2C sends.When the clock line SCL of distal end I 2C sends high level, SCL_485A is higher than SCL_485B, SCL_RXD is then high level, it is high-impedance state that the collector electrode of triode Q3 exports SCL, because the pull-up resistor R29 in SCL bus ensures high level, the drain electrode of metal-oxide-semiconductor Q4 exports SCL_DE and still keeps low level, therefore, RS485 chip U22 still keeps accepting state, then the high level that the clock line SCL that local I2C clock line SCL receives distal end I 2C sends.
When the clock line SCL of local I2C has low level to send, SCL is low level, it is high level that the drain electrode of metal-oxide-semiconductor Q4 exports SCL_DE, therefore, RS485 chip U22 is in transmission state, then RS485 chip U22 sends low level and makes SCL_485A ground connection, and SCL_485B meets+5V, and the clock line SCL of distal end I 2C just receives the low level of the clock line SCL transmission of local I2C.
When the clock line SCL of local I2C and the clock line SCL of distal end I 2C is low level simultaneously, receipts/hair-like the state of RS485 chip U22 depends on the state of eve, its follow-up receipts/hair-like state depend on the clock line SCL of local I2C and distal end I 2C clock line SCL which side first cancel low level and transfer high level to, if the clock line SCL of local I2C first transfers high level to, so, it is low level that the drain electrode of metal-oxide-semiconductor Q4 exports SCL_DE, therefore, RS485 chip U22 is in accepting state, the low level that the clock line SCL that the clock line SCL of local I2C receives distal end I 2C sends.Otherwise, if the clock line SCL of distal end I 2C first transfers high level to, if RS485 is accepting state this moment, so, SLC_RXD keeps high level, and it is high level that the drain electrode of metal-oxide-semiconductor Q4 exports SCL_DE, therefore, RS485 chip U22 keeps transmission state, and the RS485 of distal end I 2C then transfers accepting state to, and the clock line SCL of distal end I 2C then receives the low level of the clock line SCL transmission of local I2C.
Present invention ensures that clock signal retention wire and the relation of the data-signal of local I2C and the data-signal retention wire of distal end I 2C and relation, the clock signal also guaranteeing local I2C and distal end I 2C, so also just remain how main arbitration relation, thus ensure that difference I2C bus communication also can be applicable to multi-host communication.
The Transistor-Transistor Logic level of serial clock SCL and serial data SDA is converted to differential signal transmission by utilizing two RS485 interface chips by difference I2C bus communication interface circuit of the present invention, the problem that poor anti jamming capability when solving existing I2C bus communication, communication distance are short, improve the antijamming capability of circuit, achieve remote two-way communication.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to technical spirit of the present invention, within the spirit and principles in the present invention, to any simple amendment that above embodiment is done, equivalent replacement and improvement etc., within the protection range all still belonging to technical solution of the present invention.
Claims (10)
1. a difference I2C bus communication interface circuit, is characterized in that: comprise data-signal to receive/send out modular converter, differential data signals transport module, modular converter and differential clock signal transport module are received/sent out to clock signal;
Described data-signal is received/is sent out modular converter and holds for the SDA receiving local I2C the Transistor-Transistor Logic level signal that sends and transmit, or receive the Transistor-Transistor Logic level signal that sends from described differential data signals transport module and be transferred to the SDA end of local I2C, meanwhile, for controlling a receipts/enabled state of described differential data signals transport module;
Described differential data signals transport module is received/sends out Transistor-Transistor Logic level signal that modular converter sends for receiving described data-signal and send to distal end I 2C after converting differential data signals to, or receives differential data signals that distally I2C sends and be sent to described data-signal after converting Transistor-Transistor Logic level signal to and receive/send out modular converter;
Described clock signal is received/is sent out modular converter and holds for the SCL receiving local I2C the Transistor-Transistor Logic level signal that sends and transmit, or receive the Transistor-Transistor Logic level signal that sends from described differential clock signal transport module and be transferred to the SCL end of local I2C, meanwhile, for controlling a receipts/enabled state of described differential clock signal transport module;
Described differential clock signal transport module is received/sends out Transistor-Transistor Logic level signal that modular converter sends for receiving described clock signal and send to distal end I 2C after converting differential clock signal to, or receives differential data signals that distally I2C sends and be sent to described clock signal after converting Transistor-Transistor Logic level signal to and receive/send out modular converter.
2. difference I2C bus communication interface circuit according to claim 1, it is characterized in that: described data-signal is received/sent out modular converter and comprises Two-state door U1, NOR gate U2A and NOR gate U2B, wherein, described Two-state door U1 output connects the SDA end of local I2C and the first input end of NOR gate U2A, and described Two-state door U1 input is connected to the output of NOR gate U2B and second input of NOR gate U2A, described differential data signals transport module comprises a RS485 transceiver U3, resistance R1, R7, R8 and electric capacity C3, the reception output R of a described RS485 transceiver U3 connects first input end and second input of described NOR gate U2B, receive Enable Pin RE and the output driving Enable Pin DE to be connected described NOR gate U2A, input D is driven to connect the first input end of described NOR gate U2A and the output of described Two-state door U1, one end that anode A connects described resistance R8 is received/sent out to difference, the other end of described resistance R8 is connected to the SDA_485A of a described RS485 transceiver U3 differential bus, one end that negative terminal B connects described resistance R7 is received/sent out to difference, the other end of described resistance R7 is connected to the SDA_485B of a described RS485 transceiver U3 differential bus, the power positive end VCC of a described RS485 transceiver U3 connects+5V power supply, negative terminal GND ground connection, between the reception output R that described resistance R1 is connected to a described RS485 transceiver U3 and power positive end, between the power positive end that described electric capacity C3 is connected to a described RS485 transceiver and power supply negative terminal.
3. difference I2C bus communication interface circuit according to claim 2, it is characterized in that: described differential data signals transport module comprises resistance R2, R11 and/or R5 further, wherein said resistance R2 is connected to the power positive end of a described RS485 transceiver U3 and difference is received/send out between anode A, described resistance R11 is connected between two differential bus of a described RS485 transceiver U3, and the difference that described resistance R5 is connected to a described RS485 transceiver U3 is received/sent out between negative terminal B and ground.
4. difference I2C bus communication interface circuit according to claim 1, it is characterized in that: described clock signal is received/sent out modular converter and comprises Two-state door U5, NOR gate U2D and NOR gate U2C, wherein, described Two-state door U5 output connects the SCL end of local I2C and the first input end of NOR gate U2D, and described Two-state door U5 input is connected to the output of NOR gate U2C and second input of NOR gate U2D, described differential clock signal transport module comprises the 2nd RS485 transceiver U4, resistance R3, R9, R10 and electric capacity C4, the reception output R of described 2nd RS485 transceiver U4 connects first input end and second input of described NOR gate U2C, receive Enable Pin RE and the output driving Enable Pin DE to be connected described NOR gate U2D, input D is driven to connect the first input end of described NOR gate U2D and the output of described Two-state door U5, one end that anode A connects described resistance R10 is received/sent out to difference, the other end of described resistance R10 is connected to the SCL_485A of described 2nd RS485 transceiver U4 differential bus, one end that negative terminal B connects described resistance R9 is received/sent out to difference, the other end of described resistance R9 is connected to the SCL_485B of described 2nd RS485 transceiver U4 differential bus, the power positive end VCC of described 2nd RS485 transceiver U4 connects+5V power supply, negative terminal GND ground connection, between the reception output R that described resistance R3 is connected to described 2nd RS485 transceiver U4 and power positive end, between the power positive end that described electric capacity C4 is connected to described 2nd RS485 transceiver and power supply negative terminal.
5. difference I2C bus communication interface circuit according to claim 4, it is characterized in that: described differential clock signal transport module comprises resistance R4, R12 and/or R6 further, wherein said resistance R4 is connected to the power positive end of described 2nd RS485 transceiver U4 and difference is received/send out between anode A, described resistance R12 is connected between two differential bus of described 2nd RS485 transceiver U4, and the difference that described resistance R6 is connected to described 2nd RS485 transceiver U4 is received/sent out between negative terminal B and ground.
6. the difference I2C bus communication interface circuit according to claim 3 or 5, it is characterized in that: described differential data signals transport module is connected with electric capacity C2 by electric capacity C1 with differential clock signal transport module, described electric capacity C1 and electric capacity C2 is connected respectively between the power supply negative terminal of described differential data signals transport module and the power positive end of described differential clock signal transport module.
7. difference I2C bus communication interface circuit according to claim 1, it is characterized in that: described data-signal is received/sent out modular converter and comprises triode Q1, diode D1, metal-oxide-semiconductor Q2, resistance R21 and R24, wherein, the collector electrode of described triode Q1 connects local SDA and holds and described resistance R24 one end, the other end of described resistance R24 connects the grid of described metal-oxide-semiconductor Q2, the source ground of described metal-oxide-semiconductor Q2, the drain electrode of described metal-oxide-semiconductor Q2 connects the anode of described diode D1, the negative electrode of described diode D1 connects the emitter of described triode Q1, the base stage of described triode Q1 connects one end of described resistance R21, the other end of described resistance R21 connects+5V power supply, described differential data signals transport module comprises a RS485 transceiver U21, resistance R22, R32, R33 and electric capacity C21, the reception output R of a described RS485 transceiver U21 connects the emitter of described triode Q1 and the negative electrode of described diode D1, receive Enable Pin RE and be connected one end of described resistance R22 and the drain electrode of described metal-oxide-semiconductor Q2 with driving Enable Pin DE, input D is driven to connect the collector electrode of described triode Q1, one end that anode A connects described resistance R33 is received/sent out to difference, the other end of described resistance R33 is connected to the SDA_485A of a described RS485 transceiver U21 differential bus, one end that negative terminal B connects described resistance R32 is received/sent out to difference, the other end of described resistance R32 is connected to the SDA_485B of a described RS485 transceiver U21 differential bus, the power positive end VCC of a described RS485 transceiver U21 connects+5V power supply, negative terminal GND ground connection, the other end of described resistance R22 connects+5V power supply, described electric capacity C21 is connected between+5V VDD-to-VSS.
8. difference I2C bus communication interface circuit according to claim 7, it is characterized in that: described differential data signals transport module comprises resistance R23, R31 and/or R37 further, wherein, the difference that described resistance R23 is connected to a described RS485 transceiver U21 is received/sends out between anode A and+5V power supply, described resistance R31 is connected between two differential bus of a described RS485 transceiver U21, and the difference that described resistance R37 is connected to a described RS485 transceiver U21 is received/sent out between negative terminal B and ground.
9. difference I2C bus communication interface circuit according to claim 1, it is characterized in that: described clock signal is received/sent out modular converter and comprises triode Q3, diode D2, metal-oxide-semiconductor Q4, resistance R25 and R28, wherein, the collector electrode of described triode Q3 connects local SCL and holds and described resistance R28 one end, the other end of described resistance R28 connects the grid of described metal-oxide-semiconductor Q4, the source ground of described metal-oxide-semiconductor Q4, the drain electrode of described metal-oxide-semiconductor Q4 connects the anode of described diode D2, the negative electrode of described diode D2 connects the emitter of described triode Q3, the base stage of described triode Q3 connects one end of described resistance R25, the other end of described resistance R25 connects+5V power supply, described differential clock signal transport module comprises the 2nd RS485 transceiver U22, resistance R26, R35, R36 and electric capacity C22, the reception output R of described 2nd RS485 transceiver U22 connects the emitter of described triode Q3 and the negative electrode of described diode D2, receive Enable Pin RE and be connected one end of described resistance R26 and the drain electrode of described metal-oxide-semiconductor Q4 with driving Enable Pin DE, input D is driven to connect the collector electrode of described triode Q3, one end that anode A connects described resistance R36 is received/sent out to difference, the other end of described resistance R36 is connected to the SCL_485A of described 2nd RS485 transceiver U22 differential bus, one end that negative terminal B connects described resistance R35 is received/sent out to difference, the other end of described resistance R35 is connected to the SCL_485B of described 2nd RS485 transceiver U22 differential bus, the power positive end VCC of described 2nd RS485 transceiver U22 connects+5V power supply, negative terminal GND ground connection, the other end of described resistance R26 connects+5V power supply, described electric capacity C22 is connected between+5V VDD-to-VSS.
10. difference I2C bus communication interface circuit according to claim 9, it is characterized in that: described differential clock signal transport module comprises resistance R27, R34 and/or R38 further, wherein, the difference that described resistance R27 is connected to described 2nd RS485 transceiver U22 is received/sends out between anode A and+5V power supply, described resistance R34 is connected between described 2nd RS485 transceiver U22 two differential bus, and the difference that described resistance R38 is connected to described 2nd RS485 transceiver U22 is received/sent out between negative terminal B and ground.
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| CN108834267A (en) * | 2018-08-29 | 2018-11-16 | 华域视觉科技(上海)有限公司 | Flowing water taillight control circuit |
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| CN108092747A (en) * | 2018-01-09 | 2018-05-29 | 浙江立地信息科技有限公司 | Non line of sight wireless video transmission circuitry |
| CN108092747B (en) * | 2018-01-09 | 2024-02-06 | 浙江立地信息科技有限公司 | Circuit of non-line-of-sight wireless video transmission equipment |
| CN108834267A (en) * | 2018-08-29 | 2018-11-16 | 华域视觉科技(上海)有限公司 | Flowing water taillight control circuit |
| CN110224952A (en) * | 2019-06-21 | 2019-09-10 | 珠海格力智能装备有限公司 | The processing method and processing device and its processing circuit of signal transmission |
| CN110971228A (en) * | 2019-12-04 | 2020-04-07 | 成都锐成芯微科技股份有限公司 | High-speed clock driving circuit |
| CN110971228B (en) * | 2019-12-04 | 2022-08-02 | 成都锐成芯微科技股份有限公司 | High-speed clock driving circuit |
| CN111404504A (en) * | 2020-06-03 | 2020-07-10 | 广州天嵌计算机科技有限公司 | RS485 bus differential signal amplifier |
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| WO2024016916A1 (en) * | 2022-07-18 | 2024-01-25 | 江苏科技大学 | Long-distance serial wire debug interface circuit and signal transmission method |
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