CN203590181U - Audio frequency power amplifier starting charging circuit - Google Patents
Audio frequency power amplifier starting charging circuit Download PDFInfo
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- CN203590181U CN203590181U CN201320724988.7U CN201320724988U CN203590181U CN 203590181 U CN203590181 U CN 203590181U CN 201320724988 U CN201320724988 U CN 201320724988U CN 203590181 U CN203590181 U CN 203590181U
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Abstract
The utility model discloses an audio frequency power amplifier starting charging circuit. The circuit comprises a charging control module. The charging control module comprises a power supply, two comparators, a burst pulse module, a shifting register, two delay modules, three resistors and capacitors, a first inverter, three first conjunction gates, four constant current sources and nine switches. According to the utility model, rapid charging is carried out simultaneously on a bypass capacitor and an input blocking capacitor; and accurate charging is carried out on the input blocking capacitor with the voltage of the bypass capacitor as a reference; a starting time can be effectively reduced, and the voltage of the two capacitors can be accurately controlled; and thus the same anti-Pop-sound effects can be achieved under conditions of different peripheral circuits.
Description
Technical field
The utility model relates to integrated circuit (IC) design field, relates in particular to the circuit to capacitance and shunt capacitance charging in a kind of audio power amplifier start-up process.
Background technology
Audio frequency power amplifier is being switched to from resting state the process of normal operating conditions, due to the imbalance of input capacitance and shunt capacitance charging, can produce at output the signal of a transient state, and this signal performance is the Pop sound of people's ear audible.For fear of occurring Pop sound, existing technology is used a startup charging circuit to shunt capacitance quick charge when power amplifier start-up, uses a comparator to detect shunt capacitance voltage and whether reaches operating voltage, separately uses a counter to carry out timing, and duration is T.Input capacitance is by power amplifier itself, to control common mode circuit partly to charge.During charging, power amplifier keeps silent status, and after shunt capacitance charging finishes, counter starts timing, with etc. capacitance to be entered reach operating voltage.After rolling counters forward stops, cancellation is forbidden power stage, is entered normal operating conditions.
Yet there is defect in the startup charging circuit of prior art: because input capacitance can connect access chip pin after an input resistance.When charging, the voltage that die terminals detects and the actual electrical of electric capacity are pressed with certain difference.Prior art be by charging finish rear wait one fixedly duration T allow it reach operating voltage, but this voltage extent has larger difference with the difference of chip periphery circuit, voltage difference is larger, the time that reaches operating voltage is longer.Have the situation that this voltage difference still can be larger after the stand-by period, T finished, now this voltage difference is just outputed to loud speaker by power amplifier, forms Pop sound, thus the actual anti-Pop audio fruit of impact.This becomes the applicant and is devoted to the problem solving.
Summary of the invention
The purpose of this utility model is to overcome the defect of prior art and a kind of audio power amplifier start-up charging circuit is provided, can effectively reduce start-up time and the accurate voltage of controlling two electric capacity, thereby realize the effect that is issued to identical anti-Pop sound in different peripheral circuit situations.
The technical scheme that realizes above-mentioned purpose is:
An audio power amplifier start-up charging circuit, external resistance-capacitance network and the shunt capacitance being formed by non-essential resistance and input capacitance, described startup charging circuit comprises charge control module (101);
Described charge control module (101) comprises power supply, the first comparator (201), the second comparator (202), short pulse module (701), shift register (801), the first Postponement module (401), the second Postponement module (402), the first resistance (301), the second resistance (302), the 3rd resistance (303), electric capacity (403), the first inverter (601), first with door (602), second with door (603), the 3rd with door (604), the first continuous current source (901), the second continuous current source (902), the 3rd continuous current source (903) and the 4th continuous current source (904), and nine have two signal ends and a control end switch: the first switch (501), second switch (502), the 3rd switch (503), the 4th switch (504), the 5th switch (505), the 6th switch (506), minion is closed (507), the 8th switch (508) and the 9th switch (509), wherein:
Described the first resistance (301) one end connects described power supply, and the other end is by described the second resistance (302) ground connection; The common port output reference voltage Vref of described the first resistance (301) and the second resistance (302);
The end of oppisite phase of described the first comparator (201) connects the common port of described the first resistance (301) and the second resistance (302), positive terminal connects described shunt capacitance, output connect respectively the input of described the first inverter (601), the input of the input of the first Postponement module (401), the second Postponement module (402), the control end of the 3rd switch (503), minion close a control end of the control end of (507), the control end of the 8th switch (508) and the first comparator (201); Described the first comparator (201) receiving system reset signal Reset;
Described the first inverter (601) output connects respectively the control end of described the first switch (501) and the control end of second switch (502);
A signal end of described the first switch (501) connects described shunt capacitance, and another signal end connects described non-essential resistance;
A signal end of described second switch (502) connects described shunt capacitance, and another signal end connects the one end in described the first continuous current source (901), and the other end in the first continuous current source (901) connects described power supply;
A signal end of described the 3rd switch (503) connects described shunt capacitance, and another signal end connects the common port of described the first resistance (301) and the second resistance (302);
A control end of described the second comparator (202) connects the output of described the first Postponement module (401), the signal end that end of oppisite phase connects described the 8th switch (508) is connected, and another signal end of the 8th switch (508) connects described shunt capacitance; The positive terminal of described the second comparator (202) is connected with the signal end that described minion is closed (507), and another signal end that minion is closed (507) connects described non-essential resistance; The output of described the second comparator (202) is connected with the input of described short pulse module (701); Described the second comparator (202) receiving system reset signal Reset;
Described shift register (801) is containing three inputs and three outputs, an input connects the output of described short pulse module (701), an input connects the output of the second Postponement module (402), an input receiving system reset signal Reset;
The control end of described the 9th switch (509) connects the output of described short pulse module (701), and two signal ends of the 9th switch (509) are connected one by one with the two ends of described electric capacity (403); Described electric capacity (403) one end connects described power supply, other end ground connection by described the 3rd resistance (303);
Described first is connected with three outputs of described shift register (801) with door (604) input separately with the 3rd with door (603) one by one with door (602), second, and another input separately all connects the common port of described the 3rd resistance (303) and electric capacity (403);
The control end of described the 4th switch (504) connect described first with door (602) output, a signal end connects described non-essential resistance, another signal end connects the one end in described the second continuous current source (902), and the other end in the second continuous current source (902) connects described power supply;
The control end of described the 5th switch (505) connect described second with door (602) output, a signal end connects described non-essential resistance, another signal end connects the one end in described the 3rd continuous current source (903), and the other end in the 3rd continuous current source (903) connects described power supply;
The control end of described the 6th switch (506) connect the described the 3rd with door (603) output, a signal end connects described non-essential resistance, another signal end connects the one end in described the 4th continuous current source (904), and the other end in the 4th continuous current source (904) connects described power supply.
Above-mentioned audio power amplifier start-up charging circuit, wherein, when the input of described short pulse module (701) is translated into high level by low level, output one pulse signal, when input is translated into low level by high level, output does not change.
Above-mentioned audio power amplifier start-up charging circuit, wherein, described shift register (801) sequentially moves in three outputs by a logical zero when each rising edge of the pulse signal of described short pulse module (701) output.
Above-mentioned audio power amplifier start-up charging circuit, wherein, is less than the time of delay of described the second Postponement module (402) time of delay of described the first Postponement module (401).
Above-mentioned audio power amplifier start-up charging circuit, wherein, described the first continuous current source (901), the second continuous current source (902), the 3rd continuous current source (903) and the 4th continuous current source (904) charging current are separately respectively Ichr1, Ichr2, Ichr3 and Ichr4, Ichr2, Ichr3 and Ichr4 sum that Ichr1 is greater than 5 times, and Ichr2>=5
*ichr3>=5
*ichr4.
Above-mentioned audio power amplifier start-up charging circuit, wherein, described short pulse module (701) comprise the 4th with door (1001), second, third, the 4th inverter (1101,1102,1103) and the first direct-to-ground capacitance (1201), wherein:
The 4th is connected with the input of door one input of (1001) and the input of short pulse module (701) and the second inverter (1101), the output of the second inverter (1101) connects the input of the 3rd inverter (1102), the output of the 3rd inverter (1102) connects the input of the 4th inverter (1103) and one end of the first direct-to-ground capacitance (1201), the other end ground connection of the first direct-to-ground capacitance (1201).The output connection the 4th of the 4th inverter (1103) and another input of door (701); The 4th is connected the output of short pulse module (701) with the output of door (1001).
Above-mentioned audio power amplifier start-up charging circuit, wherein, described the first Postponement module (401) and the second Postponement module (402) include inverter and second direct-to-ground capacitance (1202) of n series connection, and n is even number; The end that joins of adjacent two inverters of one termination of the second direct-to-ground capacitance (1202), other end ground connection.
The beneficial effects of the utility model are: the utility model is by circuit structure simply, effectively and reasonably, in system charging process, realize successively quick charge and accurately charging, reduced the charging stand-by period, the charging current simultaneously reducing by substep reaches the object of accurate charging, thereby has buried in oblivion the pop sound in voice applications.And, because charging process does not rely on the fixedly latent period of duration, making when the peripheral capacitance applications of difference, system still can obtain consistent pop and suppress ability, has promoted the applicability of system.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of audio power amplifier start-up charging circuit of the present utility model;
Fig. 2 is the input-output wave shape figure of short pulse module;
Fig. 3 is the input-output wave shape figure of shift register;
Fig. 4 is a kind of concrete structure figure of the short-and-medium pulse module of the utility model;
Fig. 5 is a kind of concrete structure figure of Postponement module in the utility model;
Fig. 6 is the whole sequential chart of the operation principle of audio power amplifier start-up charging circuit of the present utility model;
Fig. 7 is the inside sequential chart of the short-and-medium pulse module of the utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
The utility model acts on resistance-capacitance network and the shunt capacitance Cbp of non-essential resistance Rin and input capacitance Cin composition, mainly divides two charging stages:
The quick charge stage, simultaneously to shunt capacitance Cbp and input capacitance Cin quick charge, specifically refer to: the resistance-capacitance network forming to shunt capacitance Cbp and non-essential resistance Rin and input capacitance Cin is exported a constant charge current Ichr1, and detect voltage Vchr1 on shunt capacitance Cbp and the difference of reference voltage V ref; When Vchr1 is greater than Vref, Vchr1 is fixed as to Vref, the constant charge current of breaking Ichr1, makes the voltage Vchr2 on resistance-capacitance network fall back to the real voltage of inputting capacitance Cin, enters next stage;
The accurate charging stage, the voltage of shunt capacitance Cbp of take accurately charges to input capacitance Cin as benchmark, specifically refer to: to resistance-capacitance network output constant charge current Ichr2, Ichr3 and the Ichr4 of outside resistance R in and input capacitance Cin composition, simultaneously by comparator relatively the voltage Vchr2 on this resistance-capacitance network and the voltage Vchr1 in shunt capacitance, then according to the response adjustment output charging current of comparator, until start charging, finish.Specifically refer to:
When Vchr2 equals Vchr1, the constant charge current of breaking Ichr2, Ichr3 and Ichr4, make Vchr2 fall back to the real voltage of input capacitance Cin;
Then, only to the resistance-capacitance network of outside resistance R in and input capacitance Cin composition, export constant charge current Ichr3 and Ichr4;
When Vchr2 equals Vchr1 again, the constant charge current of breaking Ichr3 and Ichr4, make Vchr2 again fall back to the real voltage of input capacitance Cin;
Then, only to the resistance-capacitance network of outside resistance R in and input capacitance Cin composition, export constant charge current Ichr4;
Finally, when Vchr2 equals Vchr1 again, the constant charge current of breaking Ichr4, charging finishes.
Refer to Fig. 1, audio power amplifier start-up charging circuit of the present utility model, comprises charge control module 101;
The end of oppisite phase of the first comparator 201 is connected with the common port of the second resistance 302 with the first resistance 301, the positive terminal of the first comparator 201 connects shunt capacitance Cbp, the output output logic signal Vcmp1 of the first comparator 201, the output of the first comparator 201 respectively with the input of the first inverter 601, the input of the input of the first Postponement module 401, the second Postponement module 402, the control end of the 3rd switch 503, minion close 507 control end, the control end of the 8th switch 508 and a control end of the first comparator 201 is connected; The first comparator 201 is receiving system reset signal Reset also;
The input of the first inverter 601 connects the output of the first comparator 201, the output of the first inverter 601 produces the logical signal of Vcmp1n, and the output of the first inverter 601 is connected with the control end of second switch 502 with the control end of the first switch 501 respectively;
The control end of the first switch 501 connects the output of the first inverter 601, and a signal end of the first switch 501 connects shunt capacitance Cbp, and another signal end of the first switch 501 connects non-essential resistance Rin;
The control end of second switch 502 connects the output of the first inverter 601, a signal end of the first switch 501 connects shunt capacitance Cbp, another signal end of the first switch 501 connects the one end in the first continuous current source 901, and the other end in the first continuous current source 901 is connected to power supply;
The control end of the 3rd switch 503 connects the output of the first inverter 601, and a signal end of the 3rd switch 503 connects shunt capacitance Cbp, and another signal end of the 3rd switch 503 connects the common port of the first resistance 301 and the second resistance 302;
The input of the first Postponement module 401 connects the output of the first comparator 201, and the output of the first Postponement module 401 produces Vdy1 signal and is connected with a control end of the second comparator 202;
The input of the second Postponement module 402 connects the output of the first comparator 201, and the output of the second Postponement module 402 produces Vset signal and is connected with shift register 801;
The end of oppisite phase of the second comparator 202 is connected with a signal end of the 8th switch 508, and another signal end of the 8th switch 508 connects shunt capacitance Cbp; The positive terminal of the second comparator 202 is connected with a signal end of minion pass 507, and minion is closed another signal end connection non-essential resistance Rin of 507.The output of the second comparator 202 produces Vcmp2 signal and is connected with the input of short pulse module 701, and the second comparator 202 is receiving system reset signal Reset also; The input of short pulse module 701 connects the output of the second comparator 202, and the output of short pulse module 701 is connected with the input of shift register 801 and the control end of the 9th switch 509 respectively; A signal end of the 9th switch 509 is connected with the common port of electric capacity 403 with the 3rd resistance 303, this common port output Vpul2; Ground connection after another signal end of the 9th switch 509 and the other end of electric capacity 403 join; The other end of the 3rd resistance 303 connects power supply; The function of short pulse module 701 is: when input is translated into high level by low level, and the pulse signal that output one width is T2, when input is translated into low level by high level, output does not change, and signal is as shown in Figure 2;
Three inputs of shift register 801 connect respectively the output of short pulse module 701, the output of the second Postponement module 402 and systematic reset signal Reset, three outputs connect respectively first with door 602, second with door the 603 and the 3rd and 604, export respectively Q1, Q2, tri-logical signals of Q3; The function of shift register 801 is: if system Reset signal is logical one, Q1, Q2, Q3 are all reset as logical zero; If system Reset signal is logical zero, shift register 801 enters normal mode of operation, when normal work, first Vset input logic " 1 ", Q1, Q2, Q3 are all set to logical one, then the rising edge of input Vpul1 is responded, when each rising edge of Vpul1, a logical zero is sequentially moved into in Q1, Q2, Q3, signal as shown in Figure 3;
First is connected respectively the output Q1 of shift register 801 and the common port of the 3rd resistance 303 and electric capacity 403 with door two inputs of 602, first with the output output Vcrt1 signal of door 602 and be connected with the control end of the 4th switch 504; A signal end of the 4th switch 504 is connected with non-essential resistance Rin, and another signal end is connected with the one end in the second continuous current source 902, and the other end in the second continuous current source 902 is connected to power supply;
Second is connected respectively the output Q2 of shift register 801 and the common port of the 3rd resistance 303 and electric capacity 403 with two inputs of door 603, and second exports Vcrt2 signal and be connected with the control end of the 5th switch 505 with the output of door 603; A signal end of the 5th switch 505 is connected with non-essential resistance Rin, and another signal end is connected with the one end in the 3rd continuous current source 903, and the other end in the 3rd continuous current source 903 is connected to power supply;
The 3rd is connected respectively the output Q3 of shift register 801 and the common port of the 3rd resistance 303 and electric capacity 403 with two inputs of door 604, and the 3rd exports Vcrt3 signal and be connected with the control end of the 6th switch 506 with the output of door 604; A signal end of the 6th switch 506 is connected with non-essential resistance Rin, and another signal end is connected with the one end in the 4th continuous current source 904, and the other end in the 4th continuous current source 904 is connected to power supply.
In the present embodiment, short pulse module 701 by the 4th with door 1001, second, third, the 4th inverter 1101,1102,1103 and the first direct-to-ground capacitance 1201 form, and consults Fig. 4, wherein:
The 4th is connected with the input of the input A1 of door 1001 and the input IN of short pulse module 701 and the second inverter 1101, the output of the second inverter 1101 connects the input of the 3rd inverter 1102, the output of the 3rd inverter 1102 connects the input of the 4th inverter 1103 and one end of the first direct-to-ground capacitance 1201, the other end ground connection of the first direct-to-ground capacitance 1201.The output connection the 4th of the 4th inverter 1103 and another input A2 of door 701.The 4th is connected the output OUT of short pulse module 701 with the output of door 1001.
In the present embodiment, the first Postponement module 401 and the second Postponement module 402 are even number by n(n such as the 5th inverter 1104, hex inverter 1105, the 7th inverter 1106, the 8th inverters 1107) individual inverter series connection and the second direct-to-ground capacitance 1202 formations, the end that joins of adjacent two inverters of one termination of the second direct-to-ground capacitance (1202), other end ground connection; Consult Fig. 5.
The operation principle of audio power amplifier start-up charging circuit of the present utility model is as follows:
Powering on initially, the first comparator 201 and shift register 801 be receiving system Reset signal first, and the output Vcmp1 of the first comparator 201 and output Q1, the Q2 of shift register 801, Q3 are all set to logical zero.System enters the quick charge stage.
In the quick charge stage, the output Vcmp1 of the first comparator 201 is logical zero, and the output Vdy1 of the first Postponement module 401 is logical zero, and the second comparator 202 turn-offs, and the output Vcmp2 of the second comparator 202 is drop-down is logical zero level.The output Vset of the second delay 402 is logical zero, output when shift register 801 keeping systems reset, be that Q1, Q2, Q3 are logical zero, first is logical zero with door the 603 and the 3rd with 604 output Vctr1, Vctr2, Vctr3 with door 602, second.The output Vcmp1n of the first inverter 601 is logical one, the first switch 501, second switch 502 conductings, shunt capacitance Cbp and non-essential resistance Rin are by the first switch 501 short circuits, charge by 502 couples of shunt capacitance Cbp of second switch and input capacitance Cin in the first continuous current source 901, voltage Vchr2 lifting thereupon on the resistance-capacitance network that voltage Vchr1 on shunt capacitance Cbp and non-essential resistance Rin and input capacitance Cin form, charging current is Ichr1.Now, Vchr1 equals Vchr2.But because Ichr1 is very large, so the pressure drop on Rin is also very large, there is larger difference with the virtual voltage on input capacitance Cin in the voltage on shunt capacitance Cbp; In the quick charge stage, the 3rd switch 503, the 4th switch 504, the 5th switch 505, the 6th switch 506, minion close the 507, the 8th switch 508 and the 9th switch 509 disconnects.Therefore, the second comparator 202 is output logic " 0 " still, and the second continuous current source 902, the 3rd continuous current source 903, the 4th continuous current source 904 are inoperative.
When the voltage Vchr1 on shunt capacitance Cbp is greater than reference voltage V ref, the first comparator 201 upsets, Vcmp1 becomes logical one, and Vcmp1n becomes logical zero.Vcmp1 returns to the first comparator 201 simultaneously, and the output of the first comparator 201 is locked as to logical one.The first switch 501 and second switch 502 disconnect, and charging current becomes 0.The 3rd switch 503 conductings, Vchr1 and Vref short circuit, the voltage on shunt capacitance Cbp remains on Vref like this.Because charging current is 0, the voltage on non-essential resistance Rin is reduced to 0, Vchr2 falling for the real voltage on input capacitance Cin, has Vchr1 to be greater than Vchr2; System enters the accurate charging stage.
In the accurate charging stage, Vcmp1 is logical one by logical zero upset, after the output Vset of the output Vdy1 of the first Postponement module 401, the second Postponement module 402 postpones a bit of time, same upset is logical one, and minion is closed the 507, the 8th switch 508 conductings.Voltage Vchr1 on shunt capacitance Cbp sends into the end of oppisite phase of the second comparator 202, and the virtual voltage Vchr2 on input capacitance Cin sends into the positive terminal of the second comparator 202; The effect of the first Postponement module 401 and the second Postponement module 402 is to wait for the subsequent conditioning circuit work that allows again after the voltage stabilization of just anti-phase two inputs of the first comparator 201.And the time of delay of the first Postponement module 401 is short compared with the second Postponement module 402, the second comparator 202 is introduced into normal mode of operation, and then shift register 801 carries out set again.
When Vdy1 turns over as logical one, the second comparator 202 enters normal mode of operation.Because Vchr1 is now greater than Vchr2, Vcmp2 output logic " 0 " still.The output Vpul1 of short pulse module 701 keeps logical zero.
When Vset upset is logical one, output Q1, the Q2 of shift register 801, Q3 are set to logical one.Now, Vpul1 keeps logical zero, and the 9th switch 509 turn-offs, and Vpul2 is logical one.Therefore, first all overturns as logical one with 604 the Vctr1 of output separately, Vctr2, Vctr3 with door the 603 and the 3rd with door 602, second, the 4th switch 504, the 5th switch 505 and the 6th switch 506 conductings, the second continuous current source 902, the 3rd continuous current source 903 and the 4th continuous current source 904 are simultaneously to input capacitance Cin charging.Charging current is Ichr2, Ichr3, Ichr4 sum, and Vchr2 rises thereupon again.When Vchr2 equals Vchr1, the second comparator 202 upsets, Vcmp2 output logic " 1 ", Vpul1 exports an impulse level, and shift register 801 is set to logical zero at impulse level rising edge by Q1, and Q2, Q3 keep logical one constant.When impulse level Vpul1 is logical one, the 9th switch 509 conductings, Vpul2 is pulled to low level, and Vctr1, Vctr2, Vctr3 all overturn as logical zero, non-essential resistance Rin end charging current is the real voltage that 0, Vchr2 falls back to input capacitance Cin again.When impulse level Vpul1 upset is during for logical zero, first with door 602, second with door the 603, the 3rd with door 604 by Q1, Q2, Q3 output, Vctr1 is logical zero, Vctr2 upset is logical one, Vctr3 upset is logical one.The second continuous current source 902 disconnects, and the 3rd continuous current source 903 and the 4th continuous current source 904 are simultaneously to input capacitance Cin charging.Charging current is Ichr3, Ichr4 sum, and Vchr2 rises thereupon again.When Vchr2 equals Vchr1 again, repeat said process, shift register 801 is set to logical zero at impulse level rising edge by Q1, Q2, and Q3 keeps logical one constant.When impulse level Vpul1 upset is logical zero, Vctr1 is logical zero, and Vctr2 is logical zero, and Vctr3 upset is logical one.The second continuous current source 902 and the 3rd continuous current source 903 disconnect, and only have the 904 couples of input capacitance Cin charging of the 4th continuous current source.Charging current is Ichr4, and Vchr2 rises thereupon again.When Vchr2 equals Vchr1 again, the second comparator 202 overturns again, and after short pulse module 701, shift register 801 etc. are processed, Vctr1, Vctr2, Vctr3 all overturn as logical zero, all continuous current sources all disconnect, and whole charging process finishes.Whole sequential chart can be referring to Fig. 6.
In above-mentioned charging process, Ichr1 is set as being greater than Ichr2, Ichr3, the Ichr4 sum of 5 times.It is Ichr2>=5 that size of current between Ichr2, Ichr3, Ichr4 is closed
*ichr3>=5
*ichr4.Therefore, concerning input capacitance Cin, whole charging current is that substep reduces, voltage drop while charging so on non-essential resistance Rin also decreases, if the electric current of Ichr4 is rationally set, while reaching final charge step, the pressure drop on non-essential resistance Rin can be controlled in several millivolts, negligible.That is to say that the real voltage that can think on input capacitance Cin equates with the voltage on shunt capacitance Cbp, thereby bury in oblivion Pop sound.And, because the electric current of Ichr1, Ichr2 can be larger, therefore also reduced the whole charging interval.Again, because all charging current sources are constant current, charging precision only depends on the size of Ichr4, for different big or small peripheral electric capacity, can obtain identical charging precision, can obtain identical Pop and suppress ability, has improved the scope of application of system.
In the present embodiment, short pulse module 701 operation principles are: VCMP2 signal receive the 4th with door 1001 input A1.Simultaneously, VCMP2 signal is through the second to the 4th inverter 1101,1102, the 1103 and first direct-to-ground capacitance 1201 postpone to receive after upset the 4th with another input A2 of door 1001, A1 like this, the signal of A2 simultaneously for the logical one time phase with just produced short pulse signal, the inner sequential chart of short pulse module 701 is referring to Fig. 7.
The operation principle of the first Postponement module 401, the second Postponement modules 402 is: by the inverter number of connecting and the second direct-to-ground capacitance size, determined time of delay.Inverter number is more, and electric capacity is longer larger time of delay.Specifically, if n inverter of series connection, be n time of delay
*t1, t1 is the single gate delay time.Electric capacity is connected on the output of a certain inverter, and in order to inhibit signal rising edge, be t2 time of delay.Be t2+n so total time of delay
*t1.And because the number of n is even number, input signal IN and output signal OUT are same-phases, are only delayed t2+n
*t1.
Above embodiment is only for illustration of the utility model, but not to restriction of the present utility model, person skilled in the relevant technique, in the situation that not departing from spirit and scope of the present utility model, can also make various conversion or modification, therefore all technical schemes that are equal to also should belong to category of the present utility model, should be limited by each claim.
Claims (7)
1. an audio power amplifier start-up charging circuit, external resistance-capacitance network and the shunt capacitance being comprised of non-essential resistance and input capacitance, is characterized in that, described startup charging circuit comprises charge control module (101);
Described charge control module (101) comprises power supply, the first comparator (201), the second comparator (202), short pulse module (701), shift register (801), the first Postponement module (401), the second Postponement module (402), the first resistance (301), the second resistance (302), the 3rd resistance (303), electric capacity (403), the first inverter (601), first with door (602), second with door (603), the 3rd with door (604), the first continuous current source (901), the second continuous current source (902), the 3rd continuous current source (903) and the 4th continuous current source (904), and nine have two signal ends and a control end switch: the first switch (501), second switch (502), the 3rd switch (503), the 4th switch (504), the 5th switch (505), the 6th switch (506), minion is closed (507), the 8th switch (508) and the 9th switch (509), wherein:
Described the first resistance (301) one end connects described power supply, and the other end is by described the second resistance (302) ground connection; The common port output reference voltage Vref of described the first resistance (301) and the second resistance (302);
The end of oppisite phase of described the first comparator (201) connects the common port of described the first resistance (301) and the second resistance (302), positive terminal connects described shunt capacitance, output connect respectively the input of described the first inverter (601), the input of the input of the first Postponement module (401), the second Postponement module (402), the control end of the 3rd switch (503), minion close a control end of the control end of (507), the control end of the 8th switch (508) and the first comparator (201); Described the first comparator (201) receiving system reset signal Reset;
Described the first inverter (601) output connects respectively the control end of described the first switch (501) and the control end of second switch (502);
A signal end of described the first switch (501) connects described shunt capacitance, and another signal end connects described non-essential resistance;
A signal end of described second switch (502) connects described shunt capacitance, and another signal end connects the one end in described the first continuous current source (901), and the other end in the first continuous current source (901) connects described power supply;
A signal end of described the 3rd switch (503) connects described shunt capacitance, and another signal end connects the common port of described the first resistance (301) and the second resistance (302);
A control end of described the second comparator (202) connects the output of described the first Postponement module (401), the signal end that end of oppisite phase connects described the 8th switch (508) is connected, and another signal end of the 8th switch (508) connects described shunt capacitance; The positive terminal of described the second comparator (202) is connected with the signal end that described minion is closed (507), and another signal end that minion is closed (507) connects described non-essential resistance; The output of described the second comparator (202) is connected with the input of described short pulse module (701); Described the second comparator (202) receiving system reset signal Reset;
Described shift register (801) is containing three inputs and three outputs, an input connects the output of described short pulse module (701), an input connects the output of the second Postponement module (402), an input receiving system reset signal Reset;
The control end of described the 9th switch (509) connects the output of described short pulse module (701), and two signal ends of the 9th switch (509) are connected one by one with the two ends of described electric capacity (403); Described electric capacity (403) one end connects described power supply, other end ground connection by described the 3rd resistance (303);
Described first is connected with three outputs of described shift register (801) with door (604) input separately with the 3rd with door (603) one by one with door (602), second, and another input separately all connects the common port of described the 3rd resistance (303) and electric capacity (403);
The control end of described the 4th switch (504) connect described first with door (602) output, a signal end connects described non-essential resistance, another signal end connects the one end in described the second continuous current source (902), and the other end in the second continuous current source (902) connects described power supply;
The control end of described the 5th switch (505) connect described second with door (602) output, a signal end connects described non-essential resistance, another signal end connects the one end in described the 3rd continuous current source (903), and the other end in the 3rd continuous current source (903) connects described power supply;
The control end of described the 6th switch (506) connect the described the 3rd with door (603) output, a signal end connects described non-essential resistance, another signal end connects the one end in described the 4th continuous current source (904), and the other end in the 4th continuous current source (904) connects described power supply.
2. audio power amplifier start-up charging circuit according to claim 1, is characterized in that, when the input of described short pulse module (701) is translated into high level by low level, and output one pulse signal, when input is translated into low level by high level, output does not change.
3. audio power amplifier start-up charging circuit according to claim 2, it is characterized in that, described shift register (801) sequentially moves in three outputs by a logical zero when each rising edge of the pulse signal of described short pulse module (701) output.
4. audio power amplifier start-up charging circuit according to claim 1, is characterized in that, is less than the time of delay of described the second Postponement module (402) time of delay of described the first Postponement module (401).
5. audio power amplifier start-up charging circuit according to claim 1, it is characterized in that, described the first continuous current source (901), the second continuous current source (902), the 3rd continuous current source (903) and the 4th continuous current source (904) charging current are separately respectively Ichr1, Ichr2, Ichr3 and Ichr4, Ichr2, Ichr3 and Ichr4 sum that Ichr1 is greater than 5 times, and Ichr2>=5
*ichr3>=5
*ichr4.
6. audio power amplifier start-up charging circuit according to claim 1, it is characterized in that, described short pulse module (701) comprise the 4th with door (1001), second, third, the 4th inverter (1101,1102,1103) and the first direct-to-ground capacitance (1201), wherein:
The 4th is connected with the input of door one input of (1001) and the input of short pulse module (701) and the second inverter (1101), the output of the second inverter (1101) connects the input of the 3rd inverter (1102), the output of the 3rd inverter (1102) connects the input of the 4th inverter (1103) and one end of the first direct-to-ground capacitance (1201), the other end ground connection of the first direct-to-ground capacitance (1201), the output connection the 4th of the 4th inverter (1103) and another input of door (701); The 4th is connected the output of short pulse module (701) with the output of door (1001).
7. audio power amplifier start-up charging circuit according to claim 1, is characterized in that, described the first Postponement module (401) and the second Postponement module (402) include inverter and second direct-to-ground capacitance (1202) of n series connection, and n is even number; The end that joins of adjacent two inverters of one termination of the second direct-to-ground capacitance (1202), other end ground connection.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320724988.7U CN203590181U (en) | 2013-11-15 | 2013-11-15 | Audio frequency power amplifier starting charging circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320724988.7U CN203590181U (en) | 2013-11-15 | 2013-11-15 | Audio frequency power amplifier starting charging circuit |
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| CN203590181U true CN203590181U (en) | 2014-05-07 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103607681A (en) * | 2013-11-15 | 2014-02-26 | 上海贝岭股份有限公司 | An audio frequency power amplifier starting charging circuit and a method |
| CN109068240A (en) * | 2018-08-27 | 2018-12-21 | 上海艾为电子技术股份有限公司 | A kind of digital audio power amplification system |
-
2013
- 2013-11-15 CN CN201320724988.7U patent/CN203590181U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103607681A (en) * | 2013-11-15 | 2014-02-26 | 上海贝岭股份有限公司 | An audio frequency power amplifier starting charging circuit and a method |
| CN109068240A (en) * | 2018-08-27 | 2018-12-21 | 上海艾为电子技术股份有限公司 | A kind of digital audio power amplification system |
| CN109068240B (en) * | 2018-08-27 | 2024-02-23 | 上海艾为电子技术股份有限公司 | Digital audio power amplifier system |
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