CN103066972A - Power-on reset circuit with global enabling pulse control automatic reset function - Google Patents
Power-on reset circuit with global enabling pulse control automatic reset function Download PDFInfo
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Abstract
The invention discloses a power-on reset circuit with a global enabling pulse control automatic reset function. The power-on reset circuit comprises a voltage dividing module, a level detection module, a quick response module, a delay module, a reset pulse signal generation module, and a waveform shaping module, wherein the input end of the voltage dividing module is connected with an external enabling pulse signal; the output end of the voltage dividing module is connected with the input end of the level detection module and the output end of the quick response module; the output end of the level detection module is connected with the input ends of both of the quick response module and the delay module; the output end of the delay module is connected with the input end of the reset pulse signal generation module; the output end of the reset pulse signal generation module is connected with the input end of the waveform shaping module; and the voltage of the output end of the waveform shaping module is the output signal of the power-on reset circuit. The power-on reset circuit provided by the invention can generate reset pulses to reset and automatically restart a digital circuit in the power-on process of a power supply or under the control of a global reset pulse signal.
Description
Technical field
The present invention relates to a kind of electrify restoration circuit, relate in particular to a kind of electrify restoration circuit with overall enabling pulse control auto-reset function, belong to analog to digital composite signal integrated circuits design field.
Background technology
Along with the increase of level of integrated system and application demand, increasing digital module and analog module are embedded in the same chip, and the application of digital hybrid circuit is also more and more extensive.In extensive digifax mix signal integrate circuit chip design; owing to have the electronic circuit unit such as a large amount of registers, trigger in the chip; the state of these electronic circuit unit is uncertain when power supply begins to be added on the chip, and this can cause whole chip from misoperation or also will reconfigure register by sending instruction before normal operation.Therefore, automatically provide afterwards the value that a reset signal refreshes register if can when chip power, reach a certain value at supply voltage, then can avoid system's misoperation or need the special time to dispose the situation of initial condition, electrify restoration circuit is exactly the element circuit of finishing specially this function.
When using the digital-to-analogue hybrid chip; the operation irregularity situation such as overflow when output valve occurring, perhaps the digital-to-analogue hybrid chip need to be carried out initialization and proofreaied and correct, when perhaps having the park mode function; need to carry out power down or reset processing to whole chip, restart again afterwards this chip.In this process, also need again some registers in the digital module to be reinitialized.But this moment, we wish to carry out resetting of digital module after the analog module circuit all reaches stable quiescent point again, and whole digital-to-analogue hybrid chip just can work resetting after like this, otherwise also may cause the situation of initialization failure.
At present, generally be that electrify restoration circuit and whole chip reset circuit are designed respectively, when whole chip reset, need design circuit to satisfy certain sequential, again the digital module register is resetted after making analog module reach first stable operating point, such shortcoming is the complexity that can increase circuit, causes the waste of chip area and power consumption.
Summary of the invention
The objective of the invention is to overcome and address the above problem, a kind of electrify restoration circuit with overall enabling pulse control auto-reset function is provided, under the prerequisite of saving chip area and power consumption, make reset in the digital-to-analog composite signal integrated circuits more accurate.
For realizing above purpose, technical scheme of the present invention is as follows: a kind of electrify restoration circuit with overall enabling pulse control auto-reset function, comprise division module, level detection module, quick respond module, time delay module, reseting pulse signal generation module and waveform-shaping module, the outside enabling pulse signal of the input termination of division module; The output of division module is connected with the input of level detection module, the output of quick respond module; The output of level detection module is connected with the input of quick respond module, the input of time delay module; The output of time delay module is connected with the input of reseting pulse signal generation module; The output of reseting pulse signal generation module is connected with the input of waveform-shaping module; The voltage of the output of waveform-shaping module is as the output signal of electrify restoration circuit, wherein: division module is for generation of the component of voltage relevant with supply voltage, it is controlled by external input signal, when external input signal was not worked division module, the final output level of division module output was lower than the trigging signal of testing circuit module; The level detection module is for detection of the output level of division module, according to the size of the output level of division module, at the different voltage signal of output output of level detection module; Quick respond module, be used for detect the division module output level greater than a certain fixed value after, make the output level fast rise of division module; Time delay module is used for adjusting the time interval between power up and the reseting pulse signal generation; The reseting pulse signal generation module for generation of the reset level pulse signal, resets afterwards at certain time intervals and finishes, and reset pulse finishes;
Waveform-shaping module, the output voltage that the reseting pulse signal generation module is produced amplifies and shaping, and will amplify with shaping after voltage signal as the output signal of electrify restoration circuit.
Preferably:
Described voltage module circuit contains the P type metal-oxide-semiconductor M1 as switching tube, under the control of systematic reset signal division module is enabled control; P type metal-oxide-semiconductor M2, M3, M4, the M5 of 4 diode connections form bleeder circuit, and the voltage with mains voltage variations is provided; The first resistance R 1 and the first capacitor C 1 form filter circuit, and the final Voltage-output of division module is provided.The source electrode of P type metal-oxide-semiconductor M1 is connected with power supply; The grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of the first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; One end of the other end of the first resistance R 1, the first capacitor C 1 and the output of division module interconnect; The other end of the first capacitor C 1 is connected with ground.
Described level detection modular circuit contains P type metal-oxide-semiconductor M6, N-type metal-oxide-semiconductor M7, consists of level sensitive circuit, by adjusting the suitable trigging signal of device size design of P type metal-oxide-semiconductor M6 and N-type metal-oxide-semiconductor M7; The first inverter INV1 is used to provide the opposite levels of signal, and the input and output signal of the first inverter INV1 is controlled the transmission gate in the quick respond module circuit simultaneously.The grid of the output of the input of level detection modular circuit, division module circuit, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7 interconnect with the output of quick respond module; The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; The output of the output of the first inverter INV1 and level detection modular circuit interconnects.
Described quick respond module circuit contains as the P type metal-oxide-semiconductor M8 of switching tube with as the N-type metal-oxide-semiconductor M9 of switching tube, consists of a transmission gate; The second capacitor C 2 provides electric charge for the output to the division module circuit when the transmission gate conducting, accelerates the rising of the output end voltage of division module circuit.The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The grid of the output of the first inverter INV1, the input of time delay module and N-type metal-oxide-semiconductor M9 interconnects; One end of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9 and the second capacitor C 2 interconnects; The other end of the second capacitor C 2 is connected with power supply; The drain electrode of the input of the output of division module circuit, level detection modular circuit, P type metal-oxide-semiconductor M8, the source electrode of N-type metal-oxide-semiconductor M9 interconnect with the output of quick respond module circuit.
Described time delay module circuit contains the second inverter INV2, the 3rd inverter INV3, is used for the anti-phase output of voltage; P type metal-oxide-semiconductor M10, N-type metal-oxide-semiconductor M11, P type metal-oxide-semiconductor M12, N-type metal-oxide-semiconductor M13, the 3rd capacitor C 3 and the 4th capacitor C 4 are for generation of the signal lag that is input to output.The input of the output of the input of time delay module circuit, level detection modular circuit and the second inverter INV2 interconnects; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; The input of the output of the output of the 3rd inverter INV3, time delay module circuit and reseting pulse signal generation module circuit interconnects.
Described reseting pulse signal generation module circuit contains P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, the 5th capacitor C 5 and the 6th capacitor C 6, for generation of the signal lag that is input to output; The 4th inverter INV4 is used for the anti-phase output of voltage; First liang of input nand gate NAND2 by the difference of input signal, produces reset pulse output.The input of the grid of the input of time delay module circuit output end, reseting pulse signal generation module circuit, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15 and first liang of input nand gate NAND2 interconnects; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2 and the output of the 4th inverter INV4 interconnect; The input of the output of first liang of input nand gate NAND2 and waveform-shaping module circuit interconnects.
Described waveform-shaping module circuit contains the 5th inverter INV5 and hex inverter INV6, and input signal is amplified and shaping, and the electrification reset output signal is provided.The input of the output of reseting pulse signal generation module circuit, the input of waveform-shaping module circuit and the 5th inverter INV5 interconnects; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
The concrete connected mode of above-mentioned on the whole reset circuit is as follows: the grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of the first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; The drain electrode of the grid of one end of the other end of resistance R 1, the first capacitor C 1, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7, P type metal-oxide-semiconductor M8 and the source electrode of N-type metal-oxide-semiconductor M9 interconnect; The other end of the first capacitor C 1 is connected with ground; The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; The grid of the input of the output of the first inverter INV1, the second inverter INV2 and N-type metal-oxide-semiconductor M9 interconnects; One end of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9 and the second capacitor C 2 interconnects; The other end of the second capacitor C 2 is connected with power supply; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; The input of the grid of the output of the 3rd inverter INV3, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15 and first liang of input nand gate NAND2 interconnects; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2 and the output of the 4th inverter INV4 interconnect; The input of first liang of input nand gate NAND2 output and the 5th inverter INV5 interconnects; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
Compared with prior art, the present invention has the following advantages and remarkable result:
Electrify restoration circuit among the present invention both can be realized the electrification reset function, also can be when the digital-to-analogue hybrid chip be carried out Global reset, and produce and allow the pulse signal of digital module circuit reset.Than alternate manner, saved total area and the power consumption of circuit;
Quick respond module circuit among the present invention can just reach at circuit the threshold voltage of the upset that resets, and begins to produce the moment quickening capacitor charging of reset signal, makes reset signal more precipitous;
Can regulate the resetting time of the electrify restoration circuit among the present invention by the metal-oxide-semiconductor in the reseting pulse signal generation module circuit and the value of electric capacity.
Description of drawings
Fig. 1 is the basic framework figure of electrify restoration circuit in the present embodiment;
Fig. 2 is the circuit structure diagram of electrify restoration circuit in the present embodiment.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing embodiments of the invention are described in further detail.
A kind of electrify restoration circuit with overall enabling pulse control auto-reset function in the present embodiment, its basic framework figure as shown in Figure 1, comprise division module 1, level detection module 2, quick respond module 3, time delay module 4, reseting pulse signal generation module 5 and waveform-shaping module 6, the outside enabling pulse signal of the input termination of division module 1; The output of division module 1 is connected with the input of level detection module 2, the output of quick respond module 3; The output of level detection module 2 is connected with the input of quick respond module 3, the input of time delay module 4; The output of time delay module 4 is connected with the input of reseting pulse signal generation module 5; The output of reseting pulse signal generation module 5 is connected with the input of waveform-shaping module 6; The voltage of the output of waveform-shaping module 6 is as the output signal of electrify restoration circuit, wherein: division module 1 is for generation of the component of voltage relevant with supply voltage, it is controlled by external input signal, when external input signal was not worked division module 1, the final output level of division module 1 output was lower than the trigging signal of testing circuit module; Level detection module 2 is for detection of the output level of division module 1, according to the size of the output level of division module 1, at the different voltage signal of output output of level detection module 2; Quick respond module 3, be used for detect division module 1 output level greater than a certain fixed value after, make the output level fast rise of division module 1; Time delay module 4 is used for adjusting the time interval between power up and the reseting pulse signal generation; Reseting pulse signal generation module 5 for generation of the reset level pulse signal, resets afterwards at certain time intervals and finishes, and reset pulse finishes; Waveform-shaping module 6, the output voltage that reseting pulse signal generation module 5 is produced amplifies and shaping, and will amplify with shaping after voltage signal as the output signal of electrify restoration circuit.Particular circuit configurations figure among the embodiment such as Fig. 2.Voltage module 1 is by P type metal-oxide-semiconductor M1,4 P type metal-oxide-semiconductor M2, M3, M4, M5 that diode connects, and resistance R 1 and capacitor C 1 consist of; Level detection module 2 is by P type metal-oxide-semiconductor M6, and N-type metal-oxide-semiconductor M7 and the first inverter INV1 consist of; Fast respond module 3 is by P type metal-oxide-semiconductor M8, N-type metal-oxide-semiconductor M9, and capacitor C 2 consists of; Time delay module 4 is by the second inverter INV2, the 3rd inverter INV3, and P type metal-oxide-semiconductor M10, N-type metal-oxide-semiconductor M11, P type metal-oxide-semiconductor M12, N-type metal-oxide-semiconductor M13, capacitor C 3 and capacitor C 4 consist of; Reseting pulse signal generation module 5 is by P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, and P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, capacitor C 5, capacitor C 6, the four inverter INV4, first liang of input nand gate NAND2 consists of.Waveform-shaping module 6 is by the 5th inverter INV5, and hex inverter INV6 consists of.
On the whole, this circuit structure connects in the following manner: the grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of the first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; The drain electrode of the grid of one end of the other end of resistance R 1, the first capacitor C 1, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7, P type metal-oxide-semiconductor M8, source electrode and the terminal A of N-type metal-oxide-semiconductor M9 interconnect; The other end of the first capacitor C 1 is connected with ground; The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The grid of the drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, P type metal-oxide-semiconductor M8, input and the end points CP of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; Grid and the end points CN of the input of the output of the first inverter INV1, the second inverter INV2, N-type metal-oxide-semiconductor M9 interconnect; One end and the terminal B of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9, the second capacitor C 2 interconnect; The other end of the second capacitor C 2 is connected with power supply; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; Input and the end points C of the grid of the output of the 3rd inverter INV3, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15, first liang of input nand gate NAND2 interconnect; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2, the output of the 4th inverter INV4 and end points D interconnect; Input and the end points E of first liang of input nand gate NAND2 output, the 5th inverter INV5 interconnect; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
In the present embodiment, when chip power power up and a high impulse global reset signal of CTR signal generation, all can produce a reset pulse.Make a concrete analysis of as follows:
When CTR connects low level all the time, all the time conducting of P type metal-oxide-semiconductor M1.In the power up, the power vd D increase of starting from scratch, the voltage of terminal A is corresponding increase also, but the increase amplitude is about power vd D half.
When power vd D increases to a certain value (such as threshold V T HP), but the voltage of terminal A is when also surpassing threshold V T HN, P type metal-oxide-semiconductor M6 conducting, and N-type metal-oxide-semiconductor M7 closes, so the voltage of end points CP voltage follow power vd D and changing.Accordingly, the voltage of end points CN, end points C is low level voltage, the change in voltage of the voltage follow power vd D of end points D, end points E.So P type metal-oxide-semiconductor M8 and N-type metal-oxide-semiconductor M9 turn-off, the voltage of terminal B is followed the change in voltage of power vd D always.
After terminal A voltage was greater than threshold V T HN, the voltage of end points CP was low level by the voltage upset of power vd D, and the voltage of end points CN is the voltage of power vd D by the low level upset.So, P type metal-oxide-semiconductor M8 and all conductings of N-type metal-oxide-semiconductor M9, electric charge on the terminal B and the electric charge on the terminal A are redistributed, because the voltage on the terminal B is the voltage of power vd D before conducting, and the voltage on the terminal A is larger than the value of capacitor C 1 if the value of C2 is held in power taking less than the voltage of power vd D, so, the voltage of redistributing on the aft terminal A can greater than original value, so just reach the purpose of accelerating the electrification reset response.
Because the voltage of end points CN is the voltage of power vd D by the low level upset, the voltage of end points C is being the voltage of power vd D by the low level upset also after the delay of t1 after a while, because having, the circuit that P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, capacitor C 5 and capacitor C 6 consist of produces the signal lag function that is input to output, this moment, the voltage of end points D still be the voltage of power vd D, was low level so the output voltage of first liang of input nand gate NAND2 is overturn by the voltage of power vd D.But after end points C voltage was voltage a period of time t2 of power vd D by the low level upset, end points D was low level by the voltage upset of power vd D, and the output voltage of first liang of input nand gate NAND2 is the voltage of power vd D by the low level upset.So in the power up of power vd D, the voltage of end points E can produce one and be turned to low level by the power supply vdd voltage, is turned to the pulse of power supply vdd voltage from low level again, its pulse duration is about time t2.Because the 5th inverter INV5 and hex inverter INV6 are the shapings that is input to output, so the output end voltage of hex inverter INV6 that is to say that the voltage of the output signal RST of electrify restoration circuit can produce a low level reseting pulse signal.
When the power supply vdd voltage was in the normal working voltage scope all the time, if the CTR signal is a high level pulse signal, just reset circuit also can produce the reset signal of a low level pulse after the trailing edge of CTR signal.Make a concrete analysis of as follows:
When the power supply vdd voltage is in the normal working voltage scope all the time, and other circuit is when work in the chip, voltage should be low level on the CTR signal, at this moment, the voltage of end points CP, end points D is low level in the electrify restoration circuit, and the voltage of the output RST signal of end points CN, end points C, end points E, terminal A, electrify restoration circuit is the power supply vdd voltage.At this moment, P type metal-oxide-semiconductor M8 and all conductings of N-type metal-oxide-semiconductor M9, terminal A equates substantially with the voltage of terminal B, and greater than threshold V T HN.
Voltage on the CTR signal is the power supply vdd voltage by the low level upset, P type metal-oxide-semiconductor M1 closes, and does not have electric current in the branch road that P type metal-oxide-semiconductor M1, M2, M3, M4, M5 consist of, so, each node voltage in the branch road all can descend, so the also corresponding decline of the voltage of terminal A.When the voltage drop of terminal A to less than VTHN, the voltage of end points CP is the voltage of power vd D by the low level upset, the voltage of end points CN is low level by the voltage upset of power vd D.So P type metal-oxide-semiconductor M8 and N-type metal-oxide-semiconductor M9 turn-off.After a period of time in, the voltage that the voltage of terminal B is no longer followed terminal A descends together, but remains a certain fixed value VB.The voltage of end points C is turned to low level by the power supply vdd voltage, and the voltage of end points D is turned to the power supply vdd voltage by low level.The voltage of the output signal RST of end points E, electrify restoration circuit remains unchanged, and still is the power supply vdd voltage.
If the time long enough of CTR signal high level, the voltage of terminal A can drop to the threshold voltage sum near P type metal-oxide-semiconductor M4 and M5.
Voltage on the CTR signal is low level by the upset of power supply vdd voltage, all the time conducting of P type metal-oxide-semiconductor M1, and the branch road that P type metal-oxide-semiconductor M1, M2, M3, M4, M5 consist of can charge to terminal A, and the voltage of terminal A can rise,
After terminal A voltage was greater than threshold V T HN, the voltage of end points CP was low level by the voltage upset of power vd D, and the voltage of end points CN is the voltage of power vd D by the low level upset.P type metal-oxide-semiconductor M8 and all conductings of N-type metal-oxide-semiconductor M9, electric charge on the terminal B and the electric charge on the terminal A are redistributed, because the voltage on the terminal B is when voltage is the power supply vdd voltage on the CTR signal, remain on a higher level, voltage on ratio terminal A this moment is large, and is larger than the value of capacitor C 1 if the value of C2 is held in power taking, so, the voltage of redistributing on the aft terminal A can greater than original value, so just reach the purpose that acceleration resets and responds.
Because the voltage of end points CN is the voltage of power vd D by the low level upset, the voltage of end points C is being the voltage of power vd D by the low level upset also after the delay of t1 after a while, because having, the circuit that P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, capacitor C 5 and capacitor C 6 consist of produces the signal lag function that is input to output, this moment, the voltage of end points D still be the voltage of power vd D, was low level so the output voltage of first liang of input nand gate NAND2 is overturn by the voltage of power vd D.But after end points C voltage was voltage a period of time t2 of power vd D by the low level upset, end points D was low level by the voltage upset of power vd D, and the output voltage of first liang of input nand gate NAND2 is the voltage of power vd D by the low level upset.So in the power up of power vd D, the voltage of end points E can produce one and be turned to low level by the power supply vdd voltage, is turned to the pulse of power supply vdd voltage from low level again, its pulse duration is about time t2.Because the 5th inverter INV5 and hex inverter INV6 are the shapings that is input to output, so the output end voltage of hex inverter INV6 that is to say that the voltage of the output signal RST of electrify restoration circuit can produce a low level reseting pulse signal.
The content that is not described in detail in this specification belongs to the known prior art of this area professional and technical personnel.
Above embodiment is a preferred embodiment of the present invention only, but is not the whole of all circuit set-up modes of the present invention, all in Spirit Essence scope of the present invention with the interior equivalents of being done, all will be in protection range of the present invention.
Claims (7)
1. electrify restoration circuit with overall enabling pulse control auto-reset function, it is characterized in that: described circuit comprises division module (1), level detection module (2), quick respond module (3), time delay module (4), reseting pulse signal generation module (5) and waveform-shaping module (6), the outside enabling pulse signal of the input termination of division module (1); The output of division module (1) is connected with the output of the input of level detection module (2), quick respond module (3); The output of level detection module (2) is connected with the input of quick respond module (3), the input of time delay module (4); The output of time delay module (4) is connected with the input of reseting pulse signal generation module (5); The output of reseting pulse signal generation module (5) is connected with the input of waveform-shaping module (6); The voltage of the output of waveform-shaping module (6) is as the output signal of electrify restoration circuit, wherein:
Division module (1) is for generation of the component of voltage relevant with supply voltage, it is controlled by external input signal, when external input signal makes division module (1) when not working, the final output level of division module (1) output is lower than the trigging signal of testing circuit module;
Level detection module (2) is for detection of the output level of division module (1), according to the size of the output level of division module (1), at the different voltage signal of output output of level detection module (2);
Quick respond module (3), be used for detect division module (1) output level greater than a certain fixed value after, make the output level fast rise of division module (1);
Time delay module (4) is used for adjusting the time interval between power up and the reseting pulse signal generation;
Reseting pulse signal generation module (5) for generation of the reset level pulse signal, resets afterwards at certain time intervals and finishes, and reset pulse finishes;
Waveform-shaping module (6), the output voltage that reseting pulse signal generation module (5) is produced amplifies and shaping, and will amplify with shaping after voltage signal as the output signal of electrify restoration circuit.
2. a kind of electrify restoration circuit with overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described voltage module (1) contains the P type metal-oxide-semiconductor M1 as switching tube, under the control of systematic reset signal division module is enabled control; P type metal-oxide-semiconductor M2, M3, M4, the M5 of 4 diode connections form bleeder circuit, and the voltage with mains voltage variations is provided; The first resistance R 1 and the first capacitor C 1 form filter circuit, and the final Voltage-output of division module is provided;
Division module (1) circuit connects in the following manner:
The source electrode of P type metal-oxide-semiconductor M1 is connected with power supply; The grid of P type metal-oxide-semiconductor M1 is connected with systematic reset signal CTR; The source electrode of the drain electrode of P type metal-oxide-semiconductor M1 and P type metal-oxide-semiconductor M2 interconnects; The grid of P type metal-oxide-semiconductor M2, the source electrode of the drain electrode of P type metal-oxide-semiconductor M2 and P type metal-oxide-semiconductor M3 interconnects; The grid of P type metal-oxide-semiconductor M3, the source electrode of the drain electrode of P type metal-oxide-semiconductor M3, P type metal-oxide-semiconductor M4 and an end of the first resistance R 1 interconnect; The grid of P type metal-oxide-semiconductor M4, the source electrode of the drain electrode of P type metal-oxide-semiconductor M4 and P type metal-oxide-semiconductor M5 interconnects; The grid of P type metal-oxide-semiconductor M5, the drain electrode of P type metal-oxide-semiconductor M5 with interconnect; The output of one end of the other end of the first resistance R 1, the first capacitor C 1 and division module (1) interconnects; The other end of the first capacitor C 1 is connected with ground.
3. a kind of electrify restoration circuit with overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described level detection module (2) circuit contains P type metal-oxide-semiconductor M6, N-type metal-oxide-semiconductor M7, consist of level sensitive circuit, by adjusting the suitable trigging signal of device size design of P type metal-oxide-semiconductor M6 and N-type metal-oxide-semiconductor M7; The first inverter INV1 is used to provide the opposite levels of signal, and the input and output signal of the first inverter INV1 is controlled the transmission gate in the quick respond module circuit simultaneously;
Level detection module (2) circuit connects in the following manner:
The grid of the output of the input of level detection module (2) circuit, division module (1) circuit, P type metal-oxide-semiconductor M6, the grid of N-type metal-oxide-semiconductor M7 interconnect with the output of quick respond module (3); The source electrode of P type metal-oxide-semiconductor M6 is connected with power supply; The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The source electrode of N-type metal-oxide-semiconductor M7 is connected with ground; The output of the output of the first inverter INV1 and level detection module (2) circuit interconnects.
4. a kind of electrify restoration circuit with overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described quick respond module (3) circuit contains as the P type metal-oxide-semiconductor M8 of switching tube with as the N-type metal-oxide-semiconductor M9 of switching tube, consists of a transmission gate; The second capacitor C 2 provides electric charge for the output to the division module circuit when the transmission gate conducting, accelerates the rising of the output end voltage of division module circuit;
Respond module (3) circuit connects in the following manner fast:
The drain electrode of P type metal-oxide-semiconductor M6, the drain electrode of N-type metal-oxide-semiconductor M7, the grid of P type metal-oxide-semiconductor M8 and the input of the first inverter INV1 interconnect; The grid of the input of the output of the first inverter INV1, time delay module (4) and N-type metal-oxide-semiconductor M9 interconnects; One end of the source electrode of P type metal-oxide-semiconductor M8, the drain electrode of N-type metal-oxide-semiconductor M9 and the second capacitor C 2 interconnects; The other end of the second capacitor C 2 is connected with power supply; The drain electrode of the input of the output of division module (1) circuit, level detection module (2) circuit, P type metal-oxide-semiconductor M8, the source electrode of N-type metal-oxide-semiconductor M9 interconnect with the output of quick respond module (3) circuit.
5. a kind of electrify restoration circuit with overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described time delay module (4) circuit contains the second inverter INV2, the 3rd inverter INV3, is used for the anti-phase output of voltage; P type metal-oxide-semiconductor M10, N-type metal-oxide-semiconductor M11, P type metal-oxide-semiconductor M12, N-type metal-oxide-semiconductor M13, the 3rd capacitor C 3 and the 4th capacitor C 4 are for generation of the signal lag that is input to output;
Time delay module (4) circuit connects in the following manner:
The output of the input of time delay module (4) circuit, level detection module (2) circuit and the input of the second inverter INV2 interconnect; The grid of the output of the second inverter INV2, P type metal-oxide-semiconductor M10 and the grid of N-type metal-oxide-semiconductor M11 interconnect; The source electrode of P type metal-oxide-semiconductor M10 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M11 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M10, the drain electrode of N-type metal-oxide-semiconductor M11, the 3rd capacitor C 3, the grid of P type metal-oxide-semiconductor M12 and the grid of N-type metal-oxide-semiconductor M13 interconnect; The other end of the 3rd capacitor C 3 is connected with ground; The source electrode of P type metal-oxide-semiconductor M12 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M13 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M12, the drain electrode of N-type metal-oxide-semiconductor M13, an end of the 4th capacitor C 4 and the input of the 3rd inverter INV3 interconnect; The input of the output of the output of the 3rd inverter INV3, time delay module (4) circuit and reseting pulse signal generation module (5) circuit interconnects.
6. a kind of electrify restoration circuit with overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described reseting pulse signal generation module (5) circuit contains P type metal-oxide-semiconductor M14, N-type metal-oxide-semiconductor M15, P type metal-oxide-semiconductor M16, N-type metal-oxide-semiconductor M17, the 5th capacitor C 5 and the 6th capacitor C 6, for generation of the signal lag that is input to output; The 4th inverter INV4 is used for the anti-phase output of voltage; First liang of input nand gate NAND2 by the difference of input signal, produces reset pulse output;
Reseting pulse signal generation module (5) circuit connects in the following manner:
The input of the grid of the input of time delay module (4) circuit output end, reseting pulse signal generation module (5) circuit, P type metal-oxide-semiconductor M14, the grid of N-type metal-oxide-semiconductor M15 and first liang of input nand gate NAND2 interconnects; The source electrode of P type metal-oxide-semiconductor M14 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M15 is connected with ground; One end of the drain electrode of P type metal-oxide-semiconductor M14, the drain electrode of N-type metal-oxide-semiconductor M15, the 5th capacitor C 5, the grid of P type metal-oxide-semiconductor M16 and the grid of N-type metal-oxide-semiconductor M17 interconnect; The other end of the 5th capacitor C 5 is connected with ground; The source electrode of P type metal-oxide-semiconductor M16 is connected with power supply; The source electrode of N-type metal-oxide-semiconductor M17 is connected with ground; The drain electrode of P type metal-oxide-semiconductor M16, the drain electrode of N-type metal-oxide-semiconductor M17, an end of the 6th capacitor C 6 and the input of the 4th inverter INV4 interconnect; The other end of the 6th capacitor C 6 is connected with ground; Another input of first liang of input nand gate NAND2 and the output of the 4th inverter INV4 interconnect; The input of the output of first liang of input nand gate NAND2 and waveform-shaping module circuit interconnects.
7. a kind of electrify restoration circuit with overall enabling pulse control auto-reset function according to claim 1, it is characterized in that: described waveform-shaping module (6) circuit contains the 5th inverter INV5 and hex inverter INV6, input signal is amplified and shaping, the electrification reset output signal is provided
Waveform-shaping module (6) circuit connects in the following manner:
The input of the output of reseting pulse signal generation module (5) circuit, waveform-shaping module (6) circuit and the input of the 5th inverter INV5 interconnect; The output of the 5th inverter INV5 and the input of hex inverter INV6 interconnect; The output RST of the output of hex inverter INV6 and electrify restoration circuit interconnects.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337846A (en) * | 2013-06-19 | 2013-10-02 | 深圳市元征科技股份有限公司 | Peripheral application circuit |
| CN103716023A (en) * | 2013-12-03 | 2014-04-09 | 北京中电华大电子设计有限责任公司 | Power-on reset circuit with ultra-low power consumption |
| CN106230411A (en) * | 2016-10-14 | 2016-12-14 | 湘潭芯力特电子科技有限公司 | A kind of low-power consumption undersized electrification reset circuit |
| CN106374896A (en) * | 2016-11-04 | 2017-02-01 | 盛科网络（苏州）有限公司 | Power off reset system |
| CN106972846A (en) * | 2017-03-21 | 2017-07-21 | 上海华力微电子有限公司 | A kind of electrification reset circuit |
| WO2019227422A1 (en) * | 2018-05-31 | 2019-12-05 | 华为技术有限公司 | Power on reset circuit and isolated half-bridge driver |
| CN112398328A (en) * | 2020-11-24 | 2021-02-23 | 西安空间无线电技术研究所 | Power supply starting time sequence self-control circuit suitable for complex digital-analog hybrid system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394170A (en) * | 2008-10-29 | 2009-03-25 | 四川登巅微电子有限公司 | Power-on resetting circuit |
| CN101588167A (en) * | 2009-06-18 | 2009-11-25 | 广州润芯信息技术有限公司 | Electrifying reset and undervoltage turnoff circuit |
| CN101826861A (en) * | 2009-12-31 | 2010-09-08 | 国民技术股份有限公司 | Integrated circuit chip containing automatic reset circuit therein |
| CN102403988A (en) * | 2011-12-22 | 2012-04-04 | 中国科学院上海微系统与信息技术研究所 | Power on reset circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
| CN203135824U (en) * | 2013-01-25 | 2013-08-14 | 湘潭芯力特电子科技有限公司 | A power on reset circuit containing a global enabling pulse control automatic reset function |
-
2013
- 2013-01-25 CN CN201310027886.4A patent/CN103066972B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394170A (en) * | 2008-10-29 | 2009-03-25 | 四川登巅微电子有限公司 | Power-on resetting circuit |
| CN101588167A (en) * | 2009-06-18 | 2009-11-25 | 广州润芯信息技术有限公司 | Electrifying reset and undervoltage turnoff circuit |
| CN101826861A (en) * | 2009-12-31 | 2010-09-08 | 国民技术股份有限公司 | Integrated circuit chip containing automatic reset circuit therein |
| CN102403988A (en) * | 2011-12-22 | 2012-04-04 | 中国科学院上海微系统与信息技术研究所 | Power on reset circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
| CN203135824U (en) * | 2013-01-25 | 2013-08-14 | 湘潭芯力特电子科技有限公司 | A power on reset circuit containing a global enabling pulse control automatic reset function |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337846A (en) * | 2013-06-19 | 2013-10-02 | 深圳市元征科技股份有限公司 | Peripheral application circuit |
| CN103716023A (en) * | 2013-12-03 | 2014-04-09 | 北京中电华大电子设计有限责任公司 | Power-on reset circuit with ultra-low power consumption |
| CN103716023B (en) * | 2013-12-03 | 2017-04-05 | 北京中电华大电子设计有限责任公司 | A kind of electrification reset circuit of super low-power consumption |
| CN106230411A (en) * | 2016-10-14 | 2016-12-14 | 湘潭芯力特电子科技有限公司 | A kind of low-power consumption undersized electrification reset circuit |
| CN106374896A (en) * | 2016-11-04 | 2017-02-01 | 盛科网络（苏州）有限公司 | Power off reset system |
| CN106374896B (en) * | 2016-11-04 | 2019-05-31 | 盛科网络（苏州）有限公司 | Power-out reset system |
| CN106972846A (en) * | 2017-03-21 | 2017-07-21 | 上海华力微电子有限公司 | A kind of electrification reset circuit |
| CN106972846B (en) * | 2017-03-21 | 2020-06-16 | 上海华力微电子有限公司 | Power-on reset circuit |
| WO2019227422A1 (en) * | 2018-05-31 | 2019-12-05 | 华为技术有限公司 | Power on reset circuit and isolated half-bridge driver |
| CN112398328A (en) * | 2020-11-24 | 2021-02-23 | 西安空间无线电技术研究所 | Power supply starting time sequence self-control circuit suitable for complex digital-analog hybrid system |
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