CN101387901B - Multi-voltage supply apparatus for considering power starting sequence and power supply enabling circuit thereof - Google Patents
Multi-voltage supply apparatus for considering power starting sequence and power supply enabling circuit thereof Download PDFInfo
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- CN101387901B CN101387901B CN2007101542430A CN200710154243A CN101387901B CN 101387901 B CN101387901 B CN 101387901B CN 2007101542430 A CN2007101542430 A CN 2007101542430A CN 200710154243 A CN200710154243 A CN 200710154243A CN 101387901 B CN101387901 B CN 101387901B
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Abstract
The invention discloses a multi-voltage supply which considers the power supply start sequence and a power supply enabled circuit thereof. The power supply enabled circuit utilizes a state signal feedback output by a target voltage regulator as one of the conditions which control the enabled property of the target voltage regulator, by aid of this, the invention can meet the requirements of enabling different voltage supplies according to the ordered sequence in a computer system standard.
Description
Technical field
The invention relates to a kind of multivoltage supply, and particularly relevant for a kind of multivoltage supply of considering power boot sequence, the status signal that it utilizes the state end of voltage adjuster to be exported, feedback become one of them the condition that whether enables of this voltage adjuster.
Background technology
In various electronic installations inside, often need multiple voltage that operational power is provided.For example computer just needs multiple voltage to offer CPU (central processing unit), north bridge chips, South Bridge chip, storer, peripheral device etc.Because modern age, computer function was become stronger day by day, and in computer system, comprised many different members.These different members can provide different functions, and relative also needs different power supplys and different working times.Therefore also computer system has certain standard for the order that enables of various power supplys in each stage.Regulation is as computer system boot-strap (power in Intel stoakleyPlatform Design Guide, comprise by dormant state S3 and revive) time, the order that enables of its power supply is: power supply unit (power supply) → south bridge 1.5V → north bridge 1.25V → primary memory 1.5V → primary memory 1.8V → 3.3V.
Fig. 1 represents traditional power enable circuit structure figure.As shown in Figure 1, this conventional art be with or door 104 realize power enable circuit 100.Or door 104 first input end is coupled to the state end of 1.5V voltage adjuster 101, and second input end then receives the sleep signal S4_N from South Bridge chip 103.Or the output terminal of door 104 is coupled to the Enable Pin of 1.8V voltage adjuster 202.
In the time of at the beginning of computer enters open state S0 from off-mode, just power supply unit (not illustrating) and South Bridge chip 103 required 1.5V voltage adjusters (not illustrating) are enabled, and the required 1.5V voltage adjuster 101 of primary memory (not illustrating) is not when being enabled as yet, the sleep signal S4_N that South Bridge chip 103 can continue output one noble potential arrives or door 104, and the status signal A3 of the state end of 1.5V voltage adjuster 101 output electronegative potential.According to the regulation of Intel stoakley Platform Design Guide, must 1.5V voltage adjuster 101 be enabled after a period of time (about 1ms～5ms), just can enable 1.8V voltage adjuster 102.Yet, because the sleep signal S4_N that South Bridge chip 103 is exported is a noble potential, will force or door 104 output signal also can become noble potential, enable 1.8V voltage adjuster 102 then.
Above-mentioned behavior pattern has been violated the regulation of Intel Stoakley Platform Design Guide.That is to say, in above-mentioned conventional art, the power supply startup sequence of 1.8V voltage adjuster 102 than the more Zao mistake that is enabled of 1.5V voltage adjuster 101 can take place.
Summary of the invention
The invention provides a kind of power enable circuit, with so that booting computer or when dormant state is revived can correctly provide various voltage enable signals orders.
The invention provides a kind of multivoltage supply,, make computer, can enable needed voltage adjuster according to correct order in start or when dormant state is revived in order to cooperate above-mentioned enable circuits.
The invention provides a kind of power enable circuit, comprising or door, switch and pull-down circuit.Or the first input end of door is coupled to the first state end of first voltage adjuster, and should or the output terminal of door and an Enable Pin of one second voltage adjuster couple.Wherein, the first state end is represented the output state of first voltage adjuster, and whether enables second voltage adjuster by the Enable Pin decision.First end of switch with or second input end of door couple, and second end of this switch is coupled to the second state end of this second voltage adjuster.This switch is controlled by an enable signal, and enable signal is a sleep signal of being sent dormant state S4 by a South Bridge chip.Wherein, the output state of representing this second adjuster by this second state end.Pull-down circuit be coupled to or the door second input end.
The present invention provides a kind of multivoltage supply in addition, comprising first voltage adjuster, second voltage adjuster and power enable circuit are arranged.First voltage adjuster is in order to exporting first voltage, and represents the output state of this first voltage adjuster by the first state end.Second voltage adjuster is in order to exporting second voltage, and represents the output state of this second voltage adjuster by the second state end, and whether enables this second voltage adjuster by the Enable Pin decision.The power enable circuit comprises or door, switch and pull-down circuit.Or the first input end of door is coupled to the first state end of first voltage adjuster, and or the output terminal of door be coupled to the Enable Pin of second voltage adjuster.Switch is controlled by enable signal, and enable signal is the S4 sleep signal of being sent by a South Bridge chip.First end of switch is coupled to or second input end of door, and second end of switch is coupled to the second state end of second adjuster.Pull-down circuit be coupled to or the door second input end.
The present invention is used as the basis for estimation whether this voltage adjuster enables because of adopting the voltage status of voltage adjuster output, and the order that the various voltages according to defining in the standard that therefore can be correct enable starts each voltage adjuster.Finish the demand of system.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is traditional a kind of power enable circuit.
Fig. 2 is a power enable circuit embodiments of the present invention.
Fig. 3 is another embodiment of power enable circuit of the present invention.
Embodiment
Those skilled in the art in the invention can look its demand and apply the present invention to various electronic installations.That is, need multiple voltage that operational power is provided, and the electronic installation of essential considering power boot sequence, all can use the present invention.For convenience of description, all embodiment below will be with computer as enforcement example of the present invention.
First embodiment
Fig. 2 is the system architecture diagram of preferred embodiment of the present invention.The multivoltage supply of present embodiment comprises first adjuster (being 1.5V voltage adjuster 201 at this), second adjuster (being 1.8V voltage adjuster 202 at this) and power enable circuit 200.Power enable circuit 200 comprises or door 204, pull-down circuit 205 and switch 206.1.5V the status signal A3 (for example Power Good signal) that voltage adjuster 201 is exported by its first state end represents the output state (for example pointing out whether the output voltage that 1.5V voltage adjuster 201 is provided meets the rated voltage current potential) of 1.5V voltage adjuster 201.Similar ground, the status signal A1 (for example PowerGood signal) that 1.8V voltage adjuster 202 is also exported by its second state end represents the output state of 1.8V voltage adjuster 202.Wherein, the control that 1.8V voltage adjuster 202 can be by its Enable Pin decides 1.8V voltage adjuster 202 whether be enabled (for example control 1.8V voltage adjuster 202 whether 1.8 volts output voltage is provided).
Illustrate as Fig. 2, first end of switch 206 is coupled to or door 204 second input end, and second end of switch 206 is coupled to the second state end of 1.8V voltage adjuster 202.Wherein, switch 206 is controlled by an enable signal, is to utilize sleep signal S4_N that South Bridge chip 203 exported as this enable signal, with the keying state of gauge tap 206 at this.Therefore, by sleep signal S4_N gauge tap 206, the status signal A1 that can determine whether to make the state end of 1.8V voltage adjuster 202 to be exported is sent to or second input end of door 204.
Or door 204 first input end receives the status signal A3 that the first state end of 1.5V voltage adjuster 201 is exported.Or door 204 second input end is coupled to an end of switch 206, and is coupled to pull-down circuit 205, wherein or the signal of second input end of door 204 be signal A2.Or the output terminal of door 204 then is coupled to the Enable Pin of 1.8V voltage adjuster 202.
The power enable that note that regulation computer system boot-strap (power on) in Intel stoakley Platform Design Guide is in proper order: power supply unit → south bridge 1.5V → north bridge 1.25V → primary memory 1.5V → primary memory 1.8V → 3.3V.In the time of at the beginning of computer enters open state S0 from off-mode, just power supply unit (not illustrating) and South Bridge chip 203 required 1.5V voltage adjusters (not illustrating) are enabled, and the required 1.5V voltage adjuster 201 of primary memory (not illustrating) is not when being enabled as yet, South Bridge chip 203 can continue the control end of the sleep signal S4_N of output one noble potential to switch 206, makes switch 206 be switched on (turn on).At the same time, because 1.5V voltage adjuster 201 all is not enabled as yet with 1.8V voltage adjuster 202, make the 1.5V voltage adjuster 201 and the state end of 1.8V voltage adjuster 202 all export the status signal of electronegative potential.Therefore, or the door 204 control signal A4 that just exports electronegative potential, make 1.8V voltage adjuster 202 remain in disabled state.
Enter the process of open state S0 from off-mode in computer system, when 1.5V voltage adjuster 201 is enabled, 1.5V voltage adjuster 201 is sent, and the status signal A3 of noble potential arrives or the first input end of door 204, has been enabled with expression 1.5V voltage adjuster 201.Or door 204 can also export the Enable Pin of the control signal A4 of a noble potential to 1.8V voltage adjuster 202 after a time delay, make that 1.8V voltage adjuster 202 is enabled therefore.When 1.8V voltage adjuster 202 was enabled and can provides rated voltage, the state end of 1.8V voltage adjuster 202 can be sent the status signal A1 of noble potential.So promptly can finish and open 1.5V voltage adjuster 201, the demand of opening 1.8V voltage adjuster 202 again after delay a period of time when starting shooting in the computer system earlier.And this computer system is in open state S0, and just the sleep signal S4_N that exported of South Bridge chip 203 can remain on noble potential, makes switch 206 keep paths.
Table 1 is the explanation conventional art and the embodiment of the invention shown in Figure 2 shown in Figure 1, the true value comparison sheet of the two.As can be seen from Table 1, the behavior pattern of the power enable circuit 100 of conventional art shown in Figure 1 has been violated the regulation of Intel Stoakley Platform Design Guide.That is to say, when computer is at the beginning of off-mode S5 enters open state S0,1.8V the Enable Pin signal of adjuster 102 can do sth. in advance transition be logical one (standard should be earlier be logical zero, treat that 1.5V adjuster 101 is enabled after, the Enable Pin signal of 1.8V adjuster 102 could transition is logical one).Therefore, the power supply startup sequence of 1.8V voltage adjuster 102 than the more Zao mistake that is enabled of 1.5V voltage adjuster 101 can take place in power enable circuit 100.The power enable circuit 200 of the embodiment of the invention can be observed the standard code of " open 1.5V voltage adjuster 201 earlier, postpone to open 1.8V voltage adjuster 202 again after a period of time ".
The true value comparison sheet of table 1: Fig. 1 and power enable circuit shown in Figure 2.
Please continue with reference to Fig. 2, when computer system will enter dormant state S3 by open state S0, South Bridge chip group 203 will be controlled 1.5V voltage adjuster 201, by this 1.5V voltage adjuster 201 cuts out.Therefore, after entering dormant state S3 fully, 1.5V voltage adjuster 201 is because of being closed the status signal A3 that sends electronegative potential.Because sleep signal S4N can remain on noble potential in dormant state S3, make switch 206 remain on conducting state and make 1.8V voltage adjuster 202 state end institute output logic 1 status signal A1 can via switch 206 with or door 204 and being fed to the Enable Pin of 1.8V voltage adjuster 202.Therefore to maintain enabled state constant for 1.8V voltage adjuster 202.
When computer system will be revived by dormant state S3, South Bridge chip group 203 will enable 1.5V voltage adjuster 201.Therefore status signal A3 changes into noble potential because of 1.5V voltage adjuster 201 is enabled, and so guarantees or the control signal A4 of door 204 outputs must be noble potential, and also 1.8V voltage adjuster 202 remains on enabled state.
When computer system will be shut down, South Bridge chip group 103 will be closed 1.5V voltage adjuster 101, make that the status signal transition of 1.5V voltage adjuster 101 is a logical zero.In addition, South Bridge chip group 103 can be come cutoff switch 206 by the sleep signal S4_N of output electronegative potential.So will make switch 206 for opening circuit, make signal A2 be pulled to electronegative potential because of pull-down circuit 205.Therefore, cause or the control signal A4 of door 204 outputs are low-potential state, and 1.8V voltage adjuster 202 cuts out.
By the premises as can be known, present embodiment can satisfy the requirement of the power supply startup sequence of Intel Stoakley Platform DesignGuide fully.
Second embodiment
Fig. 3 is another embodiment of power enable circuit of the present invention, and power enable circuit 300 comprises or door U302 that the one controllable type impact damper as the switch use (using three-state buffer U301 at this) is as the pull down resistor R301 of pull-down circuit.Disclose as Fig. 3, or second input end, first end and the three-state buffer U301 output terminal three of pull down resistor R301 of door U302 couple jointly.Second end of pull down resistor R301 then is couple to system earth end GND.Or the first input end of door U302 couples the status signal A3 that receipts come from 1.5V voltage adjuster 201 (as shown in Figure 2).Should or the output terminal of door U302 then send control signal A4, with 202 (as shown in Figure 2) of control 1.8V voltage adjuster.The input end of this three-state buffer U301 receives the status signal A1 of 1.8V voltage adjuster 202, and the Enable Pin of this three-state buffer U301 then receives enable signal (being sleep signal S4_N at this).
When computer system entered open state S0 by off-mode, because of 1.5V voltage adjuster 201 can be enabled earlier, the status signal A3 that therefore comes from 1.5V voltage adjuster 201 will be noble potential.Also therefore should or the door signal A2 that U302 exported also be noble potential.Or the control signal A4 of door U302 output can enable 1.8V voltage adjuster 202.This moment, sleep signal S4_N remained on noble potential because of open state S0, made the logical value of the signal A2 of three-state buffer U301 output terminal be equal to the status signal A1 of 1.8V voltage adjuster 202.Because of 1.8V voltage adjuster 202 is enabled, so status signal A1 and signal A2 are all noble potential.
When computer system will enter dormant state S3 by open state S0,1.5V voltage adjuster 201 will be closed, and status signal A3 will close because of 1.5V voltage adjuster 201 and become electronegative potential simultaneously.But, cause signal A2 to keep noble potential (being that its logical value is equal to status signal A1) because the enable signal (being sleep signal S4_N) of three-state buffer U301 still maintains noble potential.Therefore, or the control signal A4 of door U302 output also maintains noble potential, makes 1.8V voltage adjuster 202 keep enabled state.
When computer system will be revived by dormant state S3,1.5V voltage adjuster 201 was enabled again, so the status signal A3 of 1.5V voltage adjuster 201 converts noble potential to, made 1.8V voltage adjuster 202 remain on enabled state.
When computer system will be shut down, 1.5V voltage adjuster 201 was closed, so status signal A3 converts electronegative potential to.In addition, three-state buffer U301 because of sleep signal S4_N transition to electronegative potential, and make the output terminal of three-state buffer U301 be high impedance status.Because the output terminal of three-state buffer U301 is high impedance, so the current potential of signal A2 is by pull down resistor R301 decision, promptly changes into to be electronegative potential.Therefore, or the control signal A4 transition of door U302 output becomes electronegative potential, makes 1.8V voltage adjuster 202 be closed.
By the premises as can be known, the power enable circuit 300 of present embodiment also can satisfy the requirement of the power supply startup sequence of IntelStoakley Platform Design Guide fully.
In sum, the present invention utilizes a ready-made state output signal as feedback control signal, just can simply finish the handoff functionality of the voltage adjuster of each Status Change in the computer system.And can meet the voltage of stipulating among the Intel Stoakley Platform Design Guide and enable order.With under the minimum cost, reach best requirement.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (8)
1. power enable circuit comprises:
One or the door, its first input end is coupled to one first state end of one first voltage adjuster, and should or the output terminal of door be coupled to an Enable Pin of one second voltage adjuster, the output state of wherein representing this first voltage adjuster by this first state end, and whether enable this second voltage adjuster by the decision of this Enable Pin;
One switch, its first end is coupled to second input end of this or door, and second end of this switch is coupled to one second state end of this second voltage adjuster, wherein this switch is controlled by an enable signal, and represent the output state of this second voltage adjuster by this second state end, this enable signal is a sleep signal of being sent dormant state S4 by a South Bridge chip; And
One pull-down circuit is coupled to second input end of this or door.
2. power enable circuit as claimed in claim 1 is characterized in that, this switch is a controllable type impact damper.
3. power enable circuit as claimed in claim 1 is characterized in that this pull-down circuit comprises a resistance, and first end of this resistance is coupled to second input end of this or door, and the second end ground connection of this resistance.
4. multivoltage supply comprises:
One first voltage adjuster in order to exporting one first voltage, and is represented the output state of this first voltage adjuster by one first state end;
One second voltage adjuster in order to exporting one second voltage, and is represented the output state of this second voltage adjuster by one second state end, and whether is enabled this second voltage adjuster by Enable Pin decision; And
One power enable circuit, it comprises:
One or door, its first input end is coupled to the first state end of this first voltage adjuster, and should or the output terminal of door be coupled to the Enable Pin of this second voltage adjuster;
One switch, its first end is coupled to second input end of this or door, and second end of this switch is coupled to the second state end of this second voltage adjuster, and wherein this switch is controlled by an enable signal, and this enable signal is the S4 sleep signal of being sent by a South Bridge chip; And
One pull-down circuit is coupled to second input end of this or door.
5. multivoltage supply as claimed in claim 4 is characterized in that, this first voltage is 1.5V.
6. multivoltage supply as claimed in claim 4 is characterized in that, this second voltage is 1.8V.
7. multivoltage supply as claimed in claim 4 is characterized in that, this switch is a controllable type impact damper.
8. multivoltage supply as claimed in claim 4 is characterized in that this pull-down circuit comprises a resistance, and first end of this resistance is coupled to second input end of this or door, and the second end ground connection of this resistance.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101542430A CN101387901B (en) | 2007-09-10 | 2007-09-10 | Multi-voltage supply apparatus for considering power starting sequence and power supply enabling circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101542430A CN101387901B (en) | 2007-09-10 | 2007-09-10 | Multi-voltage supply apparatus for considering power starting sequence and power supply enabling circuit thereof |
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| Publication Number | Publication Date |
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| CN101387901A CN101387901A (en) | 2009-03-18 |
| CN101387901B true CN101387901B (en) | 2010-11-24 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545521B2 (en) * | 2001-06-29 | 2003-04-08 | International Business Machines Corporation | Low skew, power sequence independent CMOS receiver device |
| CN1960180A (en) * | 2005-10-31 | 2007-05-09 | 中兴通讯股份有限公司 | Clock signal detection circuit |
| CN2938208Y (en) * | 2006-03-20 | 2007-08-22 | 佛山市顺德区顺达电脑厂有限公司 | Power supply sequence control device |
-
2007
- 2007-09-10 CN CN2007101542430A patent/CN101387901B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545521B2 (en) * | 2001-06-29 | 2003-04-08 | International Business Machines Corporation | Low skew, power sequence independent CMOS receiver device |
| CN1960180A (en) * | 2005-10-31 | 2007-05-09 | 中兴通讯股份有限公司 | Clock signal detection circuit |
| CN2938208Y (en) * | 2006-03-20 | 2007-08-22 | 佛山市顺德区顺达电脑厂有限公司 | Power supply sequence control device |
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| Publication number | Publication date |
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| CN101387901A (en) | 2009-03-18 |
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