CN101335513B

CN101335513B - Power-on system construction applicable to multiple power system smart cards

Info

Publication number: CN101335513B
Application number: CN2007101179964A
Authority: CN
Inventors: 马纪丰; 周建锁
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2007-06-27
Filing date: 2007-06-27
Publication date: 2011-03-30
Anticipated expiration: 2027-06-27
Also published as: CN101335513A

Abstract

The invention relates to an electrifying system structure applied to a smart card chip with multi power systems. Circuits with the multi power systems in the chip system are controlled by the structure according to the principle of gradual stabilizing, namely gradual enabling from the electrifying of an external power source, and a subsequent level circuit module is started to work only after the work of a former level circuit module is stable. By the structure, the orderly electrifying and the reliable and stable starting of the internal circuit modules of the smart card can be ensured during electrifying.

Description

It is a kind of that to be applied to many power supplys be the system configuration that powers in the intelligent card chip

Technical field

The present invention is that a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip.

Background technology

Along with the progress of integrated circuit technology, the supply voltage of kernel circuitry progressively reduces in the smart card, and the outer power voltage of smart card specification still remains on 5V, so just exist a plurality of power supplys to be in smart card.The startup that a plurality of power supplys are in power up will influence the stability and the reliability of entire chip system.Each power supply is stable startup and the operate as normal that the normal startup of circuit can guarantee chip system when powering on by effective control.

When two or more power supplys are arranged in the intelligent card chip, each power supply system all will start work successively when starting, and the module under each power supply system also starts.In the former last electric system, just guarantee that by power-on reset signal final system finishes that all there is stable status in each power supply system when resetting, do not guarantee in each module of reseting period operate as normal whether.In actual conditions, may occur finishing and also have partial circuit not have the wrong output of influence of stable or electrification reset when resetting, cause system mistake at last because of power supply etc.

In this structure, utilize and power in order, what guarantee that each module in a plurality of power supplys system can both be orderly starts working, after the previous stage circuit module is stable, just open back one-level circuit module, and then guarantee can be controlled from the power on operating state of each module of beginning of external power source, finish up to system power-on reset; The state of inner each signal all is as can be known when finishing electrification reset like this, and is controlled, just can guarantee reliable and stable the starting working of whole system.

Summary of the invention

The object of the present invention is to provide that a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip.

Structure of the present invention can realize with integrated circuit, circuit structure comprises: the reference circuit that the band output voltage detects, its power supply is external power source VCC, can export stable reference voltage VREF, simultaneously output reference voltage is carried out easy detection and output level skip signal PORU, the reference voltage VREF of this module exports to voltage stabilizing circuit, and it detects the input of output as first Postponement module.

A voltage stabilizing circuit is mainly kernel circuitry stabilized power supply VDD is provided, and comprises an Enable Pin, and circuit is not worked when enable signal is invalid, and this enable signal is provided by the output EN1 of delay circuit; The output VDD of module provides power supply for kernel circuitry and electrify restoration circuit etc.If chip internal also needs another power supply system, then need two voltage stabilizing circuits, its control mode is identical with present voltage stabilizing circuit.

Two delay circuits, delay circuit only postpones rising edge, does not postpone when trailing edge occurring but directly output.Delay circuit 1 input connects the voltage detecting output PORU of reference circuit, output EN1 connects the Enable Pin of voltage stabilizing circuit, the input of while connection delay circuit 2, delay circuit 1 inputs to delay circuit 2 with the rise edge delay of reference circuit voltage detecting output after a period of time, also offer the enable port of voltage stabilizing circuit simultaneously; The output of delay circuit 2 input connection delay circuit 1, the Connect Power Enable Pin of reset circuit of output EN2, delay circuit 2 postpones the Enable Pin of back control electrify restoration circuit again with the rising edge of delay circuit 1 output, simultaneously EN2 can also be used for other core powers systems down analog module enable control.

A core power voltage detecting circuit can be used for electrification reset control, also is used for the voltage detecting of operate as normal simultaneously.This electric circuit inspection voltage is core power voltage, and it is output as and detects the reset signal RESET of output signal after delayed; The Enable Pin of this circuit connects the output EN2 of delay circuit 2, and output is the reset signal RESET of system, and before module enabled after powering on, module was output as low level; Enable to export the rising edge detection signal after the back supply voltage is higher than test point voltage, output back, the delayed back of this rising edge is finished signal as resetting of system and is offered kernel circuitry.

The present invention is that chip power when control need be according to the time of delay of the performance setting delay circuit of benchmark and voltage stabilizing circuit at many power supplys, externally behind the power initiation, reference circuit is started working, after output reference voltage surpasses certain value, reference circuit voltage detecting output output rising edge signal, 1 pair of this signal of delay circuit postpones, and guarantees that the output reference voltage of reference circuit when postponing to finish is basicly stable; The rising edge control voltage stabilizing circuit of delay circuit 1 output this moment is started working, and this rising edge signal begins to postpone in delay circuit 2.By the delay of delay circuit 2, when becoming high level, delay circuit 2 outputs guarantee that the output of voltage stabilizing circuit this moment is also basicly stable; If any core power is that analog circuit enables to be controlled by delay circuit 2 output signals, then this moment, corresponding analog circuit was also started working, comprising the core power voltage detection module, if core power voltage conforms requirement, then testing circuit can be exported a rising edge detection signal, and the delay circuit in the testing circuit is exported this signal delay and finished system reset as systematic reset signal after a period of time.The state that can guarantee all modules wherein when beginning operate as normal in system so all is controlled.

Circuit structure of the present invention is as follows:

The reference circuit of a detection with voltage, its power input is external power source VCC, can export stable reference voltage VREF, the reference voltage output of reference circuit connects the reference voltage input terminal of voltage stabilizing circuit, the input of voltage detecting output PORU connection delay circuit 1.

A voltage stabilizing circuit, power input are external power source VCC, and input provides power vd D for kernel circuitry; Reference voltage input terminal connects the reference voltage output terminal of reference circuit, the output of Enable Pin connection delay circuit 1;

Delay circuit 1, its input connects the voltage detecting output of reference circuit, and output EN1 is as the Enable Pin of voltage stabilizing circuit, and the while is the input of connection delay circuit 2 again, and this delay circuit does not postpone trailing edge only to rise edge delay;

Delay circuit 2, the output of its input connection delay circuit 1, its output EN2 connects the Enable Pin of core power voltage detecting circuit and the Enable Pin of other analog circuits in the internal circuit.

A core power voltage detecting circuit, it detects voltage and is input as core power VDD, enables the output of input connection delay circuit 2, and output connects the reset terminal of internal circuit.

The present invention utilizes reference circuit, and the progressively structure of control of formations such as voltage stabilizing circuit, delay circuit and voltage detecting circuit has realized that a kind of many power supplys are the system configuration that powers in the intelligent card chip, and this structure can be implemented in the integrated circuit.Structure of the present invention is concise flexibly, is easy to realize.This structure is used in intelligent card chip.

Description of drawings

Fig. 1 is the system configuration that powers on that powers in order that the present invention proposes;

Fig. 2 is the orderly electrifying timing sequence that many power supplys that the present invention proposes are fastened the electric system structure;

Specific implementation method

As shown in Figure 1, the kernel circuitry in frame of broken lines, it is the system configuration that powers in the intelligent card chip that other circuit has been formed many power supplys that the present invention proposes.This example is implemented in the integrated circuit of CMOS technology, and external power source VCC is 5 volts, and VCC also finally is stabilized to 5 volts since 0 volt of rising in the power up.

Total comprises: the reference circuit of detection with voltage, voltage stabilizing circuit, two delay circuits, core power voltage detecting circuit; The power supply of reference circuit, voltage stabilizing circuit, delay circuit is an external power source, the reference voltage output terminal of reference circuit offers the reference voltage input terminal of voltage stabilizing circuit, the reference voltage of reference circuit detects the input of output connection delay circuit 1, the output of delay circuit 1 is connected to the Enable Pin of voltage stabilizing circuit, simultaneously also as the input of delay circuit 2; Voltage stabilizing circuit is output as the power supply of kernel circuitry; The output of delay circuit 2 connects the Enable Pin of core power voltage detecting circuit, can also offer other analog circuits in the kernel circuitry simultaneously, as its Enable Pin; The power supply of core power voltage detecting circuit is the output of voltage stabilizing circuit, and output is as the logic reset signal of kernel circuitry.

The operation principle of foregoing circuit is as follows: it is 20us that the setting benchmark is exported the stabilization time that powers on; The setting voltage stabilizing circuit is exported the stabilization time that powers on when a fixed load be 20us; Setting 1 time of delay of delay circuit is 25us, and be 25us the time of delay of delay circuit 2; Be 20us time of delay in the setting voltage testing circuit; Outer power voltage VCC is 5V, voltage stabilizing circuit output 1.8V voltage VDD;

After externally power supply VCC begins to power on, reference circuit is started working, along with the also progressively rising of rising reference circuit output of outer power voltage, near stablizing output valve, the reference voltage of reference circuit detects PORU signal output high level after output voltage values surpasses certain value; The PORU signal is as the input of delay circuit 1, and the reference voltage output of benchmark is stable basically after with this rise edge delay 25us for delay circuit; This moment, delay output signal EN1 enabled voltage stabilizing circuit, voltage stabilizing circuit is started working, the EN1 signal enters delay circuit 2 simultaneously, the rising edge signal of EN1 is postponed, the delay of the 25us of process delay circuit 2, the output VDD of voltage stabilizing circuit was basicly stable when its output EN2 signal became high level, and can guarantee that its supply voltage be stable when being started working by the internal simulation circuit of EN2 control this moment.The core power voltage detecting circuit was started working after the EN2 signal became high level, if DD is normal for the voltage stabilizing circuit output voltage V, then testing circuit can be exported a rising edge signal and this rising edge signal is postponed, offer internal logic as systematic reset signal RESET after postponing, finish all steady operations of each electronic circuits that can guarantee when resetting in two power supplys system in system like this, and then just can guarantee normally stablizing of system.Its working timing figure is seen Fig. 2.

If mistake appears in reference circuit in circuit, then the input of delay circuit the rising edge signal can not occur, and voltage stabilizing circuit will not worked, and whole kernel circuitry will be in electroless state always; If voltage stabilizing circuit goes wrong, if output voltage is on the low side, then the core power voltage detecting circuit will can not exported the rising edge signal, and internal logic circuit also will be in reset mode always, thereby the assurance system misoperation can not occur.

Claims

One kind to be applied to many power supplys be the system configuration that powers in the intelligent card chip, utilized and progressively enabled powering in order of control method realization each circuit module of chip internal, this structure comprises the reference circuit that an output voltage detects, the voltage stabilizing circuit that band enables to control, two delay circuits, a core power voltage detecting circuit, it is characterized in that this structure is according to progressively stable principle, after previous stage circuit module working stability, just allow back one-level circuit module start working, guarantee that each module all just starts working after its input signal is stable, each circuit module can power on and stable the startup in order when guaranteeing to power on.
2. according to claim 1 a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, and it is characterized in that providing power supply with the reference circuit that output voltage detects by outside VCC, even still can export stable reference voltage VREF when VCC changes.
It is 3. according to claim 1 that a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, it is characterized in that when the reference voltage VREF of the reference circuit output of being with output voltage to detect is higher than certain voltage rising edge signal of voltage detecting output output.
It is 4. according to claim 1 that a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, it is characterized in that providing power supply by outside VCC with the voltage stabilizing circuit that enables to control, circuit has the effective Enable Pin of high level, and circuit provides stable power VDD for kernel circuitry.
It is 5. according to claim 1 that a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, it is characterized in that delay circuit only postpones the rising edge signal, the reference circuit that detects by system and band output voltage its time of delay, voltage stabilizing circuit decision stabilization time that band enables to control.
It is 6. according to claim 1 that a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, it is characterized in that the core power voltage detecting circuit core power voltage is detected and postpone output, output provides reset signal RESET for kernel circuitry.
7. according to claim 1 or 6 described a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, it is characterized in that when core power voltage is higher than certain value core power voltage detecting circuit output high level signal, this rising edge signal will be delayed and provide reset signal RESET for kernel circuitry.
8. according to claim 1 or 6 described a kind of to be applied to many power supplys be the system configuration that powers in the intelligent card chip, it is characterized in that the core power voltage detecting circuit only postpones the rising edge signal, the trailing edge signal is not postponed, and time of delay is by system requirements and correlation module decision stabilization time.