CN102111135B - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN102111135B CN102111135B CN 200910202027 CN200910202027A CN102111135B CN 102111135 B CN102111135 B CN 102111135B CN 200910202027 CN200910202027 CN 200910202027 CN 200910202027 A CN200910202027 A CN 200910202027A CN 102111135 B CN102111135 B CN 102111135B
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Abstract
The invention discloses a power-on reset circuit. The power-on reset circuit comprises a voltage regulator module, a power-on reset module and a counter, wherein the voltage regulator module used for processing an external voltage and supplying power to a logic circuit; the power-on reset module is connected with the external voltage and generates a reset signal before the power supply voltage ofa voltage regulator reaches a normal level; and the counter receives a clock signal and the reset signal generated by the power-on reset module, delays the reset signal after the power supply voltagereaches the normal level and outputs the delayed reset signal to the logic circuit. The power-on reset circuit ensures the normal power-on reset of a system by generating a reliable reset signal to an internal logic after ensuring the stability of the voltage output by the voltage regulator module when delaying the power-on reset circuit by adopting the counter.
Description
Technical field
The present invention relates to a kind of electrify restoration circuit.
Background technology
Existing electrify restoration circuit as shown in Figure 1, comprise voltage regulator module (VR, VOLTAGEREGULATOR) and electrification reset module (POR, POWER ON RESET), described voltage adjuster is processed external voltage VCC, for logical circuit and electrification reset module provide operating voltage vpwr, in the described electrification reset module process that voltage raises when powering on logical circuit is sent reset signal rstb, described logic road also provides a voltage regulator module static mode of operation enable signal Standby_en for voltage adjuster.
Generally, the waveform of the power-on reset signal rstb of electrify restoration circuit as shown in Figure 2, Low level effective, when external voltage is reduced to Vtrip_f, system is in power-down state, when external voltage reached Vtrip_r, wherein there was the sluggishness of Vhyst in system power-on reset between Vtrip_f and the Vtrip_r.When external voltage reaches Vtrip_r, the end that resets, internal logic is started working.And the voltage of voltage regulator module output this moment only has Vtrip_r, also do not reach the normal operating voltage of internal logic, although the electrification reset module has been exported an effective rstb signal like this, but logical gate is not because voltage also reaches normal working voltage and just can not receive normally this reset signal, and this just may cause internal logic can not normally reset in power up.
Summary of the invention
Technical problem to be solved by this invention provides a kind of electrify restoration circuit, guarantees behind the voltage stabilization of voltage regulator module output, to produce again a reliable reset signal to internal logic, thus the normal electrification reset of assurance system.
For solving the problems of the technologies described above, the technical scheme of electrify restoration circuit of the present invention is to comprise:
Voltage regulator module is processed external voltage, is power logic circuitry;
The electrification reset module, described electrification reset module connects external voltage, and produces a reset signal before the supply power voltage of voltage adjuster reaches normal level;
Counter receives the reset signal that a clock signal and described electrification reset module produce, and the described reset signal supply power voltage of delaying time is exported to logical circuit after reaching normal level.
The present invention guarantees to produce a reliable reset signal to internal logic behind the voltage stabilization of voltage regulator module output by adopting a counter to delay time for electrify restoration circuit again, thus the normal electrification reset of the system that guaranteed.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the structure chart of existing electrify restoration circuit;
Fig. 2 is the oscillogram of existing electrify restoration circuit when resetting;
Fig. 3 is the structure chart of an embodiment of electrify restoration circuit of the present invention;
Fig. 4 is the structure chart of another embodiment of electrify restoration circuit of the present invention;
Fig. 5 is the oscillogram of electrify restoration circuit of the present invention when resetting.
Embodiment
The invention discloses a kind of electrify restoration circuit, as shown in Figure 3, comprising:
Voltage regulator module, VCC processes to external voltage, for logical circuit provides operating voltage Vpwr;
The electrification reset module, described electrification reset module connects external voltage VCC, and produces a reset signal POR before the supply power voltage of voltage adjuster reaches normal level;
Counter receives the reset signal POR that a clock signal clk and described electrification reset module produce, and the described reset signal POR supply power voltage of delaying time is reached after the normal level, and rstb is to logical circuit for the output reset signal.
In the embodiment shown in fig. 3, the clock signal clk of described counter connection is external timing signal.
In the embodiment shown in fig. 4, also comprise oscillator module, the clock signal clk that described counter receives is produced by described oscillator module.
Described oscillator module provides clock signal clk for described logical circuit simultaneously.
Described oscillator module comprises that a beginning can hold, and the signal OSCEN that this beginning can hold is provided by described logical circuit.
In conjunction with shown in Figure 5, electrification reset module sum counter adopts the external voltage power supply, and the voltage adjuster output voltage is to logical circuit, oscillator module and other module for power supply.When the output voltage of voltage adjuster rises to the operating voltage of logical circuit and oscillator module gradually, logical circuit can hold OSCEN control generator module to begin clock signal to counter by beginning, reset signal rstb exports low always in this process, when counting arrives predetermined value, the rstb signal of logic counting circuit output discharges, the high logical circuit (rstb Low level effective) of giving of output, through such delay process, at this moment the voltage adjuster output voltage has reached the logical circuit normal working voltage, thereby guarantees a reliable and effective power-on reset signal is offered logical circuit.The present invention can be applied in the electrify restoration circuit of EE130 serial EEPROM chip and other logical circuit.
In sum, the present invention guarantees to produce a reliable reset signal to internal logic behind the voltage stabilization of voltage regulator module output by adopting a counter to delay time for electrify restoration circuit again, thus the normal electrification reset of the system that guaranteed.
Claims (5)
1. an electrify restoration circuit is characterized in that, comprising:
Operating voltage is processed and provided to voltage regulator module to external voltage, described operating voltage is connected to logical circuit also is described power logic circuitry;
The electrification reset module, described electrification reset module connects external voltage, and produces a reset signal before the described operating voltage that provides of described voltage regulator module reaches normal level;
Counter, receive the reset signal that a clock signal and described electrification reset module produce, the described reset signal described operating voltage of delaying time is exported to described logical circuit after reaching normal level, described logical circuit produces under the effect of described reset signal and resets, and described logical circuit is started working under the power supply of described operating voltage after the end that resets.
2. electrify restoration circuit according to claim 1 is characterized in that, the clock signal that described counter connects is external timing signal.
3. electrify restoration circuit according to claim 1 is characterized in that, also comprises oscillator module, and the clock signal that described counter receives is produced by described oscillator module.
4. electrify restoration circuit according to claim 3 is characterized in that, described oscillator module provides clock signal for described logical circuit simultaneously.
5. electrify restoration circuit according to claim 3 is characterized in that, described oscillator module comprises that a beginning can hold, and the signal that this beginning can hold is provided by described logical circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910202027 CN102111135B (en) | 2009-12-24 | 2009-12-24 | Power-on reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910202027 CN102111135B (en) | 2009-12-24 | 2009-12-24 | Power-on reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102111135A CN102111135A (en) | 2011-06-29 |
| CN102111135B true CN102111135B (en) | 2013-10-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910202027 Active CN102111135B (en) | 2009-12-24 | 2009-12-24 | Power-on reset circuit |
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| CN (1) | CN102111135B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832915B (en) * | 2012-08-23 | 2015-07-15 | 中国科学院微电子研究所 | Programmable power-on reset system |
| CN104579266A (en) * | 2014-11-14 | 2015-04-29 | 深圳市芯海科技有限公司 | Circuit system and power-on resetting method thereof |
| CN105322918A (en) * | 2015-10-21 | 2016-02-10 | 深圳市芯海科技有限公司 | Method for reducing power consumption of power-on process |
| CN106843435A (en) * | 2016-12-21 | 2017-06-13 | 深圳市紫光同创电子有限公司 | A kind of chip reset circuit and method for PLD |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323066A (en) * | 1992-06-01 | 1994-06-21 | Motorola, Inc. | Method and apparatus for performing power on reset initialization in a data processing system |
| US7057427B2 (en) * | 2004-07-15 | 2006-06-06 | Freescale Semiconductor, Inc | Power on reset circuit |
| CN101436095A (en) * | 2007-11-13 | 2009-05-20 | 无锡华润矽科微电子有限公司 | Low voltage resetting method for microcontroller |
| CN101562393A (en) * | 2008-09-10 | 2009-10-21 | 西安民展微电子有限公司 | Secondary startup control circuit and switching power supply |
-
2009
- 2009-12-24 CN CN 200910202027 patent/CN102111135B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323066A (en) * | 1992-06-01 | 1994-06-21 | Motorola, Inc. | Method and apparatus for performing power on reset initialization in a data processing system |
| US7057427B2 (en) * | 2004-07-15 | 2006-06-06 | Freescale Semiconductor, Inc | Power on reset circuit |
| CN101436095A (en) * | 2007-11-13 | 2009-05-20 | 无锡华润矽科微电子有限公司 | Low voltage resetting method for microcontroller |
| CN101562393A (en) * | 2008-09-10 | 2009-10-21 | 西安民展微电子有限公司 | Secondary startup control circuit and switching power supply |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2004-260648A 2004.09.16 |
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| Publication number | Publication date |
|---|---|
| CN102111135A (en) | 2011-06-29 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |