CN112613260B

CN112613260B - Asynchronous clock synchronization constraint method in chip design

Info

Publication number: CN112613260B
Application number: CN202011502006.0A
Authority: CN
Inventors: 赵庆哲
Original assignee: No47 Institute Of China Electronics Technology Group Corp
Current assignee: No47 Institute Of China Electronics Technology Group Corp
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2024-04-23
Anticipated expiration: 2040-12-18
Also published as: CN112613260A

Abstract

The invention relates to a new theoretical method for synchronizing constraint of an asynchronous clock in a chip design process. Aiming at the chip circuit design of MCU and SOC scale, under the condition that a large amount of asynchronous clocks are inevitably existed, when the design is subjected to time sequence constraint, the synchronous concept and thought are adopted, the asynchronous clock constraint in the design is subjected to synchronous normalization processing, and the chip circuit is constrained by the synchronous normalization processing. On the premise of meeting the design requirement, the iteration time from logic synthesis to gate level simulation after layout and wiring of the chip design is reduced to the greatest extent, so that the time cost of the chip design is reduced greatly, and the chip marketing speed is accelerated. Through verification of a certain chip design, compared with a common chip constraint method, the method has obvious advantages and obtains excellent effects.

Description

Asynchronous clock synchronization constraint method in chip design

Technical Field

The invention belongs to the field of chip design realization, and provides a novel theoretical method for synchronizing design constraint aiming at an asynchronous clock in a chip.

Background

The current chip design is developed towards high integration and complex functions, especially the design of MCU and SoC. Multiple functional IP cores are integrated on one microchip, implementing complex functions. This makes the clock structure of the chip extremely complex, not only increases the number of clocks, but also contains many asynchronous clocks, and the existence of these asynchronous clocks makes the timing constraint of the design particularly difficult. In logic design, the use of asynchronous clocks or the synchronization of asynchronous clocks should be avoided as much as possible. However, in the actual design process of the current large-scale chip, the asynchronous clock is unavoidable, and once the constraint of a certain asynchronous clock is misplaced due to omission, the problem of design time sequence can be caused, and the whole design is further caused to fail, which is not only the loss of the cost of streaming, but also the increase of the time cost of the product, and sometimes even disastrous. Therefore, how to deal with the timing constraint problem of these asynchronous clocks is an important discussion of chip design implementation personnel.

Disclosure of Invention

The invention aims to provide a novel chip design time sequence constraint theoretical method, which is used for synchronously constraining an asynchronous clock in chip design, so that the whole chip design completes circuit optimization under the constraint of the synchronous clock. The theory and the method have the greatest characteristics that the clock constraint of the whole chip design is a synchronous clock tree system formed by a plurality of frequency division clocks under a main clock, and the chip design is used for succinctly and efficiently optimizing the time sequence of the circuit under the constraint of the clock tree. Pseudo-path processing for asynchronous clocks in conventional timing constraints is omitted. The method not only reduces the burden of logic designers, but also greatly reduces the error probability of time sequence constraint, thereby greatly avoiding iteration between front-end design and the realization of the back simulation of the gate-level netlist, and greatly reducing the time cost of chip design.

The technical scheme adopted by the invention for achieving the purpose is as follows:

a synchronous constraint method for asynchronous clocks in chip design selects one clock of multiple asynchronous clocks as a master clock, and other clocks as frequency division clocks of the master clock to form a plurality of synchronous clock architectures under the master clock so as to complete synchronous of the asynchronous clocks.

The clock selected as the master clock is the highest frequency clock in the plurality of asynchronous clocks, so that the asynchronous clock synchronization is constrained to the highest clock frequency.

Each clock is set as a corresponding n times frequency division clock of the master clock, and n is an integer, so that the clock forms a synchronous clock architecture from the master clock to the frequency division clock.

When the frequency division coefficient of each frequency division clock is selected, the principle of the maximum frequency division coefficient is adopted, and the maximum frequency division coefficient n=max { n ₁,n₂,n₃...n_max } is selected from the frequency division coefficients which can be selected.

The frequency of the master clock is equal to or higher than the highest frequency in the asynchronous clock and is an integer.

The frequency as the master clock can be divided by 10.

The frequency of each frequency division clock is greater than or equal to the frequency of the clock and is an integer.

The frequency of each divided clock can be divided by the frequency of the master clock.

The invention has the following beneficial effects and advantages:

1. the invention adopts the synchronization idea to restrict the clock of the chip design, and can be used as a general clock restriction method, so that logic designers do not need to specially conduct the time sequence planning of the asynchronous clock, and the design time is shortened.

2. The invention adopts the synchronization idea to restrict the clock of the chip design, so that the clock restriction of the chip design is simple and efficient, and the problems are easy to find and correct.

3. The invention adopts the synchronization idea to restrict the clock of the chip design, and each part of the chip design is under the restriction of the synchronous clock, thus omitting the pseudo path processing mode aiming at the asynchronous clock independently, reducing the error rate of the restriction greatly and realizing the complete coverage of the clock restriction.

4. The invention adopts the synchronization idea to restrict the clock of the chip design, and realizes complete coverage of the clock restriction, so that once passing can be realized in the post-simulation process of the gate netlist after the static time sequence analysis passes, no repeated iteration of the design is caused, and the time cost of the design is greatly saved.

Drawings

FIG. 1 is a schematic diagram of asynchronous clock synchronization constraints;

FIG. 2 is a diagram of a multi-clock selection process.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

The invention provides a timing constraint theoretical method for asynchronous clock synchronization, which performs synchronization processing on an asynchronous clock in design in timing constraint, and achieves a very good effect in practice. The theoretical approach may be used as a general clock constraint approach.

1. When the chip design is subjected to time sequence constraint, the concept of a synchronous circuit is adopted, synchronous clock declaration is taken as a central idea, and an asynchronous clock in the chip design is constrained to be a frequency division clock of a master clock, so that the asynchronous clock is converted into the synchronous clock, a plurality of synchronous clock architectures under the master clock are formed, and further the chip design synchronization time sequence constraint is completed.

2. The designed clock network architecture is determined, and through deep analysis of the designed architecture, especially the clock structure, the designed main clock frequency and the relation of each clock (synchronous/asynchronous) are defined, namely, on a circuit, how each clock is matched with each other to complete the data flow of the circuit, and on the time sequence, whether each clock has a phase difference or not is determined.

3. The clock structure is considered from the synchronous central thought and point of view, and each designed clock is declared to be a corresponding n times (n is an integer) frequency division clock of the master clock by a command of time sequence constraint, so that the clock structure forms a complete synchronous clock tree structure from the master clock to the frequency division clock.

And 4, setting a selection terminal to select the maximum clock frequency for a multi-path selection clock structure existing in the design, so that the design is limited to the maximum clock frequency as much as possible.

5. For the selection of the frequency division coefficient of each frequency division clock, the principle of maximum frequency division coefficient should be adopted, that is, the maximum frequency division coefficient n=max { n1, n2, n3...n (max) }, for example, the main clock frequency is 40MHz, the destination clock of the synchronization process is 9MHz, and then the frequency division coefficient is n= {1,2,4,8,10} =10, that is, the clock is constrained by using a clock of 10 MHz.

The theoretical method of synchronization constraint of asynchronous clocks in the chip design process has the central ideas and principles as shown in fig. 1:

Assume that there are four asynchronous clocks in the figure in one chip design, with frequencies of 76MHz, 35MHz, 18MHz, 9MHz, respectively. According to the theoretical method of asynchronous clock synchronization processing, the master clock of the chip design is first determined, and generally, the clock with the highest frequency, here 72MHz, is selected. For a 35MHz clock, the constraint should be 40MHz, namely (80/2) MHz, for an 18MHz clock, the constraint should be 20MHz, namely (80/4) MHz, and for a 9MHz clock, the constraint should be 10MHz, namely (80/8) MHz, so that the clock system constrained by the whole chip design is a complete synchronous clock architecture system taking 80MHz clock as a main clock and 40MHz, 20MHz and 10MHz clocks as frequency division clocks.

For the problem of multiple clock selections, the processing method is as shown in fig. 2: in the figure, four asynchronous clocks of 76MHz, 35MHz, 18MHz and 9MHz are selected as one path according to the requirement in the chip design, the clock with the highest frequency is selected as the master clock of clock constraint according to the rule of the invention, the 76MHz clock is selected, after being selected, the clock is constrained to 80MHz clock through synchronization constraint processing, the clock is used as the master clock frequency of the whole design constraint, and other clocks are subjected to frequency division constraint by taking the clock as a reference.

It should be noted that, whether the master clock or the divided clock after clock constraint is provided, the frequency should be as small as possible on the premise of meeting the rule of the present invention, for example, 76MHz may be constrained by 80MHz and 90MHz, but may be constrained by 80 MHz. Thus, unnecessary area waste caused by the increase of frequency can be reduced as much as possible, and the optimal result of time sequence/area is achieved.

Claims

1. A method for restraining asynchronous clock synchronization in chip design is characterized in that one clock of a plurality of asynchronous clocks is selected as a master clock, other clocks are used as frequency division clocks of the master clock, a plurality of synchronous clock structures under the master clock are formed, and asynchronous clock synchronization is completed;

Setting each clock as a corresponding n times frequency division clock of the master clock, wherein n is an integer, so that the clock forms a synchronous clock architecture from the master clock to the frequency division clock;

When the frequency division coefficient of each frequency division clock is selected, the principle of the maximum frequency division coefficient is adopted, and the maximum frequency division coefficient n=max { n ₁,n₂,n₃...n_max } is selected from the frequency division coefficients which can be selected;

The frequency as the master clock can be divided by 10.

2. The method of claim 1, wherein the selected clock as the master clock is a highest frequency clock among the plurality of asynchronous clocks, such that the asynchronous clock is synchronously constrained to the highest clock frequency.

3. The method of claim 1, wherein the frequency of the master clock is equal to or higher than the highest frequency of the asynchronous clocks and is an integer.

4. The method of claim 1, wherein the frequency of each divided clock is greater than or equal to the frequency of the clock and is an integer.

5. The method of claim 1, wherein the frequency of each divided clock is divisible by the frequency of the master clock.