CN112732619B - Communication training method and device for high-speed LVDS interface - Google Patents
Communication training method and device for high-speed LVDS interface Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F2213/0002—Serial port, e.g. RS232C
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a high-speed LVDS interface communication training method and a device, wherein, before word alignment is carried out in the training process, the second end sampling clock phase with the largest timing margin is acquired, and the acquisition method comprises the following steps: the second end sampling clock phase with stable sampling value is used as candidate sampling clock phase, a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling value with the largest occurrence number of the same stable sampling value is used as an optimal sampling window of the second end sampling clock, and the phase median of the optimal sampling window is used as the second end sampling clock phase with the largest timing margin. According to the invention, the optimal sampling interval capable of stably sampling and the optimal sampling phase in the optimal sampling interval are found in the training stage, and the maximum shaking interval is reserved at the left and right sides of the sampling point position, so that the change of the sampling window caused by the change of the working environment is resisted, and the stability and the accuracy of sampling are improved to the greatest extent.
Description
Technical Field
The invention relates to the technical field of LVDS communication, in particular to a high-speed LVDS interface communication training method and device.
Background
With the updating of products, the requirement on data volume is higher and higher, and high speed and high bandwidth become unavoidable technical terms in product design. This introduces a high-speed interface communication technology, one of which is an LVDS interface communication technology, and has the characteristics of low power consumption, low bit error rate, low crosstalk, low radiation, and the like. The method has wide application in connection modes such as plate-to-plate, plate-to-plate and the like, and the highest speed can reach 3.125Gbps. LVDS communication can ensure the stability and correctness of sampled data.
However, due to the wiring difference between the transmitting end and the receiving end, when the receiving end samples the data with the clock signal, the setup time is not necessarily satisfied or the setup time is smaller, so that the data cannot be correctly acquired. Therefore, no matter what communication method is, training is performed before the LVDS transmitting end and the receiving end communicate, and the advantages and disadvantages of the training method are important to the stability and the correctness of the communication. The training step of LVDS basically comprises the steps that a transmitting end firstly transmits a training code, a receiving end samples the training code, the phase difference between a sampling clock and data is adjusted, the sampled data is stable, sliding bits are compared with the training code, and after the sliding bits are consistent with the training code, training is considered to be successful. In practice, many training methods ignore whether the phase difference between the sampling clock and the data is optimal, and after a long period of operation, the working environment changes, and the phase difference between the sampling clock and the data changes, that is, the sampling window changes, which may cause error code to occur.
Disclosure of Invention
The embodiment of the invention provides a high-speed LVDS interface communication training method and device, which can acquire an optimal sampling interval capable of stably sampling in a training stage, further acquire an optimal sampling point in the optimal sampling interval, and realize that the maximum shaking interval is left around the sampling phase of a second end sampling clock, so that the stability and the accuracy of sampling are improved to the greatest extent. The technical scheme is as follows:
in a first aspect, a high-speed LVDS interface communication training method is provided, and word alignment is performed after a second end sampling clock phase with a maximum timing margin is obtained for bit alignment;
the method for acquiring the second end sampling clock phase with the maximum timing margin comprises the following steps: the second end sampling clock phase with stable sampling value is used as candidate sampling clock phase, a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling value with the largest occurrence number of the same stable sampling value is used as an optimal sampling window of the second end sampling clock, and the phase median of the optimal sampling window is used as the second end sampling clock phase with the largest timing margin.
In one possible implementation manner, the sampling value stabilized second end sampling clock phase is used as a candidate sampling clock phase, which includes:
the delay adjusting unit of the second end generates a plurality of sampling clocks with different phases to sample the training codes continuously sent by the first end;
in the case where the sampling value at the sampling clock of one phase is stable, the phase of the sampling clock and the stable sampling value are recorded.
In one possible implementation manner, the delay adjusting unit of the second end generates a plurality of sampling clocks with different phases, which means that:
and under the condition that the adjustable range of the delay adjusting unit at the second end is D, a fixed value is taken as a sampling clock phase stepping value to generate a plurality of sampling clocks with the phase values uniformly distributed in (0, D).
In one possible implementation manner, the method for obtaining the optimal sampling window of the second end sampling clock includes:
under the condition that the same stable sampling value is recorded for the maximum number of times, acquiring the phase position in each record corresponding to the sampling value;
and acquiring a continuous phase interval consisting of a plurality of phases as an optimal sampling window.
In one possible implementation manner, the method for obtaining the optimal sampling window of the second end sampling clock further includes:
record each stable sampling value Q i Number of occurrences T j ；
If T j Corresponding to the maximum value of the stable sampling value Q imt Two are provided, and the sampling value Q is stabilized according to the later imt And corresponding to the phase in each record, acquiring a continuous phase interval formed by a plurality of phases as an optimal sampling window of the second end sampling clock.
In one possible implementation manner, the method for performing word alignment includes:
and sliding the sampling training code when the phase of the sampling clock at the second end is the phase median of the optimal sampling window until the sampling training code after sliding is consistent with the actual training code sent by the first end, keeping the position of the sliding bit, and finishing training, wherein the upper limit of the sliding bit operation times is the bit width of the training code.
In a second aspect, there is provided a high-speed LVDS interface communication training apparatus, including:
the bit alignment module is used for obtaining the second end sampling clock phase with the largest timing margin to perform bit alignment, and the method for obtaining the second end sampling clock phase with the largest timing margin comprises the following steps: the second end sampling clock phase with stable sampling value is used as candidate sampling clock phase, a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling value with the largest occurrence number of the same stable sampling value is used as an optimal sampling window of the second end sampling clock, and the phase median of the optimal sampling window is used as the second end sampling clock phase with the largest timing margin.
And the word alignment module is used for performing word alignment after performing bit alignment.
In a third aspect, there is provided a computer device, the electronic device comprising:
a memory for storing executable instructions;
and the processor is used for realizing the high-speed LVDS interface communication training method when running the executable instructions stored in the memory.
In a fourth aspect, a computer readable storage medium is provided storing executable instructions that when executed by a processor, the method of training high-speed LVDS interface communication as described above.
The high-speed LVDS interface communication training method has the following beneficial effects:
1. the high-speed LVDS interface communication training method can acquire the optimal sampling interval capable of stably sampling in a training stage, further acquire the optimal sampling point in the optimal sampling interval, and realize that the maximum shaking interval, namely the maximum timing margin, is reserved around the sampling phase of the second end sampling clock so as to resist the change of a sampling window after the working environments such as temperature, voltage, humidity and the like are changed, thereby improving the stability and the accuracy of sampling to the greatest extent.
2. The high-speed LVDS interface communication training method is suitable for a source synchronous communication method and a system synchronous communication method.
3. According to the high-speed LVDS interface communication training method, the whole delay adjustment interval D is directly traversed, after sampling is carried out on sampling clocks of all different phases, an optimal sampling window is screened according to sampling value stability judgment and stable sampling value recording conditions of the sampling clocks of each phase, then an optimal sampling phase is determined, bit alignment is carried out, bit slide bit operation is directly carried out after the optimal sampling phase is confirmed, word alignment is carried out until slide bit is successful or fails, and phase delay adjustment of the sampling clocks is not carried out again.
4. The invention has simple training steps, and the phase delay adjustment of the sampling clock and the bit slip are operated separately.
Drawings
FIG. 1 is a flow chart of a method of obtaining a second end sampling clock phase with a maximum timing margin in the present invention;
FIG. 2 is a block diagram of a system synchronous LVDS communication transmission system implementing a high-speed LVDS interface communication training method;
fig. 3 is a block diagram of a source synchronous LVDS communication transmission system implementing a high-speed LVDS interface communication training method.
Detailed Description
The present invention will be further described in detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent, and the described embodiments should not be construed as limiting the present invention, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.
Referring to fig. 2 and 3, in the system synchronous LVDS communication transmission system and the source synchronous LVDS communication transmission system, a phase-locked loop of a transmitting end generates a parallel clock clk_p1 and a serial clock clk_s1, the parallel clock is used for generating parallel data p_data1, and the serial clock is used for realizing parallel-to-serial conversion to generate serial data s_data. The phase-locked loop of the LVDS receiving end generates a parallel clock clk_p2 and a serial clock clk_s2, the frequency of the serial clock clk_s2 is equal to clk_s1, and the frequencies of the parallel clocks clk_p2 and clk_p1 are equal. The serial data s_data enter a serial-parallel conversion module through a delay unit, and the serial clock clk_s2 is used for sampling the serial data s_data, so that serial-parallel conversion is realized, and parallel data p_data2 is obtained.
In the system synchronous LVDS communication transmission system of fig. 2, the LVDS transmitting end and the receiving end use a clock CLK output by the same clock chip as a reference clock, the LVDS transmitting end uses the reference clock CLK as an input of a phase-locked loop, the LVDS receiving end uses the reference clock CLK as an input of the phase-locked loop, when the receiving end samples data, a phase difference between serial data s_data and serial clock clk_s2 is stable, and when LVDS training is performed, a sampling window of the LVDS receiving end is adjusted by adjusting a delay unit, so that stability and accuracy of sampled data are improved.
In the source synchronous LVDS communication transmission system of fig. 3, the LVDS transmitting end and the receiving end use different reference clocks, the LVDS transmitting end uses a local reference clock CLK as an input of a phase-locked loop, the receiving end uses a pair of differential associated clocks s_data_clk transmitted along with transmission data as a reference source to sample the data, when the receiving end samples the data, the phase difference between the serial data s_data and the serial clock clk_s2 is stable, and when the LVDS training is performed, the sampling window of the LVDS receiving end is adjusted by adjusting the delay unit, so that the stability and the accuracy of the sampled data are improved.
In this embodiment, the sampling window of the LVDS receiving end is optimized by adjusting the delay unit, so as to obtain an optimal sampling phase of the sampling clock of the LVDS receiving end, so that the phase difference between the data received by the LVDS receiving end and the sampling clock is optimal.
Referring to fig. 1, the phase difference between the sampling clock and the data is found to be optimal, that is, the high-speed LVDS interface communication training method of this embodiment, firstly, the phase of the sampling clock at the second end with the largest timing margin is acquired for bit alignment, and then word alignment is performed; the method for acquiring the second end sampling clock phase with the largest timing margin comprises the following steps: the second end sampling clock phase with stable sampling value is used as candidate sampling clock phase, a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling value with the largest occurrence number of the same stable sampling value is used as an optimal sampling window of the second end sampling clock, and the phase median of the optimal sampling window is used as the second end sampling clock phase with the largest timing margin.
By the high-speed LVDS interface communication training method, an optimal sampling interval capable of stably sampling can be obtained in a training stage, and then an optimal sampling point in the optimal sampling interval is obtained, so that the maximum shaking interval, namely the maximum timing margin, is reserved around the sampling phase of the sampling clock at the second end, and is used for resisting the change of a sampling window after the working environments such as temperature, voltage, humidity and the like are changed, and the stability and the accuracy of sampling are improved to the greatest extent.
In this embodiment, a continuous phase interval formed by a plurality of second-end sampling clock phases corresponding to the same stable sampling value with the largest occurrence number is used as an optimal sampling window of the second-end sampling clock, so that erroneous judgment of using only the sampling clock phase corresponding to the stable sampling value as an effective sampling phase of the second-end sampling clock is avoided.
Further, the step of taking the second sampling clock phase with the stable sampling value as the candidate sampling clock phase includes:
under the condition that the adjustable range of the delay adjusting unit at the second end is D, a fixed value is used as a sampling clock phase stepping value to generate a plurality of sampling clocks with phase values uniformly distributed in (0, D), and the plurality of phase distributions comprise 0-degree phases;
the first end continuously transmits the training code,
sampling training codes continuously transmitted by a first end by a plurality of sampling clocks with different phases generated by a delay adjusting unit of a second end;
under the condition that sampling values of sampling clocks with one phase are stable, recording the phase of the sampling clock and the stable sampling values, for example, the phases of a plurality of sampling clocks with even phase distribution are respectively 0, 45, 90, 135, … … and 315 degrees, sampling continuous M training codes sent by a first end by using the sampling clock with the phase of 0 degrees, recording the phase of the sampling clock and the stable sampling values if the continuous M data sampled are stable values, then sampling the continuous M training codes sent by the first end by using the sampling clocks with the phase of 45 degrees, 90 degrees, 135 degrees and … …, and carrying out sampling value stability judgment and recording;
further, after sampling by all the sampling clocks with different phases, the method for obtaining the optimal sampling window of the second end sampling clock according to the recorded stable sampling values and the sampling clock phase corresponding to each stable sampling value includes:
record each stable sampling value Q i Number of occurrences T j ；
Under the condition that the same stable sampling value is recorded for the maximum number of times, acquiring the phase position in each record corresponding to the sampling value;
a continuous phase interval of multiple phases is obtained as an optimal sampling window to filter out candidate sampling clock phases that are stable in sample values but are not actually sampling phases.
Of course, there may be two stable sampling values that appear the same maximum number of times at the same time, and at this time, the method for obtaining the optimal sampling window of the second end sampling clock is as follows:
if T j Corresponding to the maximum value of the stable sampling value Q imt Two are provided, and the sampling value Q is stabilized according to the later imt And corresponding to the phase in each record, acquiring a continuous phase interval formed by a plurality of phases as an optimal sampling window of the second end sampling clock.
According to the optimal sampling window of the second end sampling clock, taking the phase median of the optimal sampling window as the optimal sampling phase of the second end sampling clock to perform bit alignment, and performing word alignment after the bit alignment comprises the following steps:
and sliding the sampling training code when the phase of the sampling clock at the second end is the phase median of the optimal sampling window until the sampling training code after sliding is consistent with the actual training code sent by the first end, keeping the position of the sliding bit, and finishing training, wherein the upper limit of the sliding bit operation times is the bit width of the training code.
According to the high-speed LVDS interface communication training method, the whole delay adjustment interval D is directly traversed, after sampling is carried out on sampling clocks with different phases, an optimal sampling window is screened according to sampling value stability judgment and stable sampling value recording conditions of the sampling clocks with each phase, then an optimal sampling phase is determined, bit alignment is carried out, bit slide sliding operation is directly carried out after the optimal sampling phase is confirmed, word alignment is carried out until sliding is successful or fails, and phase delay adjustment of the sampling clocks is not carried out again.
Based on the above-mentioned high-speed LVDS interface communication training method, this embodiment also provides a high-speed LVDS interface communication training device, including:
the bit alignment module is used for obtaining the second end sampling clock phase with the largest timing margin to perform bit alignment, and the method for obtaining the second end sampling clock phase with the largest timing margin comprises the following steps: the second end sampling clock phase with stable sampling value is used as candidate sampling clock phase, a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling value with the largest occurrence number of the same stable sampling value is used as an optimal sampling window of the second end sampling clock, and the phase median of the optimal sampling window is used as the second end sampling clock phase with the largest timing margin.
And the word alignment module is used for performing word alignment after performing bit alignment.
It should be noted that: when the high-speed LVDS interface communication training device provided in this embodiment is used for training, only the division of the above functional modules is used for illustration, and in practical application, the above functional allocation may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the specific limitation of the high-speed LVDS interface communication training device may be referred to above as limitation of the high-speed LVDS interface communication training method, and will not be described herein.
Based on the above-mentioned high-speed LVDS interface communication training method, the embodiment further provides a computer device, which is characterized in that the electronic device includes:
a memory for storing executable instructions;
and the processor is used for realizing the high-speed LVDS interface communication training method when running the executable instructions stored in the memory.
Based on the above-mentioned high-speed LVDS interface communication training method, the present embodiment further provides a computer readable storage medium storing executable instructions, where the executable instructions implement the above-mentioned high-speed LVDS interface communication training method when executed by a processor.
The computer equipment provided by the embodiment of the invention comprises: at least one processor, memory, a user interface, and at least one network interface, wherein the processor is configured to provide computing and control capabilities;
the memory includes a non-volatile storage medium and an internal memory. The nonvolatile storage medium stores an operating system, an electronic program, and a database for storing LVDS interface communication data and the like. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media.
The network interface of the electronic device is used for communicating with an external terminal through a network connection. The computer program when executed by the processor implements the high-speed LVDS interface communication training method described above.
In addition, the various components in the electronic device are coupled together by a bus system, which is understood to enable connected communication between the components. The bus system includes a power bus, a control bus, and a status signal bus in addition to the data bus. The user interface may include, among other things, a display, keyboard, mouse, trackball, click wheel, keys, buttons, touch pad, or touch screen, etc.
The present invention is not limited to the above-described specific embodiments, and various modifications may be made by those skilled in the art without inventive effort from the above-described concepts, and are within the scope of the present invention.
Claims (9)
1. A high-speed LVDS interface communication training method is characterized in that,
after the second end sampling clock phase with the largest timing margin is obtained for bit alignment, word alignment is carried out;
the method for acquiring the second end sampling clock phase with the maximum timing margin comprises the following steps: the second end sampling clock phase with stable sampling value is used as candidate sampling clock phase, a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling value with the largest occurrence number of the same stable sampling value is used as an optimal sampling window of the second end sampling clock, and the phase median of the optimal sampling window is used as the second end sampling clock phase with the largest timing margin.
2. The method for training high-speed LVDS interface communication according to claim 1, wherein the step of taking the second sampling clock phase with the stable sampling value as the candidate sampling clock phase includes:
the delay adjusting unit of the second end generates a plurality of sampling clocks with different phases to sample the training codes continuously sent by the first end;
in the case where the sampling value at the sampling clock of one phase is stable, the phase of the sampling clock and the stable sampling value are recorded.
3. The method for training high-speed LVDS interface communication according to claim 2, wherein the delay adjustment unit at the second end generates a plurality of sampling clocks with different phases, which means:
and under the condition that the adjustable range of the delay adjusting unit at the second end is D, a fixed value is taken as a sampling clock phase stepping value to generate a plurality of sampling clocks with the phase values uniformly distributed in (0, D).
4. The method for training high-speed LVDS interface communication according to claim 2, wherein the method for obtaining the optimal sampling window of the second end sampling clock comprises:
under the condition that the same stable sampling value is recorded for the maximum number of times, acquiring the phase position in each record corresponding to the sampling value;
and acquiring a continuous phase interval consisting of a plurality of phases as an optimal sampling window.
5. The method for training high-speed LVDS interface communication according to claim 4, wherein the method for obtaining the optimal sampling window of the second sampling clock further comprises:
record each stable sampling value Q i Number of occurrences T j ；
If T j Corresponding to the maximum value of the stable sampling value Q imt Two are provided, and the sampling value Q is stabilized according to the later imt And corresponding to the phase in each record, acquiring a continuous phase interval formed by a plurality of phases as an optimal sampling window of the second end sampling clock.
6. The method for training high-speed LVDS interface communication according to claim 1, wherein the method for word alignment comprises:
and sliding the sampling training code when the phase of the sampling clock at the second end is the phase median of the optimal sampling window until the sampling training code after sliding is consistent with the actual training code sent by the first end, keeping the position of the sliding bit, and finishing training, wherein the upper limit of the operation times of the sliding bit is the bit width of the training code.
7. A high-speed LVDS interface communication training device, comprising:
the bit alignment module is used for obtaining the second end sampling clock phase with the largest timing margin to perform bit alignment, and the method for obtaining the second end sampling clock phase with the largest timing margin comprises the following steps: taking a second end sampling clock phase with stable sampling values as candidate sampling clock phases, taking a continuous phase interval formed by a plurality of second end sampling clock phases corresponding to the stable sampling values with the largest occurrence times of the same stable sampling values as an optimal sampling window of a second end sampling clock, and taking the phase median of the optimal sampling window as the second end sampling clock phase with the largest timing margin;
and the word alignment module is used for performing word alignment after performing bit alignment.
8. A computer device, the computer device comprising:
a memory for storing executable instructions;
a processor, configured to implement a high-speed LVDS interface communication training method according to any one of claims 1 to 6 when executing the executable instructions stored in the memory.
9. A computer readable storage medium storing executable instructions which when executed by a processor implement a high speed LVDS interface communication training method of any one of claims 1 to 6.
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