CN114967410B - Digital time conversion device and method - Google Patents
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- CN114967410B CN114967410B CN202210689464.2A CN202210689464A CN114967410B CN 114967410 B CN114967410 B CN 114967410B CN 202210689464 A CN202210689464 A CN 202210689464A CN 114967410 B CN114967410 B CN 114967410B
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 28
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- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 4
- 238000011161 development Methods 0.000 abstract description 4
- 239000002041 carbon nanotube Substances 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 8
- 229910021393 carbon nanotube Inorganic materials 0.000 description 8
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a digital time conversion device and a digital time conversion method, wherein the device comprises an FPGA chip, and the inside of the FPGA chip is provided with: the data processing module is used for determining configuration parameters according to the input data, wherein the configuration parameters comprise counting set values; the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach corresponding count set values and then output high level; the fine time interval generating module comprises two delay chains, the two delay chains respectively delay the high level output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module. The invention utilizes the FPGA chip to finish the conversion of digital time, and has the advantages of low production cost, short development period and high flexibility.
Description
Technical Field
The present invention relates to the field of digital signal processing technologies, and in particular, to a digital time conversion device and method.
Background
Digital time conversion (DTC, digital Time Convert) technology has found wide application in circuits. There are many methods for implementing time interval generation in the prior art, and they can be classified into an analog method and a digital method according to implementation manners. The time interval generating system constructed by using the digital method has better temperature stability and is beneficial to large-scale integration. Currently, high resolution time interval generation systems are mainly implemented using ASIC (Application Specific Integrated Circuit ) chips.
However, the use of ASIC chips to implement digital time conversion systems has the problems of high production cost, long development cycle, poor flexibility, and the like.
Disclosure of Invention
The embodiment of the invention provides a digital time conversion device and a digital time conversion method, which are used for solving the problems of high production cost, long development period, poor flexibility and the like in the prior art that an ASIC chip is utilized to realize a digital time conversion system.
In one aspect, an embodiment of the present invention provides a digital time conversion device, including an FPGA chip, where the FPGA chip has:
the data processing module is used for determining configuration parameters according to the input data, wherein the configuration parameters comprise counting set values;
the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach corresponding count set values and then output high level;
the fine time interval generating module comprises two delay chains, the two delay chains respectively delay the high level output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
In another aspect, an embodiment of the present invention provides a digital time conversion method, including:
determining configuration parameters according to input data by adopting an FPGA chip, wherein the configuration parameters comprise counting set values;
counting by adopting two counters in the FPGA chip, and outputting a high level after the count values of the two counters respectively reach corresponding count set values;
and adopting two delay chains in the FPGA chip to respectively carry out delay processing on the high level output by the two counters and output corresponding step signals, wherein the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
The digital time conversion device and the digital time conversion method have the following advantages:
compared with an ASIC chip, the high-resolution digital time converter based on the FPGA has the advantages of low production cost, short development period and high flexibility.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a functional module of a digital time conversion device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a functional module of a fine time interval generating module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a fine time interval generation module according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a coarse time interval generation module and a fine time interval generation module according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of an internal register transfer stage of an FPGA chip according to an embodiment of the present invention;
fig. 6 is a flowchart of a digital time conversion method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a functional module of a digital time conversion device according to an embodiment of the present invention. The embodiment of the invention provides a digital time conversion device, which comprises an FPGA chip, wherein the FPGA chip is internally provided with:
the data processing module is used for determining configuration parameters according to the input data, wherein the configuration parameters comprise counting set values;
the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach corresponding count set values and then output high level;
the fine time interval generating module comprises two delay chains, the two delay chains respectively delay the high level output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
For example, the required time interval preset information may be previously transmitted to the data processing module, and the transmitted data may be decoded to form configuration parameters.
In the embodiment of the invention, the FPGA chip can be a Kintex-7 series FPGA chip produced by Xilinx company, and a programmable absolute input/output unit inside the chip can be used for forming a delay chain. Specifically, each delay chain includes an input delay module (IDELAY 2 module) and an output delay module (ODELAY 2 module), which are connected in series to form a delay chain, as shown in FIG. 2.
The IDELAY2 module and the ODELAY2 module are programmable 31-order delay units, and the delay parameters can refer to a Kintex-7 series FPGA input-output module user manual produced by Xilinx company. The IDELAYE2 module and the ODELAY2 module are cyclic delay compensation modules containing 31-level delay units, the IDELAY2 module can be used for delaying logic signals in the FPGA chip with specified resolution, the ODELAY2 module is used for delaying output signals of the FPGA chip, and the FPGA chip can directly access the IDELAY2 module and the ODELAY2 module.
In a possible embodiment, the fine time interval generation module further comprises a delay control module for calibrating the delay units in the two delay chains using the input reference clock.
Illustratively, the delay resolution of each delay cell in the IDELAY2 module and the ODELAY2 module is compensated by an input reference clock provided by a delay control module (IDELAYCTRL module).
As shown in fig. 2, the IDELAYCTRL module calibrates the delay times of the delay units in the IDELAY2 module and the ODELAY2 module based on the input reference clock to reduce the effect of voltage and temperature on the accuracy of the delay units. The ideelay 2 module and the odeelay 2 module must be used together with the IDELAYCTRL module, and when two sets of delay chains with different unit delay times are created, two sets of IDELAYCTRL modules are required to perform time alignment (hereinafter referred to as IDELAYCTRLA module and ideelayctrlb module).
The high-level signal output by the coarse time interval generation module is input into the IDELAY2 module, and the signal is delayed by the IDELAY2 module, then enters the ODELAY2 module for delay and is output. The IDELAY2 module and the ODELAY2 module are connected in series to form a delay chain.
As shown in fig. 3, the ideelay 2 module (including a plurality of unit delay times τ) can be formed by using a differential delay method A And a multiplexer (MUX module)) and an ODELAY2 module (comprising a plurality of units of delay time τ) A And a multiplexer (MUX module)) in series to form a delay chain: delay chain a. An IDELAY2 module (comprising a plurality of units of delay time τ) having a different unit of delay time than the delay chain A is then provided B And a multiplexer (MUX module)) and an ODELAY2 module (comprising a plurality of units of delay time τ) B And a multiplexer (MUX module)) in series to form another delay chain: delay chain B. The resolution of the digital-to-time conversion device formed by this method is determined by the difference in unit delay times of the two delay chains (Δτ=τ) B -τ A )。
By using the differential delay method, reasonable layout and wiring can be carried out inside the FPGA chip so as to offset wiring delay and device delay, and the generated time interval is more accurate.
In a possible embodiment, the configuration parameter further includes a delay stage number, the delay chain includes a multiplexer and a plurality of delay units, the plurality of delay units are sequentially connected in series, and the multiplexer is used for controlling the delay units with the same number of delay stage numbers to be connected into the delay chain.
Illustratively, as shown in FIGS. 4 and 5, the coarse time interval generation module consists of two counters cnt_time1 and cnt_time2, both counters using the same clock S refclk From S pulse As enable signals for the two counters. When the count value of the counter reaches the count set value, a high-level signal is output to enter the fine time interval generating module shown in fig. 3. The fine time interval generating module selects delay units with the same number as the delay series by a multiplexer to be connected into a delay chain, and outputs two step signals S start (or step 1) and S stop The time interval between (or step 2) is the desired time interval, i.e. the coarse time interval (T coarse ) Andfine time interval (T) fine ) And (3) summing.
After the data processing module determines the configuration parameters, the counter sets the counting set value as a counting threshold, the data processing module configures the two delay chains into a variable delay mode, and after the multiplexer finishes controlling the access quantity of the delay units, the delay chains exit the variable delay mode.
Specifically, the upper computer transmits the required time interval data to a data processing module of the FPGA chip, and the data processing module firstly calculates and obtains the CNT A 、CNT B Values of m, n. CNT (carbon nanotube) A 、CNT B Directly transmitted to a coarse time interval generation module as count thresholds of a counter A and a counter B respectively. The data processing module further configures the ideelay 2 module and the odeelay 2 module into a variable delay mode (var_load) by setting the parameters LD of the two delay chains to 1, and after the data configuration is completed, the parameters LD are set to 0, and the delay chains exit the variable delay mode.
In one possible embodiment, the method further comprises: and the differential clock module is used for providing clock signals for the FPGA chip.
Illustratively, the FPGA module further comprises: the clock buffer is used for buffering the clock signals input by the differential clock module; the mode clock manager is used for carrying out frequency multiplication processing on the buffered clock signals to obtain two input reference clocks with different frequencies, and the two input reference clocks with different frequencies are respectively used for calibrating delay units in two delay chains by the two delay control modules.
In the embodiment of the invention, the differential clock signal input by the differential clock module is input into a clock buffer (IBUFDS) for buffering and then enters a mode clock manager (MMCM) for frequency multiplication to generate two clock signals of 300MHz and 400 MHz. The clock signal of 400MHz is used as the global clock of the FPGA chip and the input reference clock of the IDELAYCTRLA module, and the clock signal of 300MHz is used as the input reference clock of the IDELAYCTRLB module. The IDELAYCTRLA module adjusts the unit delay time of the delay chain A and the IDELAYCTRLB module adjusts the unit delay time of the delay chain B.
The delay chain A adopts 400MHz transmissionThe unit delay time tau of each stage of delay unit can be known according to the specification of the direct current-alternating current conversion characteristics of the Kintex-7 series FPGA by entering a reference clock A The delay chain B adopts 300MHz input reference clock to determine the unit delay time tau of each stage of delay unit B =52 ps. The minimum time interval resolution of the device Δτ=τ B -τ A ＝13ps。
The counting clock of the coarse time interval generating module is 400MHz, and the coarse time interval resolution T can be known 0 ＝1/f＝2.5ns。
To ensure linearity of the device, the resulting fine time intervals should have continuity, so that the number of delay cell stages in the delay chain should be not less than m (m=t 0 /τ B -1=47). And Δτ should satisfy τ B The continuity of the time intervals, i.e. the number of Δτs that can be generated thereby, is not less than n (n=τ B /Δτ -1=3). The minimum required number of delay cell stages is thus m+n=50. Because each IDELAY2 module and ODELAY2 module in the invention are provided with 31-level delay units, after the IDELAY2 module and the ODELAY2 module are connected in series, a delay chain with 62-level delay units can be formed, and the requirement of linearity of the device is met.
Let the time interval of the required generation be T, CNT A 、CNT B Generating configuration parameters, T, for two counters in a module for coarse time intervals 0 M and n are the number of stages of delay units selected by the multiplexer in the delay chain A and the delay chain B respectively, and τ is the unit coarse time interval A 、τ B The minimum time interval resolution of the device Δτ=τ for the unit delay times of delay chain a and delay chain B, respectively B -τ A % is the remainder of the division, and there are:
CNT B -CNT A directly determining the size of the coarse time interval, CNTs are generally taken for simplicity of design A =0, so the configuration parameters of coarse and fine time intervals can be obtained:
the upper computer provides input of required time intervals and transmits time interval data to the FPGA chip, and the data processing module in the FPGA chip configures the configuration parameters to the coarse time interval generation module and the fine time interval generation module of the FPGA chip through the operation.
In one possible embodiment, the FPGA chip further includes, internally: and the communication module is used for receiving the data sent by the upper computer and sending the received data to the data processing module.
The communication module communicates with the upper computer by using UART protocol to receive data sent by the upper computer.
The embodiment of the invention also provides a digital time conversion method, as shown in fig. 6, comprising the following steps:
determining configuration parameters according to input data by adopting an FPGA chip, wherein the configuration parameters comprise counting set values;
counting by adopting two counters in the FPGA chip, and outputting a high level after the count values of the two counters respectively reach corresponding count set values;
and adopting two delay chains in the FPGA chip to respectively carry out delay processing on the high level output by the two counters and output corresponding step signals, wherein the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (6)
1. The digital time conversion device is characterized by comprising an FPGA chip, wherein the FPGA chip is internally provided with:
the data processing module is used for determining configuration parameters according to the input data, wherein the configuration parameters comprise counting set values;
the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach the corresponding count set values and then output high level;
the fine time interval generation module comprises two delay chains, wherein the two delay chains respectively carry out delay processing on high levels output by the two counters and output corresponding step signals, the time interval between the two step signals is a time interval corresponding to data input into the data processing module, and the fine time interval generation module further comprises a delay control module which is used for calibrating delay units in the two delay chains by adopting an input reference clock;
the differential clock module is used for providing clock signals for the FPGA chip;
the FPGA chip further includes:
the clock buffer is used for buffering the clock signals input by the differential clock module;
and the mode clock manager is used for carrying out frequency multiplication processing on the buffered clock signals to obtain two input reference clocks with different frequencies, wherein the two input reference clocks with different frequencies are respectively used for calibrating delay units in the two delay chains by the two delay control modules.
2. The digital time conversion device according to claim 1, wherein the configuration parameters further include a delay stage number, the delay chain includes a multiplexer and a plurality of delay units, the plurality of delay units are sequentially connected in series, and the multiplexer is used for controlling the delay units with the same number as the delay stage number to be connected into the delay chain.
3. The digital-to-time conversion apparatus according to claim 2, wherein said counter sets said count setting value as a count threshold after said data processing module determines said configuration parameter, said data processing module configures two of said delay chains into a variable delay mode, and said delay chains exit the variable delay mode after said multiplexer has completed controlling the number of delay unit accesses.
4. The digital time conversion device according to claim 1, wherein the FPGA chip further comprises:
and the communication module is used for receiving the data sent by the upper computer and sending the received data to the data processing module.
5. The digital-to-time conversion apparatus according to claim 4, wherein the communication module communicates with the host computer using UART protocol.
6. A digital time conversion method, comprising:
determining configuration parameters according to input data by adopting an FPGA chip, wherein the configuration parameters comprise counting set values;
counting by adopting two counters in the FPGA chip, and outputting a high level after the count values of the two counters respectively reach the corresponding count set values;
respectively carrying out delay processing on the high level output by the two counters by adopting two delay chains in the FPGA chip, and outputting corresponding step signals, wherein the time interval between the two step signals is a time interval corresponding to the data input into the data processing module;
calibrating delay units in two delay chains by adopting an input reference clock;
providing a clock signal to the FPGA chip;
buffering the input clock signal;
and performing frequency multiplication processing on the buffered clock signals to obtain two input reference clocks with different frequencies, wherein the two input reference clocks with different frequencies are respectively used for calibrating delay units in the two delay chains.
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