JP2019176357A - Time digital conversion circuit and time digital conversion method - Google Patents

Abstract

To provide a time digital conversion circuit and a time digital conversion method, capable of normally converting a time interval between a clock signal and an object signal into a digital signal with resolution higher than a delay amount of each delay circuit, and in which a bit with low accuracy is unevenly distributed in the digital value.SOLUTION: A time digital conversion circuit comprises: a plurality of time digital conversion parts; a selector capable of selecting an output of any one of the plurality of time digital conversion parts; and a controller that transmits an object signal to be measured to a transmission path of the plurality of time digital conversion parts, sequentially distributes a clock signal to a clock transmission path of the plurality of time digital conversion parts, and controls the selector so that the output of the time digital conversion part in which a capture part group completes capture on the basis of the clock signal distributed from the plurality of time digital conversion parts.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a time digital conversion circuit (TDC) and a time digital conversion method, and more particularly to a time digital conversion circuit and a time digital conversion method using a vernier delay chain.

  Conventionally, there is a time digital conversion circuit that converts a time interval between a measurement target signal and a reference signal into a digital value using a delay chain. A typical delay chain includes a transmission line in which a plurality of delay circuits are connected in series, and a plurality of flip-flops provided corresponding to the plurality of delay stages of the transmission line. Each flip-flop captures the signal level of the corresponding delay stage of the transmission line in synchronization with the reference signal input simultaneously. In such a circuit, the target signal is input to the transmission path, and the reference signal is input to the plurality of flip-flops while the target signal travels through the transmission path. For example, when the reference signal is input at the timing when the high-level target signal reaches the x-th delay stage, the high-level signal is captured until the x-th stage flip-flop, and the flip-flops from the x + 1 stage onward Captures low level signals. Therefore, the output of the plurality of flip-flops specifies the stage of the delay line in the transmission path when the target signal has been input. Therefore, the time interval between the target signal and the reference signal is obtained from the delay amount τ of each delay circuit. In the above example, x × τ is the time interval between the target signal and the reference signal. In such a circuit, the resolution of the measured time interval is the delay amount τ.

  FIG. 3 of Patent Document 1 shows a circuit that converts a time interval of a signal into a digital value using a plurality of delay chains connected in parallel. In this circuit, measurement target signals are simultaneously input to a plurality of delay chains, while a reference signal in which a slight time difference is added to a plurality of delay chains is input. For example, if the resolution of each delay chain is τ, reference signals obtained by adding a time difference τ / i to i delay chains (i is 2 or more) are input. As a result, the reference timing of the time interval measured by the plurality of delay chains differs by time difference τ / i. Therefore, even if the resolution of one delay chain is τ, the time interval is converted into a digital value with resolution τ / i by combining the outputs of the delay chains of a plurality of columns.

  As a conventional time digital conversion circuit capable of converting a time interval into a digital value with a resolution higher than the delay amount of the delay circuit included in the delay chain, there is a circuit using a vernier type delay chain. A vernier delay chain typically includes a reference signal transmission line having a plurality of delay stages. The reference signal is sent to each flip-flop with delay added to a plurality of stages. The vernier type delay chain uses two types of delay circuits having different delay amounts τ1 and τ2, and measures a time interval having a resolution | τ1−τ2 | as a resolution.

Special table 2012-522466 gazette

  According to the technique of Patent Document 1, the time interval is converted into a digital value with a higher resolution than the resolution of the delay chain. However, in the technique of Patent Document 1, it is necessary to add a time difference obtained by dividing the resolution of the delay chain of each column by an integer to the reference signal supplied to the delay chains of a plurality of columns. And there exists a subject that the precision of the time difference of a some reference signal has a direct influence on the precision of a measurement result. For example, when supplying four reference signals with a time difference to four delay chains connected in parallel, if the accuracy of one reference signal is low, all the bits of the delay chain that have received this reference signal The output is reduced in accuracy as much as the reference signal. In other words, the technique of Patent Document 1 has a problem that bits with low accuracy are likely to be unevenly distributed in the digital value of the measurement result.

  In addition, in a circuit using a vernier delay chain, the time interval between the target signal and the reference signal is measured with high resolution by adding a delay to the reference signal in a plurality of stages. For this reason, there is a problem that the time required for measuring the time interval becomes longer than the maximum value of the measurable time interval. For example, when the resolution is τ1−τ2 and the number of stages of the delay circuit is n, the maximum measurable time interval is (τ1−τ2) × n, while the time required for one measurement is τ1 × n, and the latter requires a longer time for measurement.

  Therefore, when the reference signal is input as a periodic clock signal and measurement is repeated, the maximum measurable time interval is a part of the clock period when the clock period is adjusted to the time required for one measurement. It will be limited to the period. In this case, the time interval cannot be measured even if the target signal is input in another period within the clock cycle. Also, when the clock period is set to the maximum measurable time interval, the next clock signal is input to the delay chain before one measurement is completed after one clock signal is input to the delay chain. The next measurement will start. For this reason, when the digital value of the first measurement result is output, the digital value on the start end side is updated by the next clock signal, and there is a problem that a normal result may not be obtained (FIG. 9 and FIG. 9). (See description of comparative example).

  Therefore, the present invention provides a time digital conversion circuit and a time digital conversion method capable of normally converting a time interval between a clock signal and a target signal into a digital value with a resolution higher than the delay amount of each delay circuit. Objective.

  It is another object of the present invention to provide a time digital conversion circuit and a time digital conversion method in which bits with low accuracy are not unevenly distributed in a digital value.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to a certain aspect includes a plurality of time digital conversion units, a selector capable of selecting an output of any of the plurality of time digital conversion units, distribution of a measurement target signal and a clock signal, and the selection of the selector. A controller that performs control, and each of the plurality of time digital conversion units includes a transmission path in which a plurality of delay circuits are connected in series, and a plurality of clock delay circuits having a delay amount different from the delay circuit. Clock signals connected in series, a plurality of delay stages of the transmission path, and a plurality of delay stages of the clock transmission path, respectively, and a clock signal that has reached the corresponding delay stage of the clock transmission path And a capturing unit group including a plurality of capturing units that capture the signal level of the corresponding delay stage of the transmission line, and the controller includes the target signal. To the transmission paths of the plurality of time digital conversion units, sequentially distribute the clock signal to the clock transmission paths of the plurality of time digital conversion units, and distributed among the plurality of time digital conversion units The time digital conversion circuit controls the selector so that the outputs of the time digital conversion units that have been captured by the capturing unit group are sequentially selected based on the clock signal.

  Here, the controller distributes the clock signal to the plurality of time digital conversion units in a predetermined order, and causes the selector to select the outputs of the plurality of time digital conversion units in the same order as the predetermined order. The selection cycle of the output by the selector may be advanced by one cycle of the clock signal from the distribution cycle of the clock signal by the controller.

  Further, the controller may include a distribution circuit that distributes a clock signal and a buffer that delays the target signal and sends the delayed signal to the plurality of time digital conversion units.

  Further, each of the plurality of time digital conversion units includes a plurality of vernier delay chains each including a plurality of sets of the transmission path, the clock transmission path, and the capturing unit group. A plurality of majority voting circuits for voting the capture results of the capture units at each stage in the plurality of vernier delay chains, and the determination results of the plurality of majority circuits may be output.

  Furthermore, the period p of the clock signal, the number (i + 1) of the time-to-digital converters, and the time T for the target signal to reach the last delay stage from the beginning of the transmission path are p × (i + 1) ≧ T May be satisfied.

  Furthermore, the maximum time interval that the time digital conversion unit can convert to a digital value may be equal to or longer than the period of the clock signal.

  The present invention according to another aspect includes a plurality of time digital conversion units and a selector capable of selecting an output of any of the plurality of time digital conversion units, and each of the plurality of time digital conversion units includes a plurality of time digital conversion units. A transmission line in which a plurality of delay circuits are connected in series, a clock transmission line in which a plurality of clock delay circuits having a delay amount different from that of the delay circuit are connected in series, a plurality of delay stages in the transmission line, and the clock A plurality of capturing units that are provided corresponding to the plurality of delay stages of the transmission line, and that capture the signal level of the corresponding delay stage of the transmission line based on the clock signal that has reached the corresponding delay stage of the clock transmission line A time digital conversion method using a circuit having a capture unit group including: a signal to be measured is sent to the transmission path of the plurality of time digital conversion units, and a clock signal is transmitted A plurality of time digital conversion units that are sequentially distributed to the clock transmission paths, and among the plurality of time digital conversion units, the plurality of time acquisition units of the time digital conversion units that have completed acquisition based on the distributed clock signal. This is a time digital conversion method for controlling the selector so that outputs are sequentially selected.

  Here, the clock signals are distributed to the plurality of time digital conversion units in a predetermined order, and the selector is configured to select the outputs of the plurality of time digital conversion units in the same order as the predetermined order. The output selection cycle may be advanced by one cycle of the clock signal from the clock signal distribution cycle.

  In this specification and the like, the means does not simply mean a physical means, but includes a case where the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.

  According to the present invention, the time interval between the clock signal and the target signal can be normally converted into a digital value with a resolution higher than the delay amount of each delay circuit.

  Furthermore, according to the present invention, it is possible to provide a time digital conversion circuit and a time digital conversion method in which bits with low accuracy are not unevenly distributed in a digital value.

Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a block diagram which shows an example of a structure of the time digital conversion circuit which concerns on one Embodiment of this invention. It is a block diagram which shows an example of a structure of the controller of the time digital conversion circuit which concerns on one Embodiment of this invention. FIG. 3 is a circuit diagram illustrating an example of a configuration of the counter of FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a configuration of a distribution unit in FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a configuration of an encoder in FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a configuration of a buffer in FIG. 2. It is a circuit diagram which shows an example of a structure of the delay chain of the multiple columns of the time digital conversion circuit which concerns on one Embodiment of this invention. It is a circuit diagram which shows an example of a structure of the selector of the time digital conversion circuit which concerns on one Embodiment of this invention. It is a timing chart of each signal of the time digital conversion circuit of a comparative example. It is a timing chart of the signal of the controller in the time digital conversion circuit concerning one embodiment of the present invention. It is a timing chart of each signal of the delay chain of the 1st column in the time digital conversion circuit concerning one embodiment of the present invention. It is a timing chart of each signal of the delay chain of the 2nd column in the time digital conversion circuit concerning one embodiment of the present invention. It is a timing chart of each signal of the delay chain of the 3rd column in the time digital conversion circuit concerning one embodiment of the present invention. It is a timing chart of each signal of the delay chain of the 4th column in the time digital conversion circuit concerning one embodiment of the present invention. It is a timing chart of each signal of the delay chain of each signal of the time digital conversion circuit concerning one embodiment of the present invention. It is a block diagram which shows an example of a structure of the delay chain of the time digital conversion circuit which concerns on other embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and technical applications that are not explicitly described below. The present invention can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match actual dimensions and ratios. In some cases, the dimensional relationships and ratios may be different between the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a time digital conversion circuit according to an embodiment of the present invention. As shown in FIG. 1, the time digital conversion circuit 1 includes, for example, a plurality of vernier delay chains 13, a controller 11, and a selector 15. The time digital conversion circuit 1 receives a clock signal having a predetermined period p and a measurement target signal, and sets the time interval of the input timing between the clock signal and the target signal to output data OUT [n: 0] which is a digital value. Convert. Among the above components, the plurality of delay chains correspond to an example of a plurality of time digital conversion units according to the present invention. Hereinafter, as the time digital conversion circuit 1, a configuration example having i + 1 (i is an integer of 1 or more) columns of vernier delay chains 13 or a configuration example of i = 3 will be described. In this specification and the drawings, the notation [integer 2: integer 1] represents (integer 1−integer 2 + 1) bits from integer 1 to integer 2.

  FIG. 2 is a block diagram showing an example of the configuration of the controller of the time digital conversion circuit according to the embodiment of the present invention. The controller 11 includes, for example, a plurality of buffers 111, a counter 112, a plurality of distribution units 113, and an encoder 114. The number of the plurality of buffers 111 and the number of the plurality of distribution units 113 coincide with the number of the plurality of delay chains 13. The counter 112 and the plurality of distribution units 113 correspond to an example of a distribution circuit according to the present invention.

  The controller 11 receives the target signal from the outside, and outputs the target signal to the plurality of delay chains 13 via the plurality of buffers 111. Further, the controller 11 receives a clock signal from the outside, and distributes the clock signal to the plurality of delay chains 13 one by one through the distribution unit 113. The target signal output to the delay chain 13 in the first column to the (i + 1) th column and the distributed clock signal are represented as target signals sig0 to sigi and clock signals ck0 to cki, respectively.

  The plurality of buffers 111 are circuits that give signals the same delay. Each buffer 111 adds a delay equivalent to the amount of delay added when the clock signal passes through one of the distributors 113 to the signal passing therethrough. As a result, the delay of the target signal and the delay of the clock signal when passing through the controller 11 are equal, and the time interval between the target signal and the clock signal is suppressed from changing when passing through the controller 11.

  The counter 112 outputs state signals s [0] to s [i] that determine the distribution destination of the clock signal to the plurality of distribution units 113 in synchronization with the clock signal. For example, one of the state signals s [0] to s [i] is at a high level and the other is at a low level. The high-level state signals s [0] to s [i] are cyclically synchronized with the clock signal. Change.

  Each distribution unit 113 passes the clock signal if the input state signal is high level (asserted), and blocks the clock signal if the input state signal is low level (negate).

  The encoder 114 is used for the output of the counter 112 to select one of the captured data D0 [n: 0] to Di [n: 0] of the plurality of delay chains 13 sel [j: 0]. ] Is output to the selector 15. The encoder 114 outputs the selection signal sel [j: 0] in synchronization with the output of the counter 112, that is, in synchronization with the clock signal. The selection signal sel [j: 0] is a (j + 1) -bit signal that can select any one of (i + 1) pieces of captured data D0 [n: 0] to Di [n: 0]. The encoder 114 selects the selection signal sel [j: 0] so that the output of the delay chain 13 to which the next clock signal is distributed among the plurality of delay chains 13 is selected in synchronization with the previous clock signal. Is generated.

  Here, a specific circuit of each part of the controller 11 is shown. However, each part of the controller 11 is not limited to these specific circuits. FIG. 3 is a circuit diagram showing an example of the configuration of the counter of FIG. FIG. 4 is a circuit diagram showing an example of the configuration of the distribution unit in FIG. FIG. 5 is a circuit diagram showing an example of the configuration of the encoder of FIG. FIG. 6 is a circuit diagram showing an example of the configuration of the buffer of FIG.

  As shown in FIG. 3, the counter 112 is composed of a state machine that combines, for example, i + 1 flip-flops a to change the state by a clock signal. The state signals s [0] to s [i] indicating the state are set to an initial state such that one is at a high level and the other is at a low level.

  As shown in FIG. 4, the plurality of distribution units 113 can be composed of, for example, a plurality of AND circuits b from 0th to i-th. The plurality of AND circuits b are provided in association with the plurality of delay chains 13, respectively. Each AND circuit b receives a clock signal and a corresponding one of the state signals s [0] to s [i]. Furthermore, each AND circuit b outputs clock signals ck0 to cki to the corresponding delay chain 13. For example, when i = 3, the encoder 114 can be composed of two OR circuits c as shown in FIG. The two OR circuits c use, for example, 3 bits out of 4-bit state signals s [0] to s [3], and a 2-bit selection signal sel [0] that allows 4 (= i + 1) selections. ], Sel [1] are generated. Even in cases other than i = 3, the encoder 114 may be configured by appropriately combining logic gates. As shown in FIG. 6, the buffer 111 may be configured, for example, by connecting a predetermined number of logic gates in series. The number of stages of logic gates included in the buffer 111 is, for example, the logic from when the clock signal is input to the counter 112 until the state signals s [0] to s [i] are updated and the outputs of the plurality of distribution units 113 are switched. It is set to match the number of stages of operation.

  FIG. 7 is a circuit diagram showing an example of a configuration of a plurality of columns of delay chains in the time-to-digital conversion circuit according to the embodiment of the present invention. First, the vernier delay chain 13 in the first column will be described.

  The delay chain 13 includes a transmission path 131 in which a plurality of delay circuits e are connected in series, and a clock transmission path 132 in which a plurality of delay circuits f are connected in series. The input node of the transmission line 131 is defined as the 0th delay stage, and the output node of the uth delay circuit e (u is any one of 1 to n) from the input side is defined as the uth delay stage. The total number of delay stages from the 0th stage to the uth stage is defined as u stage without counting the 0th stage. The same applies to the clock transmission path 132. The delay chain 13 further includes a flip-flop row 133 including n + 1 flip-flops g corresponding to 0 to n delay stages. The target signal sig0 is transmitted to the transmission path 131, and the clock signal ck0 is transmitted to the clock transmission path 132. Among the above components, the delay circuit f corresponds to an example of a clock delay circuit according to the present invention. The flip-flop g corresponds to an example of the capturing unit according to the present invention. The flip-flop row 133 corresponds to an example of a capturing unit group according to the present invention.

  The delay amount τ1 of each delay circuit e in the transmission path 131 is different from the delay amount τ2 of each delay circuit f in the clock transmission path 132. For example, τ1 = 38 ps and τ2 = 28 ps.

  The plurality of flip-flops g are provided so as to correspond to the plurality of delay stages of the transmission path 131 and the clock transmission path 132, respectively. Each flip-flop g is connected so that the signal of the delay stage corresponding to the transmission path 131 is input to the data terminal and the signal of the delay stage corresponding to the clock transmission path 132 is input to the control terminal. Thus, the flip-flop g captures the signal level of the corresponding delay stage of the transmission line 131 when the clock signal ck0 reaches the corresponding delay stage, and supplements until the next clock signal ck0 is input. Continue signal level output.

  Here, the principle of time measurement by one delay chain 13 will be described. When delay amount τ1> delay amount τ2, the clock signal ck0 after the target signal sig0 is input is a measurement reference. Due to the delay amount relationship τ 1> τ 2, the speed at which the clock signal ck 0 travels through the clock transmission path 132 is faster than the speed at which the target signal sig 0 travels through the transmission path 131. Then, when the target signal sig0 reaches the x-th delay stage of the transmission path 131, the clock signal ck0 catches up with the x-th delay stage of the clock transmission path 132. In this case, before the x-th stage, when the clock signal ck0 arrives, the target signal sig0 has already reached. Further, after the x-th stage, when the clock signal ck0 arrives, the target signal sig0 has not yet arrived. Therefore, assuming that the target signal sig0 is a signal that changes from a low level to a high level, the flip-flop g up to the x-th stage captures the high-level signal, and the flip-flop g from the x + 1-th stage to the subsequent-stage flip-flop g Capture low level signals. Therefore, the captured data D0 [n: 0] of the plurality of flip-flops g specifies how many delay stages the target signal sig0 has advanced to catch up with the clock signal ck0. The timing at which the clock signal ck0 reaches the x-th delay stage is the timing at which the clock signal ck0 is input to the clock transmission path 132 + x × τ2. The timing at which the target signal sig0 reaches the x-th delay stage is the timing at which the target signal is input to the transmission path 131 + x × τ1. These can be regarded as the same timing. From these, the time interval [x × (τ1-τ2)] of the input timing between the target signal sig0 and the clock signal ck0 is obtained. Since x means the number of delay stages of the transmission path 131 and the clock transmission path 132, the resolution r of the measurable time interval is (τ1-τ2). As an example, if τ1 = 38 ps and τ2 = 28 ps, the resolution r is 10 ps, and the resolution r is smaller than the delay amounts τ1 and τ2 of the delay circuits e and f.

  The delay stage number n of the delay chain 13 is set so that the time interval between the clock signal ck0 and the target signal sig0 can be measured regardless of the timing of the clock signal p when the target signal sig0 is input. Here, the clock period p means the period of the clock signal before being distributed. Since delay stage number n × resolution r is the maximum value of the measurable time interval, delay stage number n is set to an integer equal to or greater than clock period p / resolution r. The delay stage redundancy can be eliminated by setting the delay stage number n = p / r (in the case of an integer) or the delay stage number n = [an integer obtained by rounding up the first decimal place of p / r]. The clock signal may be configured to be supplied from the outside of the time digital conversion circuit 1, or the time digital conversion circuit 1 may include a clock generation circuit that generates a clock signal having such a cycle. Good.

  As for the number i + 1 of the plurality of delay chains 13, the clock signal ck0 to be distributed next is input before one measurement time T elapses after the clock signal ck0 is input to the delay chain 13 and measurement is started. It is set not to be done. Here, one measurement time T is defined as the time (n × τ1) from when the target signal sig0 is input to the transmission line 131 until it reaches the nth delay stage. If the next clock signal ck0 is distributed before one measurement time T elapses, the value on the start side is rewritten by the next clock signal ck0 before the result of one measurement is determined. Normal results may not be obtained. Such a situation can be avoided by the above setting. Since the period of the distributed clock signal ck0 is the number of delay chains 13 (i + 1) × clock period p, the number (i + 1) is an integer equal to or greater than T / p. The number (i + 1) of the delay chains 13 is T / p (in the case of an integer) or [an integer obtained by rounding up the first decimal place of T / p (in the case of a non-integer)]. 13 redundancy can be omitted.

  Alternatively, the measurement time T ′ of the delay chain 13 is defined as the time from when the clock signal ck0 is distributed until the capture of the n-th flip-flop g is completed, and the number i + 1 of the plurality of delay chains 13 is determined. You can also In this definition, the measurement time T ′ = n × τ2. The distribution cycle of the clock signal ck0 is (i + 1) × clock cycle p if the number of delay chains 13 is i + 1. In this period, if the measurement of the delay chain 13 is completed and the last one clock period p can be assigned to the output timing of the capture data D [n: 0], the delay chain 13 can perform normal measurement and normal capture data. D [n: 0] can be output periodically. That is, the measurement time T ′ may be shorter than a time shorter by one clock cycle p than the distribution cycle (i + 1) × p of the clock signal ck0. From these relationships, the number (i + 1) of delay chains 13 can be set to an integer equal to or greater than 1+ (T ′ / p). The same value is obtained as the required number (i + 1) of the delay chains 13 regardless of which measurement time T, T ′ is applied.

  With the configuration described above, the delay chain 13 in the first column uses the selector 15 as the digital value representing the time interval between the target signal sig0 and the clock signal ck0, using the captured data D0 [n: 0] of the n + 1 flip-flops g. Output to.

  In the delay chain 13 in the second column and thereafter, input target signals sig1 to sigi, input clock signals ck1 to cki, and output captured data D1 [n: 0] to Di [n: 0] The configuration is the same as that of the delay chain 13 in the first column except that it is different from the first column.

  FIG. 8 is a circuit diagram showing an example of the configuration of the selector of the time digital conversion circuit according to the embodiment of the present invention. FIG. 8 shows a case where the time-to-digital conversion circuit 1 has four rows of delay chains 13 (i = 3). The selector 15 selects any one of the captured data D0 [n: 0] to Di [n: 0] of the delay chain 13 of the i + 1 column in accordance with the selection signal sel [j: 0] sent from the controller 11. This is output as output data OUT [n: 0]. If i = 3, the selector 15 can be configured by combining three multiplexers 151 as shown in FIG. The three multiplexers 151 are combined so as to sequentially select a plurality of captured data D0 [n: 0] to Di [n: 0] one by one based on the selection signal sel [j: 0].

  The selector 15 cyclically selects a plurality of captured data D0 [n: 0] to Di [n: 0] one by one for each clock period p (when the selection signal sel [j: 0] is switched). When there is no redundancy in the number n of delay stages 13 and the number (i + 1) of delay chains 13, one clock is required until the next measurement is started after one measurement is completed in one delay chain 13. There is only a period. Therefore, the selector 15 is controlled so that the captured data of the corresponding delay chain 13 is selected during this grace period.

  Specifically, the clock signal is cyclically distributed from the delay chain 13 in the first column to the delay chain 13 in the i + 1 column. The selector 15 cyclically selects a plurality of captured data D0 [n: 0] to Di [n: 0] in this order. However, the distribution cycle of the clock signals ck0 to cki and the selection cycle of the captured data D0 [n: 0] to Di [n: 0] are set so that the former is delayed by one clock cycle. For example, when the clock signals are sequentially distributed to the delay chains 13 in the first column, the second column,..., The i column, the i + 1 column, the selector 15 has the second column, the third column,. The captured data Dx [n: 0] are sequentially selected from the first and first delay chains 13.

<Measurement operation of comparative example>
FIG. 9 shows a timing chart of each signal of the time digital conversion circuit of the comparative example. First, the operation of the time digital conversion of the comparative example having one row of vernier type delay chains will be described. The delay chain of the comparative example has a configuration equivalent to that of the delay chain 13 of one column shown in FIG. 7, and the reference numerals of the constituent elements equivalent to the delay chain 13 of FIG. In the delay chain (13) of the comparative example, the delay circuit (e) of the transmission line (131) for transmitting the target signal exerts a delay amount τ1 = 38 ps, and the delay circuit (f) of the clock transmission line (132) is a delay. The amount τ2 = 28 ps is exerted and the resolution is τ1−τ2 = 10 ps. The delay chain (13) of the comparative example has 100 delay stages, and the input clock cycle is a maximum value of 1 ns of time intervals that can be measured by the delay chain (13) in one line (= the number of delay stages 100 × resolution). 10 ps).

  In FIG. 9, sig, sig [1] to sig [100] are the signal level of the 0th delay stage of the transmission line (131) through which the target signal is transmitted, and the signal level of the 1st delay stage to 100. The signal levels of the delay stages are shown respectively. ck, ck [1] to ck [100] are the signal level of the 0th delay stage of the clock transmission path (132), the signal level of the 1st delay stage to the signal level of the 100th delay stage, respectively. Each is shown. D [0] to D [100] indicate outputs of the 0th to 100th flip-flops (g), respectively. In FIG. 9, the same number is assigned to the same clock signal passing through each delay stage.

  As shown in sig to sig [100] in FIG. 9, the target signal is transmitted with a delay amount τ1 at each delay stage. On the other hand, as shown by ck, ck [1] to ck [100] in FIG. 9, the clock signal is transmitted with a delay amount τ2 at each delay stage. For this reason, compared with the 0th delay stage, in the 50th delay stage, the time interval between the target signal and the clock signal changes by half the clock cycle. In the 100th delay stage, the time interval between the target signal and the clock signal changes by the clock period.

  The flip-flop (g) of each delay stage captures the signal level of the corresponding delay stage of the transmission line 131 in synchronization with the rising edge of the clock signal of the corresponding delay stage, and then outputs the captured signal level. For this reason, the outputs of the flip-flops (g) from the 0th stage to the 100th stage are as shown in D [0] to D [100] in FIG.

  In such a circuit, for example, the result of the time interval measured with the second clock signal is a combination of captured data of each flip-flop (g) captured with the second clock signal (shown in a circle frame j2). ). However, when the output of the flip-flop (g) of each delay stage is viewed at the timing t1 when the second clock signal reaches the 100th delay stage, the subsequent (third, fourth, The acquisition result is updated by the clock signal. The updated results are indicated by circles j3 and j4. Therefore, even when the capture results are read from the flip-flops (g) of the plurality of delay stages at the timing t1 when the second clock signal reaches the 100th delay stage, a normal measurement result cannot be obtained. . For example, the acquisition result of the delay chain (13) in the first to third columns in FIG. 9 is updated to the low level (L) where it should be the high level (H).

<Measurement Operation of Embodiment>
Next, the operation of the time digital conversion circuit 1 of the embodiment will be described. Here, a case where there are four delay chains (i + 1 = 4) will be described. FIG. 10 is a timing chart of controller signals in the time digital conversion circuit according to the embodiment of the present invention. 11 to 14 are timing charts of signals of the delay chains in the first column to the fourth column in the time digital conversion circuit according to the embodiment of the present invention. FIG. 15 is a timing chart of each signal in the delay chain of each signal of the time-to-digital conversion circuit according to the embodiment of the present invention. 10 to 15, the same clock signal that is input to the controller 11 and distributed to each delay chain 13 is identified with the same number.

  As shown in FIG. 10, in the controller 11, the state signals s [0] to s [3] of the counter 112 are switched in synchronization with the input clock signal. In the controller 11, the clock signal is distributed by the four distribution units 113 based on the state signals s [0] to s [3], and the selection signals sel [0] and sel [1] of the encoder 114 are generated. Is done. As a result, the clock signals ck0 to ck3 are sequentially distributed to the four delay chains 13, and the selector 15 sequentially selects the captured data D0 [100: 0] to D3 [100: 0] (the selection destination is “select” in FIG. The description of [100: 0] is omitted in FIG. 10). The distribution order of the clock signals ck0 to ck3 and the selection order of the acquisition data D0 to D3 are the same. The distribution cycle of the clock signals ck0 to ck3 and the selection cycle of the acquisition data D0 to D3 are one clock in the former. Delayed by the period.

  The target signal and the clock signal in FIG. 11 indicate the input timing to the controller 11. FIG. 11 shows a signal of the delay chain 13 in the first column among the plurality of delay chains 13. In FIG. 11, sig0, sig0 [1] to sig0 [100] are the signal level of the 0th delay stage in the transmission line 131, the signal level of the 1st delay stage to the signal level of the 100th delay stage. Respectively. ck0, ck0 [1] to ck0 [100] are the signal level of the 0th delay stage of the clock transmission path 132 through which the distributed clock signal ck0 is transmitted, and the signal level of the 1st delay stage to the 100th stage. The signal level of the delay stage of the eye is shown. D0 [0] to D0 [100] indicate outputs of the 0th to 100th flip-flops g, respectively.

  In the delay chain 13 in the first column, unlike the operation of the comparative example of FIG. 9, the clock signal ck0 is input every four clock cycles. Therefore, at the timing t11 when the final delay stage flip-flop g captures the signal level (shown by a round frame j11) based on one clock signal ck0, all the other delay stage flip-flops g have the same clock. The result captured by the signal ck0 is held. The value of the captured data D0 [100: 0] of all the flip-flops g is held from timing t11 when the clock signal ck0 arrives at the final delay stage until timing t12 when the next clock signal ck0 is distributed. . Further, since the captured data D0 [100: 0] of all the flip-flops g is a result of capturing the signal level of each delay stage of the transmission line 131 based on the same clock signal ck0, the time between the clock signal ck0 and the target signal sig0. Express the interval normally. However, the time interval (the number of delay stages n × resolution r) that can be measured by one row of delay chains 13 is about one clock cycle, which is shorter than the four clock cycles of the distributed clock signal ck0. Therefore, if the time interval between the distributed clock signal ck0 and the target signal sig0 is equal to or greater than the measurable time interval, all the bits of the captured data D0 [100: 0] are at the low level or the high level.

  In the delay chains 13 in the second column to the fourth column, substantially the same operation can be obtained. However, as shown in FIGS. 11 to 14, the input timings of the clock signals ck <b> 0 to ck <b> 3 distributed to the delay chains 13 in the first column to the fourth column are shifted from each other by one clock cycle, while the target signals sig <b> 0 to sig <b> 3 are changed. Input timings are the same. For this reason, in any one of the delay chains 13, the time interval between the distributed clock signal ckx and the target signal sigx (x is any one of 0 to 3) is shorter than one clock cycle, and the captured data Dx [100: 0] shows a value representing this time interval. In the illustrated example, the captured data D2 [100: 0] of the delay chain 13 in the third column in FIG. 13 includes a high level bit and a low level bit, so that the target signal sig is detected from the rising edge of the clock signal ck2. The time interval until the rise or fall is represented.

  As shown in FIG. 15, the selector 15 sequentially selects captured data D0 [100: 0] to D3 [100: 0] whose measurement is completed and held in synchronization with the clock signal, and this is the time. The output data OUT [100: 0] of the digital conversion circuit 1 is output. If the time interval between the rising edge of the clock signal ck0 of No. 0, No. 4, No. 8, No. 8,... And the rising edge or falling edge of the target signal is within one clock cycle, the captured data D0 [100: 0] Represent. If the time interval between the rising edge of the first, fifth, ninth,... Clock signal ck1 and the rising or falling edge of the target signal is within one clock cycle, the captured data D1 [100: 0] Represent. If the time interval between the rising edge of the clock signal ck2 of No. 2, 6, No. 10,... And the rising edge or falling edge of the target signal is within one clock cycle, the captured data D2 [100: 0] Represent. If the time interval between the rise of the clock signal ck3 of No. 3, No. 7, No. 11,... And the rise or fall of the target signal is within one clock cycle, the captured data D3 [100: 0] Represent. Therefore, the time interval between the clock signal and the target signal is represented by the output data OUT [100: 0].

  A control method of the plurality of delay chains 13 and the selector 15 realized by the controller 11 corresponds to an example of a time digital conversion method according to the present invention.

  As described above, according to the time digital conversion circuit 1 and the time digital conversion method according to the present embodiment, the time interval between the clock signal and the target signal is set to a resolution higher than the delay amounts τ1 and τ2 of the delay circuits e and f. And it can be converted into a digital value normally. Further, although errors in device manufacturing occur in the delay amounts τ1 and τ2 of the plurality of delay circuits e and f, the errors are distributed in the plurality of delay circuits e and f. For this reason, there is no possibility that an error is unevenly distributed in a specific portion of all bits of the output data OUT [n: 0] × (i + i) times representing the time interval between the target signal and the clock signal. Therefore, according to the present embodiment, it is possible to provide the time digital conversion circuit 1 and the time digital conversion method in which low-precision bits are less likely to be unevenly distributed in the output data OUT [n: 0].

(Other embodiments)
FIG. 16 is a block diagram showing an example of the configuration of a delay chain of a time digital conversion circuit according to another embodiment of the present invention. The time digital conversion circuit of the present embodiment is obtained by replacing each delay chain 13 shown in FIG. 1 with a time digital conversion unit 23 shown in FIG. That is, the time digital conversion circuit of this embodiment includes (i + 1) time digital conversion units 23. FIG. 16 illustrates the time digital conversion unit 23 in the first column. Regarding the time-to-digital converters 23 from the 2nd column to the (i + 1) th column, the signals input to each are the target signals sig1 to sigi and the distributed clock signals ck1 to cki, and the data output from each is captured. Data D1 [n: 0] to Di [n: 0].

  Next, the time digital conversion unit 23 in the first column will be described. The time digital conversion unit 23 includes a plurality of vernier delay chains 231 and a plurality of majority circuits 233 that take the majority of the outputs of the respective delay stages of the plurality of delay chains 231. The target signal sig0 and the distributed clock signal ck0 are simultaneously input to the plurality of delay chains 231. Each delay chain 231 has the same configuration as that of the delay chain 13 in one column in FIG. 7, that is, each of the plurality of delay chains 231 includes a plurality of transmission lines 131, clock transmission paths 132, and flip-flop arrays 133. The plurality of delay chains 231 operate in substantially the same manner, and the captured data D0a [0] to D0a [n], D0b [0] to D0b [n], and D0c [0] to D0c [n] of the plurality of flip-flop trains 133 are operated. ] Is output. However, there may occur a case where the time interval between the target signal sig0 and the clock signal ck0 is just before the unit time divided for each resolution. In such a case, a difference may occur in the captured data D0a [n: 0], D0b [n: 0], and D0c [n: 0] in a plurality of columns due to errors in the delay amounts of the plurality of delay circuits e and f. is there. At this time, each majority decision circuit 233 takes a majority decision of each bit, so that a majority decision result is output as captured data D0 [n: 0].

  The time digital conversion units 23 in the second and subsequent columns are such that the input target signals sig1 to sig, the clock signals ck1 to cki and the output captured data D1 [n: 0] to Di [n: 0] are 1 The configuration is the same as that of the time digital conversion unit 23 in the first column, except for the difference from the column.

  The time digital conversion circuit of this embodiment operates in the same manner as the circuit of FIG. 1 except that the operation of each delay chain 13 in FIG. 1 is changed to the operation of the time digital conversion unit 23 in FIG. The time digital conversion circuit of the present embodiment outputs output data OUT [n: 0] obtained by converting the time interval between the input target signal and the clock signal into a digital value.

  As described above, according to the time digital conversion circuit of the present embodiment, the captured data Dx [n: 0] (x is any one of 0 to i) output from one time digital conversion unit 23 has a plurality of delays. This is a value obtained with a large number of each bit of the acquisition data of the chain 231. Therefore, even if there is an error in device manufacture in the delay amount of each delay circuit e, f of each delay chain 231, these errors are averaged to obtain captured data Dx [n: 0]. Thereby, according to the present embodiment, it is possible to provide a time digital conversion circuit and a time digital conversion method in which bits with low accuracy are less likely to be unevenly distributed in the output data OUT [n: 0].

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, a specific feature (technical matter) in one embodiment is appropriately improved and added to another embodiment or the other implementation. Specific features in the form can be substituted, and such form is also included in the gist of the present invention.

  The present invention can be widely used in the field of TOF (Time of Flight), laser radar, and other devices that require an operation for converting a time interval into a digital value.

DESCRIPTION OF SYMBOLS 1 ... Time digital conversion circuit 11 ... Controller 13 ... Vernier-type delay chain 23 ... Time digital conversion part 15 ... Selector 111 ... Buffer 112 ... Counter 113 ... Distribution part 114 ... Encoder 131 ... Transmission path 132 ... Clock transmission path 133 ... Flip-flop 231 ... Vernier delay chain 233 ... Majority circuit e, f ... Delay circuit g ... Flip-flop (capture unit)
sig0 to sigi ... target signal ck0 to cki ... distributed clock signal D0 [n: 0] to Di [n: 0] ... captured data OUT [n: 0] ... output data

Claims (8)

A plurality of time digital conversion units;
A selector capable of selecting an output of any of the plurality of time digital conversion units;
A controller for distributing the measurement target signal and the clock signal and controlling the selector,
Each of the plurality of time digital conversion units is
A transmission line in which a plurality of delay circuits are connected in series;
A clock transmission path in which a plurality of clock delay circuits having a delay amount different from that of the delay circuit are connected in series;
A delay corresponding to each of the plurality of delay stages of the transmission line and a plurality of delay stages of the clock transmission line, and corresponding to the delay of the transmission line based on a clock signal reaching the corresponding delay stage of the clock transmission line; A capture unit group including a plurality of capture units for capturing the signal level of the stage;
Have
The controller sends the target signal to the transmission paths of the plurality of time digital conversion units, sequentially distributes a clock signal to the clock transmission paths of the plurality of time digital conversion units, and the plurality of time digital conversions The selector is controlled so that the outputs of the time digital conversion units that have been captured by the capturing unit group based on the distributed clock signal are sequentially selected.
Time digital conversion circuit. The controller distributes clock signals to the plurality of time digital conversion units in a predetermined order, and causes the selector to select outputs of the plurality of time digital conversion units in the same order as the predetermined order,
The output selection cycle by the selector is advanced by one cycle of the clock signal from the clock signal distribution cycle by the controller.
The time digital conversion circuit according to claim 1. The controller includes a distribution circuit that distributes a clock signal, and a buffer that delays the target signal and sends it to the plurality of time digital conversion units.
The time digital conversion circuit according to claim 1 or 2. Each of the plurality of time digital conversion units is
A plurality of vernier delay chains including a plurality of sets of the transmission path, the clock transmission path, and the capturing unit group;
A plurality of majority voting circuits for voting the capture results of the capture units at each stage in the plurality of vernier delay chains;
Outputting determination results of the plurality of majority circuits,
The time digital conversion circuit according to any one of claims 1 to 3. The period p of the clock signal, the number (i + 1) of the time digital conversion units, and the time T for the target signal to reach the last delay stage from the beginning of the transmission path are:
satisfying the relationship of p × (i + 1) ≧ T.
The time digital conversion circuit according to any one of claims 1 to 4. The maximum time interval that the time digital conversion unit can convert to a digital value is equal to or greater than the period of the clock signal.
The time digital conversion circuit according to any one of claims 1 to 5. A plurality of time digital conversion units;
A selector capable of selecting an output of any of the plurality of time digital conversion units,
Each of the plurality of time digital conversion units is
A transmission line in which a plurality of delay circuits are connected in series;
A clock transmission path in which a plurality of clock delay circuits having a delay amount different from that of the delay circuit are connected in series;
A delay corresponding to each of the plurality of delay stages of the transmission line and a plurality of delay stages of the clock transmission line, and corresponding to the delay of the transmission line based on a clock signal reaching the corresponding delay stage of the clock transmission line; A capture unit group including a plurality of capture units for capturing the signal level of the stage;
A time digital conversion method using a circuit having
Send the signal to be measured to the transmission path of the plurality of time digital conversion units,
A clock signal is sequentially distributed to the clock transmission paths of the plurality of time digital conversion units,
The selector is controlled so that outputs of the time digital conversion units that have been captured by the plurality of capture units are sequentially selected based on the distributed clock signal among the plurality of time digital conversion units.
Time digital conversion method. Distributing clock signals in a predetermined order to the plurality of time digital conversion units, and causing the selector to select outputs of the plurality of time digital conversion units in the same order as the predetermined order;
The output selection cycle by the selector is advanced by one cycle of the clock signal from the clock signal distribution cycle.
The time digital conversion method according to claim 7.

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