CN114967410A - Digital time conversion device and method - Google Patents
Digital time conversion device and method Download PDFInfo
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- CN114967410A CN114967410A CN202210689464.2A CN202210689464A CN114967410A CN 114967410 A CN114967410 A CN 114967410A CN 202210689464 A CN202210689464 A CN 202210689464A CN 114967410 A CN114967410 A CN 114967410A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 9
- 239000002041 carbon nanotube Substances 0.000 description 9
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a digital time conversion device and a method, wherein the device comprises an FPGA chip, and the FPGA chip is internally provided with: the data processing module is used for determining configuration parameters according to input data, and the configuration parameters comprise counting set values; the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach corresponding count set values and then output high levels; and the fine time interval generating module comprises two delay chains, the two delay chains respectively delay the high levels output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module. The invention uses the FPGA chip to complete the conversion of digital time, and has the advantages of low production cost, short development period and high flexibility.
Description
Technical Field
The present invention relates to the field of digital signal processing technologies, and in particular, to a digital time conversion apparatus and method.
Background
Digital Time Conversion (DTC) technology is widely used in circuits. There are many methods for generating the time interval in the prior art, and the methods can be divided into an analog method and a digital method according to different implementation manners. The time interval generation system constructed by using a digital method has better temperature stability and is beneficial to large-scale integration. At present, the high-resolution time interval generation system is mainly implemented by using an ASIC (Application Specific Integrated Circuit) chip.
However, the digital time conversion system implemented by the ASIC chip has problems of high production cost, long development period, and poor flexibility.
Disclosure of Invention
The embodiment of the invention provides a digital time conversion device and a digital time conversion method, which are used for solving the problems of high production cost, long development period, poor flexibility and the like in the prior art of realizing a digital time conversion system by utilizing an ASIC chip.
In one aspect, an embodiment of the present invention provides a digital time conversion apparatus, including an FPGA chip, where:
the data processing module is used for determining configuration parameters according to input data, and the configuration parameters comprise counting set values;
the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach corresponding count set values and then output high levels;
and the fine time interval generating module comprises two delay chains, the two delay chains respectively delay the high levels output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
In another aspect, an embodiment of the present invention provides a digital time conversion method, including:
determining configuration parameters by adopting an FPGA chip according to input data, wherein the configuration parameters comprise a counting set value;
counting by adopting two counters in the FPGA chip, and outputting a high level when the count values of the two counters respectively reach corresponding counting set values;
and respectively carrying out delay processing on the high levels output by the two counters by adopting two delay chains in the FPGA chip, and outputting corresponding step signals, wherein the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
The digital time conversion device and the method thereof have the following advantages:
compared with an ASIC chip, the high-resolution digital-to-time converter based on the FPGA has the advantages of low production cost, short development period and high flexibility.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a functional block diagram of a digital-to-time conversion apparatus according to an embodiment of the present invention;
FIG. 2 is a functional block diagram of a fine time interval generation module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a fine time interval generation module according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a coarse time interval generation module and a fine time interval generation module provided by an embodiment of the present invention;
fig. 5 is a circuit diagram of a transmission stage of an internal register of an FPGA chip according to an embodiment of the present invention;
fig. 6 is a flowchart of a digital time conversion method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of functional modules of a digital-to-time conversion apparatus according to an embodiment of the present invention. The embodiment of the invention provides a digital time conversion device, which comprises an FPGA chip, wherein the FPGA chip is internally provided with:
the data processing module is used for determining configuration parameters according to input data, and the configuration parameters comprise counting set values;
the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach corresponding count set values and then output high levels;
and the fine time interval generating module comprises two delay chains, the two delay chains respectively delay the high levels output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
For example, the required time interval preset information may be transmitted to the data processing module in advance, and the transmitted data may be decoded to form the configuration parameters.
In the embodiment of the invention, the FPGA chip can adopt a Kintex-7 series FPGA chip produced by Xilinx company, and a programmable absolute input and output unit inside the chip can be adopted to form a delay chain. Specifically, each delay chain includes an input delay block (IDELAY2 block) and an output delay block (ODELAY2 block), which are connected in series to form the delay chain, as shown in fig. 2.
The IDELAY2 module and ODELAY2 module are programmable 31-step delay units, and the delay parameters can be referred to Kintex-7 series FPGA I/O module user manual manufactured by Xilinx corporation. The IDELAY2 module and the ODELAY2 module are circulating delay compensation modules with 31-level delay units, the IDELAY2 module can be used for delaying logic signals inside the FPGA chip with specified resolution, the ODELAY2 module is used for delaying output signals of the FPGA chip, and the FPGA chip can directly access the IDELAY2 module and the ODELAY2 module.
In a possible embodiment, the fine time interval generation module further comprises a delay control module for calibrating the delay units in the two delay chains using the input reference clock.
Illustratively, the delay resolution of each delay cell in the IDELAY2 module and the ODELAY2 module is compensated and calibrated by an input reference clock provided by the delay control module (IDELAYCTRL module).
As shown in fig. 2, the IDELAYCTRL module calibrates the delay time of the delay cells in the IDELAY2 module and the ODELAY2 module based on the input reference clock to reduce the voltage and temperature effects on the accuracy of the delay cells. The IDELAY2 module and the ODELAY2 module must be used in conjunction with the IDELAYCTRL module, and two sets of IDELAYCTRL modules are required for time alignment when creating two sets of delay chains with different unit delay times (hereinafter referred to as the IDELAYCTRLA module and the IDELAY trlb module).
The high level signal output by the coarse time interval generating module is input into the IDELAY2 module, and the signal enters the ODELAY2 module for delaying and output after being delayed by the IDELAY2 module. The IDELAY2 module and the ODELAY2 module are connected in series to form a delay chain.
As shown in fig. 3, the IDELAY2 module (including a plurality of unit delay times τ) can be implemented by using the differential delay method A A multiplexer (MUX block)) and an ODELAY2 block (comprising a plurality of unit delay times tau A And a multiplexer (MUX module)) to form a delay chain: delay chain a. Then an IDELAY2 module (containing a plurality of unit delay times of tau) with different unit delay time than the delay chain A B A multiplexer (MUX block)) and an ODELAY2 block (comprising a plurality of unit delay times tau B And a multiplexer (MUX module)) to form another delay chain: delay chain B. The resolution of the digital time converter constructed by the method is determined by the difference of unit delay time of two delay chains (delta tau) B -τ A )。
By using the differential delay method, the reasonable layout and wiring can be carried out in the FPGA chip so as to offset the wiring delay and the device delay and ensure that the generated time interval is more accurate.
In a possible embodiment, the configuration parameter further includes a delay progression, the delay chain includes a multiplexer and a plurality of delay units, the plurality of delay units are sequentially connected in series, and the multiplexer is configured to control the delay units with the same delay progression as the number of delay progression to be connected into the delay chain.
Illustratively, as shown in FIGS. 4 and 5, the coarse interval generation module consists of two counters cnt _ time1 and cnt _ time2, both using the same clock S refclk From S pulse As enable signals for both counters. When the count value of the counter reaches the count set value, a high level signal is output to enter the fine time interval generation module shown in fig. 3. The fine time interval generating module selects the delay units with the same number and the same delay series from the multiplexer to be connected into the delay chain, and outputs two step signals S start (or step1) and S stop The time interval between (or step2) is the desired time interval, i.e. the coarse time interval (T) coarse ) And a fine time interval (T) fine ) And (4) the sum.
After the data processing module determines the configuration parameters, the counter sets the counting set value as a counting threshold value, the data processing module configures the two delay chains into a variable delay mode, and after the multiplexer finishes controlling the access number of the delay units, the delay chains exit the variable delay mode.
Specifically, the upper computer transmits the required time interval data to a data processing module of the FPGA chip, and the data processing module firstly calculates to obtain CNT A 、CNT B M, n. CNT (carbon nanotube) A 、CNT B And directly transmitting the data to a coarse time interval generation module to be used as counting thresholds of a counter A and a counter B respectively. The data processing module also configures the IDELAY2 module and the ODELAY2 module into a variable delay mode (VAR _ LOAD) by setting the parameter LD of both delay chains to 1, and when the data configuration is completed, the parameter LD is set to 0 and the delay chains exit the variable delay mode.
In a possible embodiment, further comprising: and the differential clock module is used for providing a clock signal for the FPGA chip.
Illustratively, the FPGA module further includes: the clock buffer is used for buffering the clock signals input by the differential clock module; and the mode clock manager is used for carrying out frequency multiplication on the buffered clock signals to obtain two input reference clocks with different frequencies, and the two input reference clocks with different frequencies are respectively used for the two delay control modules to calibrate the delay units in the two delay chains.
In the embodiment of the invention, the differential clock signals input by the differential clock module are input into a clock buffer (IBUFDS) for buffering and then enter a mode clock manager (MMCM) for frequency multiplication, so as to generate two clock signals of 300MHz and 400 MHz. And taking a clock signal of 400MHz as a global clock of the FPGA chip and an input reference clock of the IDELAYCTRLA module, and taking a clock signal of 300MHz as an input reference clock of the IDELAYTRLB module. The IDELAYCTRLA module adjusts the unit delay time of the delay chain A, and the IDELAYTRLB module adjusts the unit delay time of the delay chain B.
The delay chain A adopts a 400MHz input reference clock, and the unit delay time tau of each stage of delay unit can be known according to Kintex-7 series FPGA DC/AC conversion characteristic specification A The delay chain B adopts an input reference clock of 300MHz (39 ps), and the unit delay time tau of each stage of delay unit can be known B 52 ps. The minimum time interval resolution of the device, Δ τ ═ τ B -τ A ＝13ps。
The counting clock of the coarse time interval generation module is 400MHz, and the resolution T of the coarse time interval can be known 0 ＝1/f＝2.5ns。
To ensure the linearity of the device, the fine time intervals should be generated continuously, so that the number of delay units in the delay chain should not be less than m (m ═ T) 0 /τ B -1 ═ 47). And Δ τ should satisfy τ B Continuity of the time interval, i.e. the number of Δ τ that can be generated thereby is not less than n (n ═ τ) B And/Δ τ -1 ═ 3). Therefore, the minimum required number of delay unit stages is m + n equal to 50. Because each IDELAY2 module and each ODELAY2 module in the invention are provided with 31 stages of delay units, after the IDELAY2 module and the ODELAY2 module are connected in series, a delay chain with 62 stages of delay units can be formed, and the requirement of device linearity is met.
Let T, CNT be the size of the time interval to be generated A 、CNT B For generating configuration parameters, T, of two counters in a module for a coarse time interval 0 For unit coarse time interval, m and n are the stages of delay units selected by the multi-way selector in the delay chain A and the delay chain B respectivelyNumber, tau A 、τ B The unit delay time of the delay chain A and the delay chain B respectively, and the minimum time interval resolution delta tau of the device B -τ A And the percent is the remainder of the division, then:
CNT B -CNT A the value of (A) directly determines the size of the coarse time interval, and CNT is generally taken for simplifying the design A If 0, the configuration parameters of the coarse time interval and the fine time interval can be obtained:
the upper computer provides input of required time intervals and transmits time interval data to the FPGA chip, and the data processing module in the FPGA chip configures configuration parameters to the coarse time interval generating module and the fine time interval generating module of the FPGA chip through the operation.
In a possible embodiment, the FPGA chip further internally includes: and the communication module is used for receiving the data sent by the upper computer and sending the received data to the data processing module.
Illustratively, the communication module communicates with the upper computer by adopting a UART protocol to receive data sent by the upper computer.
An embodiment of the present invention further provides a digital time conversion method, as shown in fig. 6, the method includes:
determining configuration parameters by adopting an FPGA chip according to input data, wherein the configuration parameters comprise a counting set value;
counting by adopting two counters in the FPGA chip, and outputting a high level when the count values of the two counters respectively reach corresponding counting set values;
and respectively carrying out delay processing on the high levels output by the two counters by adopting two delay chains in the FPGA chip, and outputting corresponding step signals, wherein the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. The digital time conversion device is characterized by comprising an FPGA chip, wherein the FPGA chip is internally provided with:
the data processing module is used for determining configuration parameters according to input data, and the configuration parameters comprise counting set values;
the coarse time interval generation module comprises two counters, and the count values of the two counters respectively reach the corresponding count set values and then output high levels;
and the fine time interval generation module comprises two delay chains, the two delay chains respectively carry out delay processing on the high level output by the two counters and output corresponding step signals, and the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
2. The apparatus according to claim 1, wherein the configuration parameters further include a delay progression, the delay chain includes a multiplexer and a plurality of delay units, the plurality of delay units are connected in series, and the multiplexer is configured to control the delay units with the same number as the delay progression to be connected to the delay chain.
3. The apparatus according to claim 2, wherein said data processing module determines said configuration parameters, and wherein said counter sets said count setting value as a count threshold, and wherein said data processing module configures two of said delay chains into a variable delay mode, and wherein said delay chains exit from said variable delay mode after said multiplexer completes controlling the number of delay cell accesses.
4. A digital-to-time conversion apparatus according to claim 1, wherein said fine time interval generating module further comprises a delay control module, said delay control module being configured to use an input reference clock to calibrate the delay elements in both said delay chains.
5. A digital-to-time conversion apparatus according to claim 4, further comprising:
and the differential clock module is used for providing a clock signal for the FPGA chip.
6. The digital-to-time conversion apparatus of claim 5, wherein said FPGA module further comprises:
the clock buffer is used for buffering the clock signal input by the differential clock module;
and the mode clock manager is used for performing frequency multiplication processing on the buffered clock signals to obtain two input reference clocks with different frequencies, and the two input reference clocks with different frequencies are respectively used for the two delay control modules to calibrate the delay units in the two delay chains.
7. The digital-to-time conversion apparatus of claim 1, wherein the FPGA chip further comprises:
and the communication module is used for receiving the data sent by the upper computer and sending the received data to the data processing module.
8. The apparatus according to claim 7, wherein the communication module communicates with the host computer using a UART protocol.
9. A digital-to-time conversion method, comprising:
determining configuration parameters by adopting an FPGA chip according to input data, wherein the configuration parameters comprise a counting set value;
counting by adopting two counters in the FPGA chip, and outputting a high level when the count values of the two counters respectively reach the corresponding count set values;
and respectively carrying out delay processing on the high levels output by the two counters by adopting the two delay chains in the FPGA chip, and outputting corresponding step signals, wherein the time interval between the two step signals is the time interval corresponding to the data input into the data processing module.
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