CN113900369A - Time-to-digital converter, calibration method and chip - Google Patents
Time-to-digital converter, calibration method and chip Download PDFInfo
- Publication number
- CN113900369A CN113900369A CN202111190409.0A CN202111190409A CN113900369A CN 113900369 A CN113900369 A CN 113900369A CN 202111190409 A CN202111190409 A CN 202111190409A CN 113900369 A CN113900369 A CN 113900369A
- Authority
- CN
- China
- Prior art keywords
- frequency
- count value
- ring oscillator
- count
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
Abstract
The invention discloses a time-to-digital converter, a calibration method and a chip, wherein the time-to-digital converter comprises: delay chain, memory and calibration circuit, calibration circuit includes ring oscillator and frequency counter, wherein: the memory stores a corresponding table of the fine count and the fine timing and an initial frequency count value of the ring oscillator when the calibration is started; the delay chain is used for generating a corresponding target fine count when a signal to be tested is received; the ring oscillator is used for generating a corresponding frequency signal under the influence of the temperature of the delay chain and inputting the frequency signal to the frequency counter; the frequency counter is used for counting the frequency signals to obtain a test frequency count value, so that the calibration method updates the target fine count based on the test frequency count value and the initial frequency count value, and searches the corresponding target fine count in the corresponding table based on the updated target fine count to improve the TDC timing precision.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a time-to-digital converter, a calibration method and a chip.
Background
In recent years, the incidence of cancer is increasing, a new type of Positron Emission Tomography (PET) scan is an important means for detecting cancer in advance, and the PET imaging technology has accurate imaging information and high accuracy, and is an important means for detecting cancer.
The front-end electronics of PET imaging systems mainly read energy and Time, wherein the reading Time is generally implemented by a Time To Digital Converter (TDC). As can be seen from the current state analysis of domestic and foreign research, in a multi-channel high-speed and high-precision (FPGA) TDC system, the delay chain mode is a non-binary choice for implementing the FPGA TDC.
The TDC accuracy seriously affects the imaging quality of PET, and the working environment of the chip changes along with the continuous work of the PET system. When the temperature changes, the chip can stabilize high-precision timing, which is the premise of ensuring high-precision imaging of the system, so that effective measures must be taken to improve the timing precision of the TDC, thereby improving the imaging quality.
Disclosure of Invention
The embodiment of the application provides a time-to-digital converter, a calibration method and a chip, and the target fine count is updated by additionally arranging a calibration circuit in a TDC structure, so that the corresponding target fine count is searched in a corresponding table based on the updated target fine count, the time delay is reduced, and the TDC timing precision is effectively improved.
In a first aspect, the present invention provides the following technical solutions through an embodiment of the present invention:
a time-to-digital converter applied to a field programmable gate array chip, the time-to-digital converter comprising: delay chain, memory and calibration circuit, the calibration circuit includes ring oscillator and frequency counter, the ring oscillator is connected with the frequency counter, frequency counter and delay chain all are connected with the memory, calibration method wherein: the memory is stored with a corresponding table of the fine count and the fine timing and an initial frequency count value of the ring oscillator when the calibration is started; the delay chain is used for generating a corresponding target fine count when a signal to be tested is received and recording the target fine count into the corresponding table; the ring oscillator is used for generating a corresponding frequency signal under the influence of the temperature of the delay chain and inputting the frequency signal to the frequency counter; the frequency counter is used for counting the frequency signals to obtain a test frequency count value, and the calibration method updates the target fine count in the corresponding table based on the test frequency count value and the initial frequency count value.
Preferably, the delay chain comprises a plurality of carry multiplexers connected in series.
Preferably, the ring oscillator comprises an odd number of sequentially cascaded carry multiplexers, wherein the first carry multiplexer is connected with the last carry multiplexer.
Preferably, the frequency counter is configured to: and counting the number of rising edges of the ring oscillator in the period of the reference clock based on the received frequency signal and a preset reference clock to obtain the test frequency count value.
Preferably, the reference clock period range is 214-216。
Preferably, the frequency counter comprises a system clock, a state machine and a D flip-flop, and the system clock is connected with the state machine and the D flip-flop respectively.
Preferably, the precision of the system clock is 80-100 ppm.
In a second aspect, the present invention provides the following technical solutions through an embodiment of the present invention:
a time-to-digital converter calibration method applied to the time-to-digital converter of any one of the preceding first aspects, the calibration method comprising:
acquiring an initial frequency count value of the ring oscillator and a test frequency count value obtained by a frequency counter; updating a target fine count based on the initial frequency count value and a test frequency count value; and searching the corresponding target detail count in the corresponding table based on the updated target detail count.
Preferably, the updating the target fine count based on the initial frequency count value and the test frequency count value includes: obtaining a temperature adjustment coefficient based on the ratio of the initial frequency count value to the test frequency count value; and adjusting the target fine count by using the temperature adjustment coefficient to obtain an updated target fine count.
In a third aspect, the present invention provides the following technical solutions through an embodiment of the present invention:
a field programmable gate array chip comprising a controller and the time-to-digital converter of any of the preceding first aspects, the controller being connected to the time-to-digital converter.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
the embodiment of the invention provides a time-to-digital converter, a calibration method and a chip, wherein the time-to-digital converter comprises: delay chain, memory and calibration circuit, calibration circuit include ring oscillator and frequency counter, and ring oscillator is connected with frequency counter, and frequency counter and delay chain all are connected with the memory, wherein: the memory stores a corresponding table of the fine count and the fine timing and an initial frequency count value of the ring oscillator when the calibration is started; the delay chain is used for generating a corresponding target fine count when a signal to be tested is received and recording the target fine count into a corresponding table; the ring oscillator is used for generating a corresponding frequency signal under the influence of the temperature of the delay chain and inputting the frequency signal to the frequency counter; the frequency counter is used for counting the frequency signals to obtain a test frequency count value, and updating the target fine count in the corresponding table based on the test frequency count value and the initial frequency count value. According to the TDC structure, the calibration circuit is additionally arranged in the TDC structure, and the calibration circuit can update the target fine counting under the influence of the temperature of the delay chain. And then look for the corresponding target count in the corresponding table based on the updated target count, the time-to-digital converter can effectively improve the timing precision and improve the imaging quality.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a time-to-digital converter according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a delay chain according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a ring oscillator according to an embodiment of the present invention;
FIG. 4 is a simulation diagram of a frequency counting function of a ring oscillator according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for calibrating a time-to-digital converter according to an embodiment of the invention.
Detailed Description
The inventor finds that common schemes for calibrating the temperature based on the TDC of the delay chain of the FPGA include: off-line calibration, statistical calibration, etc. The off-line calibration is to design a function module for monitoring the delay time change in the lookup table, the delay time change is not calibrated in the acceptance range, and the start calibration is restarted when the delay time change is large. The statistical calibration is to consider that the delay time of all delay chains is basically consistent under the influence of temperature change, a special delay chain is adopted for monitoring the influence of temperature on the delay time, the influence of the temperature on the delay time is compensated in real time by fitting a corresponding relation coefficient of the temperature and the code width through multiple experiments, and then the influence of the temperature on the delay time is compensated by searching a corresponding coefficient according to the real-time temperature of a chip.
Among these, off-line calibration can serve to monitor the effect of temperature on delay time, but start-up calibration requires statistically large numbers of random tests and needs to be completed in a short time (e.g., milliseconds). Meanwhile, the power consumed by the TDC during the starting calibration is far greater than that during the actual measurement, and the method has the disadvantages that: real-time compensation cannot be performed and the TDC system cannot start measuring signals when calibration is started again. Although the statistical calibration can calibrate the influence of the temperature on the time delay in real time, the method is too complicated and the data in the lookup table obtained by calibrating each time are different, so that the influence of the temperature on the time delay cannot be accurately compensated by looking up the corresponding relation coefficient of the temperature and the code width.
The above estimation methods have many defects, and most of the methods are based on TDC data under a laboratory constant condition, and have no practical operation significance. For real-time calibration, a real-time calibration technology can be realized, and the method has a certain engineering value.
In order to solve the above problem, embodiments of the present application provide a time-to-digital converter, a calibration method, and a chip, and update of a target fine count is implemented by adding a calibration circuit in a TDC structure, so that a corresponding target fine count is searched in a corresponding table based on the updated target fine count, time delay is reduced, and precision of TDC timing is effectively improved.
In order to solve the technical problems, the general idea of the embodiment of the application is as follows:
a time-to-digital converter applied to a programmable gate array chip, the time-to-digital converter comprising: delay chain, memory and calibration circuit, calibration circuit include ring oscillator and frequency counter, and ring oscillator is connected with frequency counter, and frequency counter and delay chain all are connected with the memory, wherein: the memory stores a corresponding table of the fine count and the fine timing and an initial frequency count value of the ring oscillator when the calibration is started; the delay chain is used for generating a corresponding target fine count when a signal to be tested is received and recording the target fine count into a corresponding table; the ring oscillator is used for generating a corresponding frequency signal under the influence of the temperature of the delay chain and inputting the frequency signal to the frequency counter; the frequency counter is used for counting the frequency signals to obtain a test frequency count value, and updating the target fine count in the corresponding table based on the test frequency count value and the initial frequency count value.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
In a first aspect, as shown in fig. 1, a time-to-digital converter 20 provided in an embodiment of the present invention is applied to a Programmable Gate Array (FPGA) 10, and specifically, the time-to-digital converter 20 includes: a delay chain 201, a Memory (RAM) 202, and a calibration circuit 203, where the calibration circuit 203 includes a ring oscillator 2031 and a frequency counter 2032, the ring oscillator 2031 is connected to the frequency counter 2032, and the frequency counter 2032 and the delay chain 201 are both connected to the Memory 202, where:
the RAM stores a correspondence table of the fine count and an initial frequency count value of the ring oscillator 2031 at the time of starting calibration; the delay chain 201 is used for generating a corresponding target fine count when a signal to be tested is received and recording the target fine count into a corresponding table; the ring oscillator 2031 is configured to generate a corresponding frequency signal under the influence of the temperature of the delay chain 201, and input the frequency signal to the frequency counter 2032.
The frequency counter 2032 is configured to count the frequency signal to obtain a test frequency count value, and update the target fine count in the correspondence table based on the test frequency count value and the initial frequency count value.
As an alternative embodiment, the ring oscillator 2031, the frequency counter 2032, and the memory 202 are connected to the controller 30 in the chip.
It should be noted that the fine count mentioned in this application indicates the time interval, i.e. the time delay, between the rising edge of the signal to be detected and the rising edge of the test signal generated by the calibration circuit. In addition, the time-to-digital converter 20 further includes an encoder 204, and the encoder 204 is connected to the delay chain 201.
In a specific embodiment, the process of establishing the correspondence table between the count and count in the RAM may be: when the FPGA chip is powered on, the ring oscillator 205 generates a periodic calibration signal, for example, the calibration signal is a square wave signal, each set of calibration signals passes through the multi-bit Multiplexer (MUXCY)206, the delay chain 201, and the encoder 204 to obtain a fine count i, 1 is added to the address i of the lookup table formed by the RAM, after a preset clock period, the generation of the calibration signal is stopped to obtain a fine timing corresponding to the fine count, thereby establishing a pair of the fine count and the fine timingAnd (6) applying a table. For example, the predetermined clock period is 216One clock cycle.
When the FPGA chip is powered on, the ring oscillator 2031 is also started in real time, the ring oscillator generates a frequency signal under the action of the calibration signal and transmits the frequency signal to the frequency counter 2032, the frequency counter counts the frequency signal to obtain an initial frequency count value, and the frequency signal is input to the lookup table in the RAM.
Specifically, as shown in fig. 2, the delay chain in the present application may include a plurality of carry multiplexers MUXCY connected in sequence. Specifically, MUXCY of a CARRY-ahead logic structure CARRY4 module in an Xilinx FPGA chip is used as a delay unit, each CARRY4 module is provided with four MUXCY units, the MUXCY is a logic gate with certain delay, and under the condition of neglecting line delay, the total delay of 4 MUXCY is the delay of one CARRY4 module. For example, the delay chain of the present application includes 31-45 CARRY4 modules. Where CI in fig. 2 is the input and Cout is the output.
Preferably, once the first CARRY4 module is placed, all CARRY4 modules are automatically placed and routed into a delay chain by the compilation tool as long as the number of CARRY4 is set. Therefore, the delay chain is convenient to be transplanted to other Xilinx chips, so that the purpose of the delay chain is wider.
Specifically, the present application places the ring oscillator 2031 adjacent to the delay chain 201 such that the ring oscillator 2031 generates a corresponding frequency signal under the influence of the temperature of the delay chain. Considering that the delay chain TDC is formed by MUXCY, the invention adopts MUXCY to form a ring oscillator, if the time delay of the MUXCY is changed, the frequency of the adjacent MUXCY is also changed, and the accuracy and the reliability of online calibration are improved.
It should be noted that the adjacent positions of the delay chain 201 mentioned in the present application may be a plurality of positions near the delay chain 201, and the ring oscillator placed in the adjacent position of the delay chain will be completely affected by the delay chain.
Specifically, as shown in fig. 3, the ring oscillator of the present application includes an odd number of sequentially cascaded carry multiplexers MUXCY, where the first carry multiplexer MUXCY is connected to the last carry multiplexer MUXCY. For example, the ring oscillator included in the present application includes 90 MUXCY. If the enable is 1, the ring oscillator generates a square wave signal osc _ out, the enable is 0, and the generation of the square wave signal osc _ out is stopped.
Specifically, during the formal measurement, the signal to be detected is input to the delay chain 201 through the multi-bit multiplexer 206 to obtain a thermometer code, a fine count is obtained through the encoder 204, and a fine timing corresponding to the fine count is obtained from the lookup table, which is also called a code density test and is referred to herein as start calibration. However, since the delay of the delay chain is affected by temperature and voltage, if the temperature and voltage are changed, an error is increased by always using the fine timing in the lookup table, and thus the real-time calibration of the delay chain is an important point of the TDC.
Therefore, the temperature change of the delay chain is converted into the frequency change of the ring oscillator, and the time delay change of the delay unit in the lookup table is updated linearly by monitoring the frequency change of the ring oscillator, so that the online temperature compensation effect is achieved. Specifically, the principle of online temperature compensation of the present application is: when the temperature changes, the frequency of the ring oscillator at the position adjacent to each delay chain also changes, and the fluctuation of the frequency of the output signal of the ring oscillator along with the temperature voltage is inversely related to the fluctuation of the delay time along with the temperature voltage, namely when the frequency fluctuation of the ring oscillator is larger, the delay time is shorter; the frequency of the ring oscillator is counted by using a high-precision system clock, so that the time delay of a delay chain can be accurately delayed, and the error caused by the temperature and voltage change is effectively reduced.
Therefore, after the signal to be tested is input, the frequency counter obtains a test frequency count value, and the target fine count is updated based on the test frequency count value and the initial frequency count value stored in the memory.
In a specific embodiment, the calibration method comprises: acquiring an initial frequency count value of the ring oscillator and a test frequency count value obtained by the frequency counter; updating the target fine count based on the initial frequency count value and the test frequency count value; and searching the corresponding target detail count in the corresponding table based on the updated target detail count.
Specifically, the frequency counter 2032 counts the number of rising edges of the ring oscillator in a reference clock period based on the received frequency signal and a preset reference clock, and obtains the test frequency count value.
As an alternative embodiment, the frequency counter 2032 may comprise a system clock, a state machine, and a D flip-flop, and the system clock is connected to the state machine and the D flip-flop, respectively. Preferably, to improve the counting accuracy, a higher accuracy system clock will be selected, for example: the system clock precision provided by the embodiment of the application is 80-100 ppm.
Specifically, the state machine synchronizes into the ring oscillator domain by converting a single clock cycle pulse of the reference clock domain of the system clock to a single clock cycle pulse in the ring oscillator domain and converting the pulse to a level change, then latching the level change via a two-stage D flip-flop, and finally restoring the pulse to the ring oscillator domain. The number of rising edges of the ring oscillator is counted in the reference clock period and the result is returned, all signals being synchronized to the reference clock. For example, the reference clock period range is 214-216。
As shown in FIG. 4, for the simulation of the frequency counting function of the ring oscillator, wherein clk _ i is the system reference clock, clk _ m _ i is the pulse signal outputted by the ring oscillator, when the state signal m _ started is "1" and m _ stop is "0", the state machine state starts counting the ring oscillator in the "measuring" state, and 2 passes16After the reference clock period count timer, the state signal stop is "0", at this time, the reference clock stops counting, and the ring oscillator frequency count value freq _ o is output. It should be noted that the longer the reference clock period, the higher the accuracy of the frequency count value will be.
Specifically, the controller 30 of the present application is configured to initiate a calibrated state transition, including: clearing the RAM generating each path of TDC, accumulating the RAM data and enabling the storage of the RAM data. And a state transition for online calibration, comprising: and generating the enabling of the frequency counting of the ring oscillator, performing multiplication division operation when the lookup table is linearly updated, entering the enabling of the online calibration of the next TDC, and stopping the enabling of the online calibration.
For example, when calibration is started, a calibration signal is input, EN of the ring oscillator 2031 is 1, the ring oscillator generates an initial frequency signal, the initial frequency signal is input to the frequency counter to generate an initial frequency count value, the initial frequency count value is stored in the memory, the generation of the calibration signal is stopped after a preset clock period, and EN of the ring oscillator 2031 is 0. During online calibration, a signal to be detected is input, the EN of the ring oscillator 2031 is 1, the ring oscillator generates a test frequency signal, the test frequency signal is input to the frequency counter to generate a test frequency count value, and the test frequency count value is input to the memory.
In a specific embodiment, updating the target fine count based on the initial frequency count value and the test frequency count value includes: obtaining a temperature adjustment coefficient based on the ratio of the initial frequency count value to the test frequency count value; and adjusting the target fine count by using the temperature adjustment coefficient to obtain an updated target fine count.
That is, the correspondence between the target fine count τ i after the update and the target fine count τ i before the update is expressed by the following formula:
wherein f isonFor testing the frequency count value, foffIs the initial frequency count value.
The time-to-digital converter provided by the application can realize real-time calibration of time based on a real-time calibration technology of a ring oscillator. And an online calibration method based on the ring oscillator is adopted, so that accumulated errors can be avoided, a TDC system which is complex in establishment and high in precision requirement can be established, and factors such as external calibration do not need to be considered too much. In addition, the start calibration and the on-line calibration (real-time calibration when the TDC works normally) provided by the application are self-calibration, so that the complexity and the reliability are effectively simplified.
The application combines the application of multi-channel, high-speed and high-precision imaging of a PET imaging system, adopts a delay chain structure to design a TDC structure in a Xilinx FPGA chip, and improves the timing precision by designing a special circuit for calibrating temperature change to TDC so as to improve the imaging quality.
In a second aspect, as shown in fig. 5, an embodiment of the present invention provides a calibration method applied to the time-to-digital converter in any one of the foregoing first aspects, the calibration method including:
acquiring an initial frequency count value of the ring oscillator and a test frequency count value obtained by a frequency counter; updating a target fine count based on the initial frequency count value and a test frequency count value; and searching the corresponding target detail count in the corresponding table based on the updated target detail count.
As an alternative embodiment, the updating the target fine count based on the initial frequency count value and the test frequency count value includes: obtaining a temperature adjustment coefficient based on the ratio of the initial frequency count value to the test frequency count value; and adjusting the target fine count by using the temperature adjustment coefficient to obtain an updated target fine count.
The calibration method provided by the embodiment of the invention has the same implementation principle and technical effect as the time-to-digital converter embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the time-to-digital converter embodiment where no part of the embodiment of the apparatus is mentioned.
In a third aspect, based on the same inventive concept, this embodiment provides a field programmable gate array chip, including a controller and the time-to-digital converter of any one of the foregoing first aspects, where the controller is connected to the time-to-digital converter.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A time-to-digital converter applied to a field programmable gate array chip, the time-to-digital converter comprising: delay chain, memory and calibration circuit, calibration circuit includes ring oscillator and frequency counter, ring oscillator with the frequency counter is connected, frequency counter and delay chain all are connected with the memory, wherein:
the memory is stored with a corresponding table of the fine count and the fine timing and an initial frequency count value of the ring oscillator when the calibration is started;
the delay chain is used for generating a corresponding target fine count when a signal to be tested is received and recording the target fine count into the corresponding table;
the ring oscillator is used for generating a corresponding frequency signal under the influence of the temperature of the delay chain and inputting the frequency signal to the frequency counter;
the frequency counter is used for counting the frequency signals to obtain a test frequency count value, and updating the target fine count in the corresponding table based on the test frequency count value and the initial frequency count value.
2. The converter of claim 1, wherein the delay chain comprises a plurality of carry multiplexers connected in series.
3. The converter of claim 1, wherein the ring oscillator comprises an odd number of sequentially cascaded carry multiplexers, wherein a first carry multiplexer is connected to a last carry multiplexer.
4. The converter of claim 1, wherein the frequency counter is to: and counting the number of rising edges of the ring oscillator in the period of the reference clock based on the received frequency signal and a preset reference clock to obtain the test frequency count value.
5. The converter of claim 4, wherein the reference clock period ranges from 214-216。
6. The converter of claim 1, wherein the frequency counter comprises a system clock, a state machine, and a D flip-flop, the system clock being connected to the state machine and the D flip-flop, respectively.
7. The converter of claim 6, wherein the accuracy of the system clock is 80-100 ppm.
8. A time-to-digital converter calibration method applied to the time-to-digital converter according to any one of claims 1 to 7, the calibration method comprising:
acquiring an initial frequency count value of the ring oscillator and a test frequency count value obtained by a frequency counter;
updating a target fine count based on the initial frequency count value and a test frequency count value;
and searching the corresponding target detail count in the corresponding table based on the updated target detail count.
9. The method of claim 8, wherein updating a target fine count based on the initial frequency count value and a test frequency count value comprises:
obtaining a temperature adjustment coefficient based on the ratio of the initial frequency count value to the test frequency count value;
and adjusting the target fine count by using the temperature adjustment coefficient to obtain an updated target fine count.
10. A field programmable gate array chip comprising a controller and the time-to-digital converter of any one of claims 1-7, the controller being coupled to the time-to-digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111190409.0A CN113900369A (en) | 2021-10-13 | 2021-10-13 | Time-to-digital converter, calibration method and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111190409.0A CN113900369A (en) | 2021-10-13 | 2021-10-13 | Time-to-digital converter, calibration method and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113900369A true CN113900369A (en) | 2022-01-07 |
Family
ID=79191660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111190409.0A Pending CN113900369A (en) | 2021-10-13 | 2021-10-13 | Time-to-digital converter, calibration method and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113900369A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114967410A (en) * | 2022-06-16 | 2022-08-30 | 陕西科技大学 | Digital time conversion device and method |
| CN115145139A (en) * | 2022-07-13 | 2022-10-04 | 合肥工业大学 | High-precision time-to-digital converter and conversion method thereof |
| CN116015284A (en) * | 2022-12-31 | 2023-04-25 | 成都电科星拓科技有限公司 | Method and device for obtaining TDC delay stepping based on reference clock period |
| CN116009376A (en) * | 2022-09-29 | 2023-04-25 | 深圳越登智能技术有限公司 | Carry chain timing calibration method, device, equipment and storage medium |
| CN116932441A (en) * | 2023-07-06 | 2023-10-24 | 无锡芯光互连技术研究院有限公司 | Parallel interface and delay calibration method capable of reducing delay calibration complexity |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100260242A1 (en) * | 2008-03-04 | 2010-10-14 | Katsuaki Abe | Time digital converter, digital pll frequency synthesizer, transceiver, and receiver |
| CN103633975A (en) * | 2012-08-20 | 2014-03-12 | 特克特朗尼克公司 | Ring oscillator timer circuit |
| CN110703583A (en) * | 2019-11-08 | 2020-01-17 | 中国科学院光电技术研究所 | Multi-channel high-precision wide-range time-to-digital converter based on SOC (system on chip) |
| CN112578661A (en) * | 2020-12-11 | 2021-03-30 | 天津大学 | Delay line calibration circuit for FPGA type time-to-digital converter |
-
2021
- 2021-10-13 CN CN202111190409.0A patent/CN113900369A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100260242A1 (en) * | 2008-03-04 | 2010-10-14 | Katsuaki Abe | Time digital converter, digital pll frequency synthesizer, transceiver, and receiver |
| CN103633975A (en) * | 2012-08-20 | 2014-03-12 | 特克特朗尼克公司 | Ring oscillator timer circuit |
| CN110703583A (en) * | 2019-11-08 | 2020-01-17 | 中国科学院光电技术研究所 | Multi-channel high-precision wide-range time-to-digital converter based on SOC (system on chip) |
| CN112578661A (en) * | 2020-12-11 | 2021-03-30 | 天津大学 | Delay line calibration circuit for FPGA type time-to-digital converter |
Non-Patent Citations (4)
| Title |
|---|
| 张孟翟: "多通道大量程高精度事件计时器关键技术研究" * |
| 张孟翟: "多通道大量程高精度事件计时器关键技术研究", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》 * |
| 张孟翟等: "基于FPGA的8通道高精度TDC技术", 《激光与光电子学进展》 * |
| 罗鸣等: "基于FPGA的高精度时间间隔测量技术研究", 《光学与光电技术》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114967410A (en) * | 2022-06-16 | 2022-08-30 | 陕西科技大学 | Digital time conversion device and method |
| CN114967410B (en) * | 2022-06-16 | 2024-03-08 | 陕西科技大学 | Digital time conversion device and method |
| CN115145139A (en) * | 2022-07-13 | 2022-10-04 | 合肥工业大学 | High-precision time-to-digital converter and conversion method thereof |
| CN115145139B (en) * | 2022-07-13 | 2023-07-18 | 合肥工业大学 | High-precision time-digital converter and conversion method thereof |
| CN116009376A (en) * | 2022-09-29 | 2023-04-25 | 深圳越登智能技术有限公司 | Carry chain timing calibration method, device, equipment and storage medium |
| CN116015284A (en) * | 2022-12-31 | 2023-04-25 | 成都电科星拓科技有限公司 | Method and device for obtaining TDC delay stepping based on reference clock period |
| CN116015284B (en) * | 2022-12-31 | 2024-01-30 | 成都电科星拓科技有限公司 | Method and device for obtaining TDC delay stepping based on reference clock period |
| CN116932441A (en) * | 2023-07-06 | 2023-10-24 | 无锡芯光互连技术研究院有限公司 | Parallel interface and delay calibration method capable of reducing delay calibration complexity |
| CN116932441B (en) * | 2023-07-06 | 2024-02-09 | 无锡芯光互连技术研究院有限公司 | Parallel interface and delay calibration method capable of reducing delay calibration complexity |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113900369A (en) | Time-to-digital converter, calibration method and chip | |
| US7816960B2 (en) | Circuit device and method of measuring clock jitter | |
| US6668346B1 (en) | Digital process monitor | |
| US7746183B2 (en) | Measurement apparatus for improving performance of standard cell library | |
| CN101019035B (en) | Precise time measurement apparatus and method | |
| CN105445569A (en) | On-chip nanosecond power supply noise transient waveform measurement system applicable to high-speed integrated circuit and measurement method thereof | |
| JP2013024853A (en) | Frequency counter | |
| CN108061848A (en) | The measuring method and system of addition carry chain delay based on FPGA | |
| CN110515292A (en) | TDC circuit and measurement method based on way traffic annular carry chain | |
| CN100517515C (en) | Method and system for measurement | |
| US6215345B1 (en) | Semiconductor device for setting delay time | |
| CN102104384A (en) | Differential delay chain unit and time-to-digital converter comprising same | |
| CN102928805A (en) | Multi-meter position instrument for calibrating digital energy meters | |
| CN110047552B (en) | Memory reading speed measuring circuit | |
| JP2013024854A (en) | Distance measuring method and system therefor | |
| US20230003781A1 (en) | Apparatus, method, system and medium for measuring pulse signal width | |
| US6944099B1 (en) | Precise time period measurement | |
| CN1014468B (en) | Frequency and time measurement circuit | |
| CN106647226A (en) | Time digital converter, error correcting device and error correcting method | |
| JP2013024857A (en) | Speed measuring method and system therefor | |
| KR101957412B1 (en) | Built Off Self-Test Circuit Apparatus and Time to Digital Converter with New Vernier Delay Line Design | |
| CN115268247B (en) | High-precision establishment holding time measuring circuit for digital-analog mixing and implementation method thereof | |
| KR100642915B1 (en) | A method for measuring/trimming a reference clock cycle of oscillator and an oscillator thereof | |
| CN114779607B (en) | Time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic equipment | |
| Iqbal et al. | High resolution asynchronous digital event timer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |