CN115145139B - High-precision time-digital converter and conversion method thereof - Google Patents
High-precision time-digital converter and conversion method thereof Download PDFInfo
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- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
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Abstract
The invention discloses a high-precision time-digital converter and a conversion method thereof, wherein the converter comprises: the system comprises a sampling and holding circuit, a fine measuring circuit and a calibration circuit, wherein the sampling and holding circuit collects the state of a gate SIGNAL test_signal to be detected and circularly holds the state of the gate SIGNAL test_signal to be detected in a ring-shaped structure RO 1; the fine measurement circuit quantifies the real device delay time of the gate signal to be measured by using the data selector MUXCY (q) _j, and obtains the number NUM of the data selector MUXCY (q) _j; the calibration circuit is used for mainly calibrating the quantized value NUM in the fine measurement circuit to obtain a final measured value DATA_RAM0[ NUM-1] after the gate signal to be measured is calibrated. The invention can ensure that the resource cost of the time-digital converter is reduced and the measurement precision is further improved, thereby being convenient for simultaneously constructing a large-scale multi-channel parallel detection time-digital converter.
Description
Technical Field
The invention belongs to the field of time domain measurement integrated circuit design, and particularly relates to a high-precision time-digital converter (TDC) and a conversion method thereof.
Background
Time-to-digital conversion (TDC) is widely used in high-tip fields such as integrated circuit tester (ATE), laser ranging, satellite navigation, and quantum communication, and the accuracy and resolution of TDC are closely related to advanced development of these fields. At present, although the picosecond TDC is mainly implemented on an ASIC, the disadvantages of long design period, high price and the like of the ASIC cannot meet the requirement of quickly constructing a TDC measurement system. Therefore, the design method of the time-digital converter based on the FPGA platform is widely used, and the time-digital converter not only can obtain very high precision, but also has the advantages of short development period, low cost, flexible design and the like.
The design method of the time-digital converter generally has the technical schemes of a tap delay line method, a NUTT interpolation method, a vernier delay line method, a multi-chain averaging method and the like. Although the time resolution of some schemes can reach technical indexes better than 10ps, the time resolution of some schemes still has the defects of serious nonlinearity, high resource overhead, low throughput and the like, and is not beneficial to the requirement of constructing a large-scale parallel and instant time-to-digital converter.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and provides a high-precision time-digital converter and a conversion method thereof, so that the measurement precision is further improved while the resource expense of the time-digital converter is reduced and the linearity is improved, thereby being convenient for simultaneously constructing a large-scale multi-channel parallel detection time-digital converter.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the invention relates to a high-precision time-digital converter, which is characterized by comprising: a sample-and-hold circuit, a fine measurement circuit, and a calibration circuit;
the sample hold circuit has a ring structure RO1 composed of two alternative multiplexers MUX0, MUX1, an exclusive OR gate XOR0, a D trigger FDRE0, an inverter INV0, m BUFFERs BUFFER 0-BUFFER (m-1);
the first input end MUX0_I0 of the first alternative multiplexer MUX0 is fixed to be at logic low level, and the second input end MUX0_I1 is connected to the SIGNAL to be tested, KEEP_SIGNAL;
the first input terminal MUX1_I0 of the second one-out-of-two multiplexer MUX1 is connected to the output terminal BUFFER_O [ m-1] of the mth BUFFER BUFFER (m-1 ], and the second input terminal MUX1_I1 thereof is fixed to a logic low level;
the output ends MUX0_O and MUX1_O of the two alternative multiplexers are respectively connected to the first input end XOR0_I1 and the second input end XOR0_I0 of the exclusive OR gate XOR 0;
the output XOR0_o of the exclusive or gate XOR0 is connected to the input buffer_i0 of the first BUFFER 0;
the output end BUFFER_O [ I ] of the ith BUFFER BUFFER (I) is connected to the input end BUFFER_I [ i+1] of the (i+1) th BUFFER BUFFER (i+1), i=0, 1, …, m-1;
The data input port FDRE0_d and the synchronous reset port FDRE0_r of the D flip-flop FDRE0 are both fixed to a logic low level, the clock enable port FDRE0_ce is fixed to a logic high level, the clock input port FDRE0_c is connected to an inv0_o signal, and the inv0_o signal is an output signal of the output signal buffer_o0 of the first BUFFER0 after passing through the inverter INV 0; the data output port FDRE0_Q of the D trigger FDRE0 is respectively connected with the control ends MUX0_ S, MUX1_S of two alternative multiplexers;
the fine measurement circuit is composed of n CARRY-ahead chain structures CARRY4_0-CARRY4_n-1, one-out-of-two multiplexer MUX2, two 4 Xn stage D flip-flop groups D0[ 0]]-D0[4n-1]、D1[0]-D1[4n-1]One inverter INV1, one 3×n-stage inverter group INV2[4k+0 ]]-INV2[4k+3]、INV2[4(k+1)]、INV2[4(k+1)+2]And a b-bit counter "1" counter COUNT, where n is even, k=0, 2, … n-2, b e (log) 2 4n ,log 2 8n ]；
Any j-th CARRY-lookahead chain structure carry4_j consists of four two-input data selectors muxcy0_j-muxcy3_j and four exclusive or gates XOR0_j-XOR3_j, j=0, 1, …, n-1;
the first input MUXCY0_I0_j-MUXCY3_I0_j of the four two-input data selectors MUXCY0_j-MUXCY3_j in the jth CARRY-lookahead chain structure CARRY4_j are all fixed to a logic low level, and the control terminals MUXCY0_S_j-MUXCY3_S_j are all fixed to a logic high level;
The output MUXCY (q) _c0_j of the q-th two-input data selector MUXCY (q) _j in the j-th CARRY-lookahead chain structure carry4_j is connected to the second input MUXCY (q+1) _i1_j of the q+1th two-input data selector MUXCY (q+1) _j, where q=0, 1,2; the output end MUXCY0_C0_j-MUXCY3_C3_j of the four two-input data selector MUXCY0_j-MUXCY3_j forms a continuous four-bit carry output end;
the CARRY output muxcy3_c3_j of the j-th CARRY-forward structure CARRY4_j is connected to the second input muxcy0_i1_j+1 of the first two-input data selector muxcy0_j+1 of the j-th +1-th CARRY-forward structure CARRY4_j, thereby being cascaded into a chain from n CARRY-forward structures CARRY4_0-CARRY 4_n-1;
the first input terminals XOR0_i0_j-XOR3_i0_j of the four exclusive or gates XOR0_j-XOR3_j in the j-th CARRY-lookahead chain structure carry4_j are each fixed to a logic low level, the second input terminals XOR0_i1_j-XOR3_i1_j are connected to the second input terminals muxcy0_i1_j-muxcy3_i1_j of the four two-input data selectors muxcy0_j-muxcy3_j, respectively, and then the output terminals XOR0_j-XOR 3_o3_j of the four exclusive or gates XOR0_j-XOR3_j constitute a continuous four-bit exclusive or output terminal;
the outputs XOR0_O0_k-XOR3_O3_k of the four exclusive OR gates in the kth CARRY-lookahead structure CARRY4_k are connected to the data input of the first D flip-flop D0[4k+0] -D0[4k+3 ]; the outputs muxcy0_c0_k+1, muxcy2_c2_k+1 of the first and third two-input data selectors muxcy4_k+1 of the k+1-th CARRY-look-ahead structure are connected to the data inputs d0_d4 (k+1) ], d0_d4 (k+1) +2 of the first D flip-flop group D0, respectively, the outputs XOR1_o1_k+1, XOR3_o3_k+1 of the second and fourth exclusive or gates XOR3_k+1 are connected to the data inputs d0_d4 (k+1) +1] and d0_d4 (k+1) +3], k=0, 2,4, …, n-2 of the first D flip-flop group, respectively;
The output ends D0_O4 (k+1) +1 and D0_O4 (k+1) +3 of the first D trigger group are directly connected to the data input ends D1_D4 (k+1) +1 and D1_D4 (k+1) +3 of the second D trigger group, the output ends D0_O4k+0-D0_O4k+3, D0_O4 (k+1) +2 are respectively connected to the data input ends INV2_I [4k+0] -INV2_I [4k+3], INV2_I [4 (k+1) +2], and the output ends INV2_O4k+0 ] -2_O4 [ 4+3 ], 2_O4 (k+1) +2] of the inverter group are connected to the data input ends INV2_O4+1, d4+4+1;
the second input terminal muxcy0_i1_0 of the first two-input data selector muxcy0 in the first CARRY-lookahead structure carry4_0 is used as a START signal terminal START to be tested; an input end inv1_i of the inverter INV1 is used as an end signal input port STOP to be detected; the first input end MUX2_I0 of the alternative multiplexer MUX2 is connected to the output end INV1_O of the inverter, and the second input end MUX2_I1 of the alternative multiplexer MUX2 is connected to the system clock end SYS_CLK;
the clock input ends D0_Cj of any jth D trigger D0[ j ] in the first D trigger group are all interconnected and connected to the output port MUX2_O of the alternative multiplexer MUX 2;
The clock input ends D1_Cj of any jth D trigger D1[ j ] in the second D trigger group are all interconnected and connected to the system clock end SYS_CLK;
the calibration circuit consists of an alternative multiplexer MUX3, an M-order ring oscillator RO and a random access memory block RAM0, wherein M is an odd number;
the M-stage ring oscillator consists of a two-input NAND gate NAND0 and M-1 inverters INV3[0] -INV3[ M-2 ];
the first input terminal NAND0_I0 of the two-input NAND gate NAND0 is connected to the output terminal INV3_O [ M-2] of the M-1 th inverter INV3[ M-2], the second input terminal NAND0_I1 is connected to the enable control signal EN, and the output terminal NAND0_O thereof is connected to the input terminal INV3_I0 of the first inverter INV3[ 0];
the output end inv3_o [ N ] of the nth inverter INV3[ N ] is connected to the input end inv3_i [ n+1] of the n+1th inverter INV3[ n+1], n=0, 1, … M-2;
the first input end MUX3_I0 of the alternative multiplexer MUX3 is connected to the output end INV3_O3 of the M-3 rd inverter INV3[ M-3] in the ring oscillator RO, and the second input end MUX3_I1 is connected to the gate SIGNAL to be tested TEST_SIGNAL.
The invention discloses a conversion method based on the high-precision time-digital converter, which is characterized by comprising the following steps of:
Step 1, an initial state;
enabling an enable control signal EN of an M-stage ring oscillator RO in the calibration circuit to be at a logic low level, enabling the ring oscillator RO not to oscillate, and outputting a fixed logic low level by an output end INV3_O3 of an M-2 inverter INV3[ M-3 ]; the control end MUX3_S of the alternative multiplexer MUX3 is in a logic low level, and the alternative multiplexer MUX3 sends an output end MUX3_O to output a logic low level SIGNAL to a SIGNAL end enable_signal to be detected in the sample hold circuit;
the data output end FDRE0_Q of the D trigger FDRE0 in the sample hold circuit outputs logic high level, so that two one-out-of-two multiplexers MUX0 and MUX1 gate the second input end; the output terminal mu0_o of the first one-out-of-two multiplexer MUX0 outputs the keep_signal, and the output terminal mu1_o of the second one-out-of-two multiplexer MUX1 outputs a logic low level, so that the exclusive or gate XOR0 acts as a buffer and its output terminal XOR0_o outputs the input SIGNAL keep_signal of the second input terminal XOR 0_i1; the SIGNAL to be measured (KEEP_SIGNAL) is logic low level, and after passing through a multiplexer MUX0, an exclusive OR gate XOR0 and BUFFERs BUFFER 0-BUFFER (m-1) in turn, the output end BUFFER_O [ m-1] of the (m-1) BUFFER BUFFER (m-1) outputs logic low level to a START SIGNAL end START and an end SIGNAL end STOP in the fine measurement circuit;
The output end MUXCY0_C0_j-MUXCY3_C3_j of four two-input data selectors MUXCY0_j-MUXCY3_j in any jth CARRY-ahead chain structure CARRY4_j in the fine measurement circuit outputs a logic low level;
the output ends XOR0_O0_j-XOR3_O3_j of four XOR gates XOR0_j-XOR3_j in any jth CARRY-forward chain structure CARRY4_j in the fine measurement circuit output logic high level, j=0, 1 … and n-1;
the partial D flip-flops D0[4k+0] -D0[4k+3], D0[4 (k+1) ] and D0[4 (k+1) +2] in the first D flip-flop group D0[0] -D0[4n-1] each output a logic high level from the output terminals D0_O4k+0 ] -D0_O4k+3 ], D0_O4 (k+1) +2, k=0, 2, …, n-2;
the outputs D1_O0-D1_O4n-1 of the second D flip-flop group D1[0] -D1[4n-1] all output logic low level, and the counter value of "1" is 0;
step 2, working states, including a calibration mode and a measurement mode:
step 2a, in the calibration mode:
2a.1, setting an enable control SIGNAL EN of an M-stage ring oscillator RO in the calibration circuit to be at a logic high level, starting oscillation of the ring oscillator RO, setting a control end MUX3_S of an alternative multiplexer MUX3 to be at a logic low level, and outputting a SIGNAL to be detected INV3_O [ M-3] to a SIGNAL to be detected end KEEP_SIGNAL in the sampling circuit by an output end MUX3_O;
2a.2. If the SIGNAL keep_signal to be detected in the sample-hold circuit completely enters the ring structure RO1, the output end buffer_o0 of the BUFFER0 generates a falling edge jump and inputs the falling edge jump to the inverter INV0, and after the output end INV0_o of the inverter INV0 outputs a rising edge jump SIGNAL and triggers the output end FDRE0_o of the D flip-flop FDRE0 to jump to a logic low level, so that the two alternative multiplexers MUX0 and MUX1 both gate the first input end; the output terminal mu0_o of the first one-out-of-two multiplexer MUX0 outputs a logic low level, and the output terminal mu1_o of the second one-out-of-two multiplexer MUX1 outputs the output signal buffer_o [0] of the m-1 st BUFFER (m-1), so that the exclusive or gate XOR0 functions as a BUFFER and its output terminal XOR0_o outputs the input signal buffer_o [0] of the first input terminal XOR 0_i0; in the process that the SIGNAL to be detected KEEP_SIGNAL is always circulated and propagated in the annular structure RO1, the sampling hold circuit outputs the SIGNAL to be detected KEEP_SIGNAL to a START SIGNAL end and an end SIGNAL end STOP in the fine measuring circuit through an output end BUFFER_O [ m-1] of an m-1 BUFFER BUFFER (m-1);
2a.3, setting the control end MUX2_S of the alternative multiplexer MUX2 in the fine measurement circuit to be at a logic high level;
When the rising edge of the SIGNAL to be detected keep_signal arrives, the logic high level of the SIGNAL to be detected keep_signal propagates in the CARRY-ahead structure CARRY4_0-CARRY4_n-1 through the START SIGNAL end START;
when the rising edge of the system clock sys_clk signal arrives, the first set of D flip-flops D0 propagate the START signal START to the state of the p-th two-input data selector MUXCY (p) _j in the j-th CARRY-look ahead chain structure carry4_j for latching, p=0, 1,2,3; on arrival of the rising edge of the next system clock sys_clk signal, the outputs d1_o [0] -d1_o [4j+p ] of the partial D flip-flops D1[0] -D1[4j+p ] in the second D flip-flop group D1[0] -D1[4n-1] output a logic high level, so that the output value num=4×j+p, j=0, 1..;
measuring the device delay time of four two-input data selectors MUXCY0-MUXCY3 in n CARRY-ahead structures CARRY4 and writing the device delay time into a random access memory block RAM0 in sequence, so that 4×n device delay data are written into 4×n addresses in total; then, summing the data of the ith and (i-1) th addresses in the random access memory block RAM0 and writing the data into the current ith address, and obtaining a calibration data storage table DATE_RAM0, wherein i=0, 1,2, n-1;
Step 2b, in the measurement mode:
2b.1, setting the enable control SIGNAL EN of the M-stage ring oscillator RO in the calibration circuit to be logic low level, setting the control end MUX3_S of the alternative multiplexer MUX3 to be logic high level, and outputting the gate SIGNAL TEST_SIGNAL to be tested by the output end MUX3_O;
step 2b.2. Is performed according to step 2a.2 in calibration mode;
2b.3, setting the control end MUX2_S of the alternative multiplexer MUX2 in the fine measurement circuit to be at a logic low level;
obtaining an output value NUM of a counter COUNT of a q-bit meter '1' according to the process of the step 2 a.3;
2b.4, taking the calibration data storage table DATE_RAM0 as a reference object, finding the value DATE_RAM0[ NUM-1] of the NUM-1 address, and taking the value DATE_RAM0 as a group of calibrated measurement results;
step 2b.5. Repeat step 2 b.1-step 2b.4 in the measurement mode, thus get the measurement result after the multiunit calibration, and take the average value as the final measurement result of the gate SIGNAL test_signal to be measured.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention introduces a sample hold circuit on a field programmable gate array platform for the first time, wherein the sample hold circuit fully utilizes one input end of the exclusive or gate XOR0 to be fixed at a logic low level, so that the exclusive or gate XOR0 serves as a buffer; when the signal to be detected does not arrive, the signal input into the sample hold circuit is an invalid signal; when the signal to be detected completely enters, the signal input into the sample hold circuit is circularly held in the annular structure RO 1; the defect that a plurality of channels are needed to serve one gate signal to be tested for improving the precision in the past is overcome, and the resource utilization rate is improved.
2. The sample hold circuit overcomes the defect that a signal to be measured can only be measured once through a single measurement channel in the past, and the conversion precision of the time-digital converter can be effectively improved through multiple measurements.
3. According to the invention, the fine measurement circuit does not adopt a traditional four-bit CARRY output CCCC mode, but adopts a four-bit exclusive-or and CARRY output cross-combined SSSS plus SCSC mode, so that the existence of the delay time of an ultra-wide device can be removed, the device delay time of a data selector MUXCY (q) _j in a CARRY-ahead structure CARRY4_0-CARRY4_n-1 is more uniform, and the defect of serious nonlinearity of a time-digital converter is overcome.
4. The three main measuring circuits in the invention all adopt a pipeline working mode, and the system throughput is improved by reducing the dead time of the time-digital converter.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a sample-and-hold circuit diagram of the present invention;
FIG. 3 is a diagram of a fine measurement circuit of the present invention;
FIG. 4 is a diagram of a calibration circuit according to the present invention.
Detailed Description
In this embodiment, as shown in fig. 1, a high-precision time-to-digital converter includes:
the sampling and holding circuit is used for sampling the gate SIGNAL to be measured, can sample and store the state of the gate SIGNAL to be measured in the annular structure RO1, and then the fine measuring circuit measures the gate SIGNAL to be measured for a plurality of times;
The fine measurement circuit is used for carrying out quantitative measurement on the gate signal to be measured, and the circuit uses a data selector MUXCY (q) _j in a carry-ahead structure as a delay unit to count the number of the data selector MUXCY (q) _j of which the logic high level is transmitted in the time interval of the gate signal to be measured to obtain a measured value NUM;
the calibration circuit is used for calibrating the measured value NUM in the fine measurement circuit, and the circuit obtains the real device delay time of the DATA selector MUXCY in the CARRY-ahead structure CARRY4_0-CARRY4_4n-1 and generates a calibration memory table DATA_RAM0 by using a code density measurement method;
as shown in fig. 2, the sample-and-hold circuit has a ring structure RO1 composed of two alternative multiplexers MUX0, MUX1, an exclusive or gate XOR0, a D flip-flop FDRE0, an inverter INV0, and m BUFFERs BUFFER0 to BUFFER (m-1);
the first input end MUX0_I0 of the first alternative multiplexer MUX0 is fixed to be at logic low level, and the second input end MUX0_I1 is connected to the SIGNAL to be tested, KEEP_SIGNAL;
the first input terminal MUX1_I0 of the second one-out-of-two multiplexer MUX1 is connected to the output terminal BUFFER_O [ m-1] of the mth BUFFER BUFFER (m-1 ], and the second input terminal MUX1_I1 thereof is fixed to a logic low level;
The output ends MUX0_O and MUX1_O of the two alternative multiplexers are respectively connected to a first input end XOR0_I1 and a second input end XOR0_I0 of the exclusive OR gate XOR 0;
the output XOR0_o of the exclusive or gate XOR0 is connected to the input buffer_i [0] of the first BUFFER 0;
the output end BUFFER_O [ I ] of the ith BUFFER BUFFER (I) is connected to the input end BUFFER_I [ i+1] of the (i+1) th BUFFER BUFFER (i+1), i=0, 1, …, m-1;
the number m of the BUFFER BUFFER (i) is related to the real device delay time of the BUFFER BUFFER (i) and the gate SIGNAL test_signal to be tested; for example, let the time of the gate signal to be tested be T, the device delay time of the BUFFER BUFFER (i) be τ, and the device delay time of the alternative multiplexer MUX1 be τ 1 The value of the buffer number m is (T- τ) 1 )/(τ)；
The data input port FDRE0_D and the synchronous reset port FDRE0_R of the D trigger FDRE0 are both fixed to be at a logic low level, the clock enable port FDRE0_CE is fixed to be at a logic high level, the clock input port FDRE0_C is connected with an INV0_O signal, and the INV0_O signal is an output signal of an output signal BUFFER_O0 of the first BUFFER BUFFER0 after passing through an inverter INV0; the data output port FDRE0_Q of the D trigger FDRE0 is respectively connected with the control ends MUX0_ S, MUX1_S of the two alternative multiplexers;
When the gate SIGNAL test_signal to be detected does not arrive, the SIGNAL input by the second input end MUX0_I1 of the alternative multiplexer MUX0 is an invalid SIGNAL, and the ring structure RO1 is in an inactive state; after the gate SIGNAL test_signal to be detected completely enters the sample hold circuit, the input SIGNAL of the first input end MUX1_I0 of the alternative multiplexer MUX1 is the gate SIGNAL test_signal to be detected, the annular structure RO1 is in a working state, and the state of the gate SIGNAL test_signal to be detected is held;
as shown in FIG. 3, the fine measurement circuit is composed of n CARRY-lookahead chain structures CARRY4_0-CARRY4_n-1, one-out-of-two multiplexer MUX2, two 4 Xn stage D flip-flop groups D0[0 ]]-D0[4n-1]、D1[0]-D1[4n-1]One inverter INV1, one 3×n-stage inverter group INV2[4k+0 ]]-INV2[4k+3]、INV2[4(k+1)]、INV2[4(k+1)+2]And a b-bit counter "1" counter COUNT, where n is even, k=0, 2, … n-2, b e (log) 2 4n ,log 2 8n ]；
Any j-th CARRY-lookahead chain structure carry4_j consists of four two-input data selectors muxcy0_j-muxcy3_j and four exclusive or gates XOR0_j-XOR3_j, j=0, 1, …, n-1;
the first input MUXCY0_I0_j-MUXCY3_I0_j of the four two-input data selectors MUXCY0_j-MUXCY3_j in the jth CARRY-lookahead chain structure CARRY4_j are all fixed to a logic low level, and the control terminals MUXCY0_S_j-MUXCY3_S_j are all fixed to a logic high level;
The output MUXCY (q) _c0_j of the q-th two-input data selector MUXCY (q) _j in the j-th CARRY-lookahead chain structure carry4_j is connected to the second input MUXCY (q+1) _i1_j of the q+1th two-input data selector MUXCY (q+1) _j, where q=0, 1,2; the output end MUXCY0_C0_j-MUXCY3_C3_j of the four two-input data selector MUXCY0_j-MUXCY3_j forms a continuous four-bit carry output end; since the CARRY terminal of the data selector MUXCY (q) _j outputs a logic low level after the fine measurement circuit initializes the CARRY-ahead structure CARRY4_0-CARRY4_n-1, the CARRY terminal of the data selector MUXCY (q) _j through which the rising edge propagates outputs a logic high level when the rising edge of the gate SIGNAL test_signal to be measured arrives and propagates along the CARRY-ahead structure CARRY4_0-CARRY 4_n-1;
the CARRY output muxcy3_c3_j of the j-th CARRY-forward structure CARRY4_j is connected to the second input muxcy0_i1_j+1 of the first two-input data selector muxcy0_j+1 of the j-th +1-th CARRY-forward structure CARRY4_j, thereby being cascaded into a chain from n CARRY-forward structures CARRY4_0-CARRY 4_n-1;
the first input terminals XOR0_i0_j-XOR3_i0_j of the four exclusive or gates XOR0_j-XOR3_j in the j-th CARRY-lookahead chain structure carry4_j are each fixed to a logic high level, the second input terminals XOR0_i1_j-XOR3_i1_j are connected to the second input terminals muxcy0_i1_j-muxcy3_i1_j of the four two-input data selectors muxcy0_j-muxcy3_j, respectively, and then the output terminals XOR0_j-XOR 3_o3_j of the four exclusive or gates XOR0_j-XOR3_j constitute a continuous four-bit exclusive or output terminal; since the first input terminal of the exclusive or gate XOR0_j-XOR3_j in the CARRY-ahead structure CARRY4_0-CARRY4_n-1 is at the logic high level after the initialization of the fine measurement circuit, the second input terminal of the data selector MUXCY (q) _j is at the logic low level, and the output terminal XOR0_o0_j-XOR3_o3_j of the exclusive or gate XOR0_j-XOR3_j outputs the logic high level; when the rising edge of the gate SIGNAL to be tested comes and propagates along the CARRY-ahead structure CARRY4_0-CARRY4_n-1, the CARRY end of the data selector MUXCY (q) _j propagating through the rising edge outputs a logic high level, and the output end XOR0_O0_j-XOR3_O3_j of the exclusive OR gate XOR0_j-XOR3_j outputs a logic low level;
The outputs XOR0_O0_k-XOR3_O3_k of the four exclusive OR gates in the kth CARRY-lookahead structure CARRY4_k are connected to the data input of the first D flip-flop D0[4k+0] -D0[4k+3 ]; the outputs muxcy0_c0_k+1, muxcy2_c2_k+1 of the first and third two-input data selectors muxcy4_k+1 of the k+1-th CARRY-look-ahead structure are connected to the data inputs d0_d4 (k+1) ], d0_d4 (k+1) +2 of the first D flip-flop group D0, respectively, the outputs XOR1_o1_k+1, XOR3_o3_k+1 of the second and fourth exclusive or gates XOR3_k+1 are connected to the data inputs d0_d4 (k+1) +1] and d0_d4 (k+1) +3], k=0, 2,4, …, n-2 of the first D flip-flop group, respectively;
the output ends D0_O4 (k+1) +1 and D0_O4 (k+1) +3 of the first D trigger group are directly connected to the data input ends D1_D4 (k+1) +1 and D1_D4 (k+1) +3 of the second D trigger group, the output ends D0_O4k+0-D0_O4k+3 of the first D trigger group, D0_O4 (k+1) +2] are respectively connected to the data input ends INV2_I [4k+0] -INV2_I [4k+3], INV2_I [4 (k+1) ], 2_I [4 (k+2 ], and the output ends INV2_O4k+0 ] -2_O4k+3, 2_O4 (k+1) +2] of the inverter group are connected to the data input ends INV2_O4k+1+4;
The second input end muxcy0_i1_0 of the first two-input data selector muxcy0 in the first CARRY-lookahead structure carry4_0 is used as a START signal end START to be tested; an input end inv1_i of the inverter INV1 is used as an end signal input port STOP to be detected; the first input end MUX2_I0 of the alternative multiplexer MUX2 is connected to the output end INV1_O of the inverter, and the second input end MUX2_I1 of the alternative multiplexer MUX2 is connected to the system clock end SYS_CLK; the end SIGNAL end STOP and the system clock end SYS_CLK are latch SIGNALs of the first D trigger D0[0] -D0[4n-1], and as the end SIGNAL end STOP is connected with a gate SIGNAL TEST_SIGNAL to be detected taking a falling edge as the end SIGNAL, an inverter INV1 is needed to be connected, and the falling edge SIGNAL is changed into a rising edge SIGNAL to trigger the first D trigger D0[0] -D0[4n-1] to latch the CARRY and the output state of the exclusive OR end in the CARRY look-ahead structure CARRY4_0-CARRY4_n-1;
the clock input ends D0_Cj of any jth D trigger D0[ j ] in the first D trigger group are all interconnected and connected to the output port MUX2_O of the alternative multiplexer MUX 2;
the clock input ends D1_Cj of any jth D trigger D1[ j ] in the second D trigger group are all interconnected and connected to the system clock end SYS_CLK;
As shown in fig. 4, the calibration circuit is composed of an alternative multiplexer MUX3, an M-stage ring oscillator RO and a random access memory block RAM0, where M is an odd number;
the M-stage ring oscillator consists of a two-input NAND gate NAND0 and M-1 inverters INV3[0] -INV3[ M-2 ];
the first input terminal NAND0_I0 of the two-input NAND gate NAND0 is connected to the output terminal INV3_O [ M-2] of the M-1 th inverter INV3[ M-2], the second input terminal NAND0_I1 is connected to the enable control signal EN, and the output terminal NAND0_O thereof is connected to the input terminal INV3_I0 of the first inverter INV3[ 0];
NAND gate NAND0 can also act as an inverter in ring oscillator RO in addition to controlling ring oscillator RO to start oscillation through its second input EN;
the output end inv3_o [ N ] of the nth inverter INV3[ N ] is connected to the input end inv3_i [ n+1] of the n+1th inverter INV3[ n+1], n=0, 1, … M-2;
the first input end MUX3_I0 of the alternative multiplexer MUX3 is connected to the output end INV3_O [ M-3] of the M-3 rd inverter INV3[ M-3] in the ring oscillator RO, and the second input end MUX3_I1 is connected to the gate SIGNAL to be tested. In the calibration mode, the MUX3 gates a first input end, and an output end MUX3_O thereof connects a periodic pulse signal generated by the ring oscillator RO into the fine measurement circuit; in the measurement mode, the MUX3 gates the second input end, and the output end MUX3_O thereof connects the gate SIGNAL to be measured TEST_SIGNAL to the fine measurement circuit;
2. A conversion method based on the high-precision time-to-digital converter of claim 1, characterized by the steps of:
step 1, an initial state;
enabling an enable control signal EN of an M-stage ring oscillator RO in the calibration circuit to be at a logic low level, enabling the ring oscillator RO not to oscillate, and outputting a fixed logic low level by an output end INV3_O3 of an M-2 inverter INV3[ M-3 ]; the control end MUX3_S of the alternative multiplexer MUX3 is in a logic low level, and the alternative multiplexer MUX3 sends an output end MUX3_O to output a logic low level SIGNAL to a SIGNAL end enable_signal to be detected in the sample hold circuit;
the calibration signal is a square wave pulse signal with the periodicity of t, which is generated by an M-order ring oscillator RO, and is transmitted into the sample hold circuit through a first input end MUX3_I0 and an output end MUX3_O of the MUX 3; let the true device delay time of NAND gate NAND0 be τ 2 Inverter INV3[ j ]]Is tau 3 The value of the pulse period t generated by the M-stage ring oscillator RO is 1/(2× (τ) 2 +(M-1)τ 3 ))；
The data output end FDRE0_Q of the D trigger FDRE0 in the sample hold circuit outputs logic high level, so that the two one-out-of-two multiplexers MUX0 and MUX1 gate the second input end; the output terminal mu0_o of the first one-out-of-two multiplexer MUX0 outputs the keep_signal, and the output terminal mu1_o of the second one-out-of-two multiplexer MUX1 outputs a logic low level, so that the exclusive or gate XOR0 acts as a buffer and its output terminal XOR0_o outputs the input SIGNAL keep_signal of the second input terminal XOR 0_i1; the SIGNAL to be measured (KEEP_SIGNAL) is a logic low level, and after passing through the alternative multiplexer MUX0, the exclusive OR gate XOR0 and the BUFFERs BUFFER 0-BUFFER (m-1) in turn, the output end BUFFER_O [ m-1] of the (m-1) BUFFER BUFFER (m-1) outputs the logic low level to the START SIGNAL end START and the end SIGNAL end STOP in the fine measurement circuit;
The output end MUXCY0_C0_j-MUXCY3_C3_j of four two-input data selectors MUXCY0_j-MUXCY3_j in any j-th CARRY-lead chain structure CARRY4_j in the fine measurement circuit outputs a logic low level;
the output ends XOR0_O0_j-XOR3_O3_j of the four exclusive OR gates XOR0_j-XOR3_j in any jth CARRY-lookahead chain structure CARRY4_j in the fine measurement circuit output logic high level, j=0, 1 …, n-1;
the partial D flip-flops D0[4k+0] -D0[4k+3], D0[4 (k+1) ] and D0[4 (k+1) +2] in the first D flip-flop group D0[0] -D0[4n-1] each output a logic high level from the output terminals D0_O4k+0 ] -D0_O4k+3 ], D0_O4 (k+1) +2, k=0, 2, …, n-2; the logic high level output by D0[4k+0] -D0[4k+3], D0[4 (k+1) ] and D0[4 (k+1) +2] through the inverter groups INV2[4k+0] -INV2[4k+3], INV2[4 (k+1) ], and INV2[4 (k+1) +2] becomes logic low level after the logic high level output by D0[4k+0] -D0[4k+3], D0[4 (k+1) ] and D0[4 (k+1) +2] passes through the inverter groups INV2[4k+0] -INV2[4k+3], INV2[4 (k+1) ];
the outputs D1_O0-D1_O4n-1 of the second D flip-flop group D1[0] -D1[4n-1] all output logic low level, and the counter value of "1" is 0;
step 2, working states, including a calibration mode and a measurement mode:
step 2a, under the calibration mode:
2a.1, setting an enable control SIGNAL EN of an M-stage ring oscillator RO in a calibration circuit to be a logic high level, starting oscillation of the ring oscillator RO, setting a control end MUX3_S of an alternative multiplexer MUX3 to be a logic low level, and outputting a SIGNAL to be detected INV3_O [ M-3] to a SIGNAL to be detected end KEEP_SIGNAL in a sampling circuit by an output end MUX3_O;
2a.2. If the SIGNAL to be tested keep_signal in the sample hold circuit completely enters the ring structure RO1, the output end buffer_o0 of the BUFFER0 generates a falling edge jump and inputs the falling edge jump to the inverter INV0, and after the output end INV0_o of the inverter INV0 outputs a rising edge jump SIGNAL and triggers the output end FDRE0_o of the D trigger FDRE0 to jump to logic low level, so that the two alternative multiplexers MUX0 and MUX1 gate the first input end; the output terminal mu0_o of the first one-out-of-two multiplexer MUX0 outputs a logic low level, and the output terminal mu1_o of the second one-out-of-two multiplexer MUX1 outputs the output signal buffer_o [0] of the m-1 st BUFFER (m-1), so that the exclusive or gate XOR0 functions as a BUFFER and its output terminal XOR0_o outputs the input signal buffer_o [0] of the first input terminal XOR 0_i0; in the process that the SIGNAL to be detected KEEP_SIGNAL is always circulated and propagated in the annular structure RO1, the sample hold circuit outputs the SIGNAL to be detected KEEP_SIGNAL to a START SIGNAL end and an end SIGNAL end STOP in the fine measuring circuit through an output end BUFFER_O [ m-1] of an m-1 BUFFER BUFFER (m-1);
2a.3, setting the control end MUX2_S of the alternative multiplexer MUX2 in the fine measurement circuit to be logic high level; the second input end MUX2_I1 is gated by the alternative multiplexer MUX2, and when the rising edge signal of the system clock SYS_CLK arrives, the first D trigger group D0[0] -D0[4n-1] is triggered to latch a logic high level signal propagated in the CARRY-look-ahead structure CARRY4_0-CARRY4_n-1;
When the rising edge of the SIGNAL to be detected keep_signal arrives, the logic high level of the SIGNAL to be detected keep_signal propagates in the CARRY-ahead structure CARRY4_0-CARRY4_n-1 through the START SIGNAL end START;
when the rising edge of the system clock sys_clk signal arrives, the first set of D flip-flops D0 propagate the START signal START to the state of the p-th two-input data selector MUXCY (p) _j in the j-th CARRY-look ahead chain structure carry4_j for latching, p=0, 1,2,3; on arrival of the rising edge of the next system clock sys_clk signal, the outputs d1_o [0] -d1_o [4j+p ] of the partial D flip-flops D1[0] -D1[4j+p ] in the second D flip-flop group D1[0] -D1[4n-1] output a logic high level, so that the output value num=4×j+p, j=0, 1..; since the second set of D flip-flops D1[0] -D1[4n-1] output is a thermometer code, and cumulatively summed with a meter "1" counter; for example, taking an 8-bit thermometer code as example 1110_0000, the counter "1" counter COUNT value is 3, indicating that the calibration signal has passed through 3 data selectors muxcy0_0-muxcy2_0; w times of measurement are carried out on a CARRY-ahead structure CARRY4_0-CARRY4_n-1 in a fine measurement circuit, and the real device delay time of the (q+4j) th data selector MUXCY (q) _j is (W/W) multiplied by T_clk by a mathematical statistics method under the assumption that the number of thermometer code 1 to 0 hops on the (q+4j) th data selector MUXCY (q) _j is W;
Measuring the device delay time of four two-input data selectors MUXCY0-MUXCY3 in n CARRY-ahead structures CARRY4 and writing the device delay time into a random access memory block RAM0 in sequence, so that 4×n device delay data are written into 4×n addresses in total; then, summing the data of the ith and (i-1) th addresses in the random access memory block RAM0 and writing the data into the current ith address, and obtaining a calibration data storage table DATE_RAM0, wherein i=0, 1,2, n-1;
step 2b. Under the measurement mode:
in the step 2b.1. In the calibration circuit, the enable control SIGNAL EN of the M-stage ring oscillator RO is set to be at a logic low level, the control end MUX3_S of the alternative multiplexer MUX3 is set to be at a logic high level, and the output end MUX3_O of the alternative multiplexer MUX3 outputs a gate SIGNAL to be tested;
step 2b.2. Is performed according to step 2a.2 in calibration mode;
step 2b.3. The control terminal MUX2_S of the alternative multiplexer MUX2 in the fine measurement circuit is set to logic low level;
obtaining an output value NUM of a counter COUNT of a q-bit meter '1' according to the process of the step 2 a.3;
2b.4, taking the calibration data storage table DATE_RAM0 as a reference object, finding the value DATE_RAM0[ NUM-1] of the NUM-1 address, and taking the value DATE_RAM0[ NUM-1] as a group of calibrated measurement results;
Step 2b.5. Repeat step 2 b.1-step 2b.4 in the measurement mode, thus get the measurement result after the multiunit calibration, and take the average value as the final measurement result of the gate SIGNAL test_signal to be measured.
Claims (2)
1. A high precision time to digital converter, comprising: a sample-and-hold circuit, a fine measurement circuit, and a calibration circuit;
the sample hold circuit has a ring structure RO1 composed of two alternative multiplexers MUX0, MUX1, an exclusive OR gate XOR0, a D trigger FDRE0, an inverter INV0, m BUFFERs BUFFER 0-BUFFER (m-1);
the first input end MUX0_I0 of the first alternative multiplexer MUX0 is fixed to be at logic low level, and the second input end MUX0_I1 is connected to the SIGNAL to be tested, KEEP_SIGNAL;
the first input terminal MUX1_I0 of the second one-out-of-two multiplexer MUX1 is connected to the output terminal BUFFER_O [ m-1] of the mth BUFFER BUFFER (m-1 ], and the second input terminal MUX1_I1 thereof is fixed to a logic low level;
the output ends MUX0_O and MUX1_O of the two alternative multiplexers are respectively connected to the first input end XOR0_I1 and the second input end XOR0_I0 of the exclusive OR gate XOR 0;
the output XOR0_o of the exclusive or gate XOR0 is connected to the input buffer_i0 of the first BUFFER 0;
The output end BUFFER_O [ I ] of the ith BUFFER BUFFER (I) is connected to the input end BUFFER_I [ i+1] of the (i+1) th BUFFER BUFFER (i+1), i=0, 1, …, m-1;
the data input port FDRE0_d and the synchronous reset port FDRE0_r of the D flip-flop FDRE0 are both fixed to a logic low level, the clock enable port FDRE0_ce is fixed to a logic high level, the clock input port FDRE0_c is connected to an inv0_o signal, and the inv0_o signal is an output signal of the output signal buffer_o0 of the first BUFFER0 after passing through the inverter INV 0; the data output port FDRE0_Q of the D trigger FDRE0 is respectively connected with the control ends MUX0_ S, MUX1_S of two alternative multiplexers;
the fine measurement circuit is composed of n CARRY-ahead chain structures CARRY4_0-CARRY4_n-1, one-out-of-two multiplexer MUX2, two 4 Xn stage D flip-flop groups D0[ 0]]-D0[4n-1]、D1[0]-D1[4n-1]One inverter INV1, one 3×n-stage inverter group INV2[4k+0 ]]-INV2[4k+3]、INV2[4(k+1)]、INV2[4(k+1)+2]And a b-bit counter "1" counter COUNT, where n is even, k=0, 2, … n-2, b e (log) 2 4n ,log 2 8n ]；
Any j-th CARRY-lookahead chain structure carry4_j consists of four two-input data selectors muxcy0_j-muxcy3_j and four exclusive or gates XOR0_j-XOR3_j, j=0, 1, …, n-1;
The first input MUXCY0_I0_j-MUXCY3_I0_j of the four two-input data selectors MUXCY0_j-MUXCY3_j in the jth CARRY-lookahead chain structure CARRY4_j are all fixed to a logic low level, and the control terminals MUXCY0_S_j-MUXCY3_S_j are all fixed to a logic high level;
the output MUXCY (q) _c0_j of the q-th two-input data selector MUXCY (q) _j in the j-th CARRY-lookahead chain structure carry4_j is connected to the second input MUXCY (q+1) _i1_j of the q+1th two-input data selector MUXCY (q+1) _j, where q=0, 1,2; the output end MUXCY0_C0_j-MUXCY3_C3_j of the four two-input data selector MUXCY0_j-MUXCY3_j forms a continuous four-bit carry output end;
the CARRY output muxcy3_c3_j of the j-th CARRY-forward structure CARRY4_j is connected to the second input muxcy0_i1_j+1 of the first two-input data selector muxcy0_j+1 of the j-th +1-th CARRY-forward structure CARRY4_j, thereby being cascaded into a chain from n CARRY-forward structures CARRY4_0-CARRY 4_n-1;
the first input terminals XOR0_i0_j-XOR3_i0_j of the four exclusive or gates XOR0_j-XOR3_j in the j-th CARRY-lookahead chain structure carry4_j are each fixed to a logic low level, the second input terminals XOR0_i1_j-XOR3_i1_j are connected to the second input terminals muxcy0_i1_j-muxcy3_i1_j of the four two-input data selectors muxcy0_j-muxcy3_j, respectively, and then the output terminals XOR0_j-XOR 3_o3_j of the four exclusive or gates XOR0_j-XOR3_j constitute a continuous four-bit exclusive or output terminal;
The outputs XOR0_O0_k-XOR3_O3_k of the four exclusive OR gates in the kth CARRY-lookahead structure CARRY4_k are connected to the data input of the first D flip-flop D0[4k+0] -D0[4k+3 ]; the outputs muxcy0_c0_k+1, muxcy2_c2_k+1 of the first and third two-input data selectors muxcy4_k+1 of the k+1-th CARRY-look-ahead structure are connected to the data inputs d0_d4 (k+1) ], d0_d4 (k+1) +2 of the first D flip-flop group D0, respectively, the outputs XOR1_o1_k+1, XOR3_o3_k+1 of the second and fourth exclusive or gates XOR3_k+1 are connected to the data inputs d0_d4 (k+1) +1] and d0_d4 (k+1) +3], k=0, 2,4, …, n-2 of the first D flip-flop group, respectively;
the output ends D0_O4 (k+1) +1 and D0_O4 (k+1) +3 of the first D trigger group are directly connected to the data input ends D1_D4 (k+1) +1 and D1_D4 (k+1) +3 of the second D trigger group, the output ends D0_O4k+0-D0_O4k+3, D0_O4 (k+1) +2 are respectively connected to the data input ends INV2_I [4k+0] -INV2_I [4k+3], INV2_I [4 (k+1) +2], and the output ends INV2_O4k+0 ] -2_O4 [ 4+3 ], 2_O4 (k+1) +2] of the inverter group are connected to the data input ends INV2_O4+1, d4+4+1;
The second input terminal muxcy0_i1_0 of the first two-input data selector muxcy0 in the first CARRY-lookahead structure carry4_0 is used as a START signal terminal START to be tested; an input end inv1_i of the inverter INV1 is used as an end signal input port STOP to be detected; the first input end MUX2_I0 of the alternative multiplexer MUX2 is connected to the output end INV1_O of the inverter, and the second input end MUX2_I1 of the alternative multiplexer MUX2 is connected to the system clock end SYS_CLK;
the clock input ends D0_Cj of any jth D trigger D0[ j ] in the first D trigger group are all interconnected and connected to the output port MUX2_O of the alternative multiplexer MUX 2;
the clock input ends D1_Cj of any jth D trigger D1[ j ] in the second D trigger group are all interconnected and connected to the system clock end SYS_CLK;
the calibration circuit consists of an alternative multiplexer MUX3, an M-order ring oscillator RO and a random access memory block RAM0, wherein M is an odd number;
the M-stage ring oscillator consists of a two-input NAND gate NAND0 and M-1 inverters INV3[0] -INV3[ M-2 ];
the first input terminal NAND0_I0 of the two-input NAND gate NAND0 is connected to the output terminal INV3_O [ M-2] of the M-1 th inverter INV3[ M-2], the second input terminal NAND0_I1 is connected to the enable control signal EN, and the output terminal NAND0_O thereof is connected to the input terminal INV3_I0 of the first inverter INV3[ 0];
The output end inv3_o [ N ] of the nth inverter INV3[ N ] is connected to the input end inv3_i [ n+1] of the n+1th inverter INV3[ n+1], n=0, 1, … M-2;
the first input end MUX3_I0 of the alternative multiplexer MUX3 is connected to the output end INV3_O3 of the M-3 rd inverter INV3[ M-3] in the ring oscillator RO, and the second input end MUX3_I1 is connected to the gate SIGNAL to be tested TEST_SIGNAL.
2. A conversion method based on the high-precision time-to-digital converter of claim 1, characterized by the steps of:
step 1, an initial state;
enabling an enable control signal EN of an M-stage ring oscillator RO in the calibration circuit to be at a logic low level, enabling the ring oscillator RO not to oscillate, and outputting a fixed logic low level by an output end INV3_O3 of an M-2 inverter INV3[ M-3 ]; the control end MUX3_S of the alternative multiplexer MUX3 is in a logic low level, and the alternative multiplexer MUX3 sends an output end MUX3_O to output a logic low level SIGNAL to a SIGNAL end enable_signal to be detected in the sample hold circuit;
the data output end FDRE0_Q of the D trigger FDRE0 in the sample hold circuit outputs logic high level, so that two one-out-of-two multiplexers MUX0 and MUX1 gate the second input end; the output terminal mu0_o of the first one-out-of-two multiplexer MUX0 outputs the keep_signal, and the output terminal mu1_o of the second one-out-of-two multiplexer MUX1 outputs a logic low level, so that the exclusive or gate XOR0 acts as a buffer and its output terminal XOR0_o outputs the input SIGNAL keep_signal of the second input terminal XOR 0_i1; the SIGNAL to be measured (KEEP_SIGNAL) is logic low level, and after passing through a multiplexer MUX0, an exclusive OR gate XOR0 and BUFFERs BUFFER 0-BUFFER (m-1) in turn, the output end BUFFER_O [ m-1] of the (m-1) BUFFER BUFFER (m-1) outputs logic low level to a START SIGNAL end START and an end SIGNAL end STOP in the fine measurement circuit;
The output end MUXCY0_C0_j-MUXCY3_C3_j of four two-input data selectors MUXCY0_j-MUXCY3_j in any jth CARRY-ahead chain structure CARRY4_j in the fine measurement circuit outputs a logic low level;
the output ends XOR0_O0_j-XOR3_O3_j of four XOR gates XOR0_j-XOR3_j in any jth CARRY-forward chain structure CARRY4_j in the fine measurement circuit output logic high level, j=0, 1 … and n-1;
the partial D flip-flops D0[4k+0] -D0[4k+3], D0[4 (k+1) ] and D0[4 (k+1) +2] in the first D flip-flop group D0[0] -D0[4n-1] each output a logic high level from the output terminals D0_O4k+0 ] -D0_O4k+3 ], D0_O4 (k+1) +2, k=0, 2, …, n-2;
the outputs D1_O0-D1_O4n-1 of the second D flip-flop group D1[0] -D1[4n-1] all output logic low level, and the counter value of "1" is 0;
step 2, working states, including a calibration mode and a measurement mode:
step 2a, in the calibration mode:
2a.1, setting an enable control SIGNAL EN of an M-stage ring oscillator RO in the calibration circuit to be at a logic high level, starting oscillation of the ring oscillator RO, setting a control end MUX3_S of an alternative multiplexer MUX3 to be at a logic low level, and outputting a SIGNAL to be detected INV3_O [ M-3] to a SIGNAL to be detected end KEEP_SIGNAL in the sampling circuit by an output end MUX3_O;
2a.2. If the SIGNAL keep_signal to be detected in the sample-hold circuit completely enters the ring structure RO1, the output end buffer_o0 of the BUFFER0 generates a falling edge jump and inputs the falling edge jump to the inverter INV0, and after the output end INV0_o of the inverter INV0 outputs a rising edge jump SIGNAL and triggers the output end FDRE0_o of the D flip-flop FDRE0 to jump to a logic low level, so that the two alternative multiplexers MUX0 and MUX1 both gate the first input end; the output terminal mu0_o of the first one-out-of-two multiplexer MUX0 outputs a logic low level, and the output terminal mu1_o of the second one-out-of-two multiplexer MUX1 outputs the output signal buffer_o [0] of the m-1 st BUFFER (m-1), so that the exclusive or gate XOR0 functions as a BUFFER and its output terminal XOR0_o outputs the input signal buffer_o [0] of the first input terminal XOR 0_i0; in the process that the SIGNAL to be detected KEEP_SIGNAL is always circulated and propagated in the annular structure RO1, the sampling hold circuit outputs the SIGNAL to be detected KEEP_SIGNAL to a START SIGNAL end and an end SIGNAL end STOP in the fine measuring circuit through an output end BUFFER_O [ m-1] of an m-1 BUFFER BUFFER (m-1);
2a.3, setting the control end MUX2_S of the alternative multiplexer MUX2 in the fine measurement circuit to be at a logic high level;
When the rising edge of the SIGNAL to be detected keep_signal arrives, the logic high level of the SIGNAL to be detected keep_signal propagates in the CARRY-ahead structure CARRY4_0-CARRY4_n-1 through the START SIGNAL end START;
when the rising edge of the system clock sys_clk signal arrives, the first set of D flip-flops D0 propagate the START signal START to the state of the p-th two-input data selector MUXCY (p) _j in the j-th CARRY-look ahead chain structure carry4_j for latching, p=0, 1,2,3; on arrival of the rising edge of the next system clock sys_clk signal, the outputs d1_o [0] -d1_o [4j+p ] of the partial D flip-flops D1[0] -D1[4j+p ] in the second D flip-flop group D1[0] -D1[4n-1] output a logic high level, so that the output value num=4×j+p, j=0, 1..;
measuring the device delay time of four two-input data selectors MUXCY0-MUXCY3 in n CARRY-ahead structures CARRY4 and writing the device delay time into a random access memory block RAM0 in sequence, so that 4×n device delay data are written into 4×n addresses in total; then, summing the data of the ith and (i-1) th addresses in the random access memory block RAM0 and writing the data into the current ith address, and obtaining a calibration data storage table DATE_RAM0, wherein i=0, 1,2, n-1;
Step 2b, in the measurement mode:
2b.1, setting the enable control SIGNAL EN of the M-stage ring oscillator RO in the calibration circuit to be logic low level, setting the control end MUX3_S of the alternative multiplexer MUX3 to be logic high level, and outputting the gate SIGNAL TEST_SIGNAL to be tested by the output end MUX3_O;
step 2b.2. Is performed according to step 2a.2 in calibration mode;
2b.3, setting the control end MUX2_S of the alternative multiplexer MUX2 in the fine measurement circuit to be at a logic low level;
obtaining an output value NUM of a counter COUNT of a q-bit meter '1' according to the process of the step 2 a.3;
2b.4, taking the calibration data storage table DATE_RAM0 as a reference object, finding the value DATE_RAM0[ NUM-1] of the NUM-1 address, and taking the value DATE_RAM0 as a group of calibrated measurement results;
step 2b.5. Repeat step 2 b.1-step 2b.4 in the measurement mode, thus get the measurement result after the multiunit calibration, and take the average value as the final measurement result of the gate SIGNAL test_signal to be measured.
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| CN202121568U (en) * | 2011-07-11 | 2012-01-18 | 山东欧龙电子科技有限公司 | Time-digital converter |
| CN103795406A (en) * | 2014-01-23 | 2014-05-14 | 复旦大学 | High-performance gating vernier type time digital converter |
| CN113900369A (en) * | 2021-10-13 | 2022-01-07 | 中国科学院微电子研究所 | Time-to-digital converter, calibration method and chip |
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| CN103795406A (en) * | 2014-01-23 | 2014-05-14 | 复旦大学 | High-performance gating vernier type time digital converter |
| CN113900369A (en) * | 2021-10-13 | 2022-01-07 | 中国科学院微电子研究所 | Time-to-digital converter, calibration method and chip |
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