CN112711296B - Calibration system - Google Patents
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- CN112711296B CN112711296B CN202011561882.0A CN202011561882A CN112711296B CN 112711296 B CN112711296 B CN 112711296B CN 202011561882 A CN202011561882 A CN 202011561882A CN 112711296 B CN112711296 B CN 112711296B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The present application relates to a calibration system comprising: the digital test module, the control terminal and the relay array; the digital test module comprises: the system comprises a plurality of signal transmission channels, a programmable logic module and a main control module; the two ends of each signal transmission channel are respectively connected with the programmable logic module and the relay array; the main control module is in communication connection with the control terminal, and the programmable logic module is electrically connected with the relay array; the control terminal issues a delay calibration instruction to the main control module; the method comprises the steps that under the control of a delay calibration instruction, a main control module controls a programmable logic module to detect the internal transmission time length of each signal transmission channel in a digital test module, any two signal transmission channels form a closed loop through a relay array, and the programmable logic module detects the integral transmission time length of the closed loop; and the synchronous time sequence calibration is carried out on the digital test module, so that the problem of time delay among signal transmission channels of the digital test module is solved.
Description
Technical Field
The present application relates to the field of chip testing, and in particular, to a calibration system.
Background
Along with the advanced manufacturing process of the chip, the data transmission rate of the chip is faster and faster, and the time sequence relation requirement among the functional pins of the chip is higher and higher, and the quality of the chip is generally tested by connecting the signal transmission channels of the digital test module with the functional pins of the chip.
However, delay differences exist between the signal transmission channels of the digital test module and the connection of the functional pins of the chip, and the signal transmission channels cannot test the functional pins of the chip at the same time, so that the accuracy of the chip test is low.
There are generally two methods for inter-channel timing calibration: the first traditional method is to ensure the time sequence synchronization among the signal transmission channels by designing parameters such as wiring length, wiring group ports, the number of through holes, signal transmission speed and the like in advance, but the requirements on designers are very high, the design difficulty is high, and the cost is high; the second traditional method is to add a delay chip for each path of signal transmission channel, then send calibration signals to all signal transmission channels, and then adjust the delay chip according to the delay between the calibration signals received by the FPGA. This approach is very flexible in adjusting the delay of each signal transmission channel and can change at any time, but requires a large number of additional delay chips, which can increase the complexity, power consumption and cost of the device circuitry.
Disclosure of Invention
The application provides a calibration system which is used for solving the problem of time delay among signal transmission channels of a digital test module, and has low design difficulty and simple system constitution.
The embodiment of the application provides a calibration system, which comprises: the digital test module, the control terminal and the relay array;
the digital test module comprises: the system comprises a plurality of signal transmission channels, a programmable logic module and a main control module;
the two ends of each signal transmission channel are respectively connected with the programmable logic module and the relay array;
the main control module is in communication connection with the control terminal, and the programmable logic module is electrically connected with the relay array;
the control terminal is used for issuing a delay calibration instruction to the main control module;
the main control module is used for controlling the programmable logic module to detect the internal transmission time length of each signal transmission channel in the digital test module under the control of the delay calibration instruction, any two signal transmission channels form a closed loop through the relay array, and the main control module is used for controlling the programmable logic module to detect the integral transmission time length of the closed loop;
the main control module controls the programmable logic module to perform synchronous time sequence calibration on the internal transmission time length and the integral transmission time length;
the digital test module after the synchronous time sequence calibration is used for testing pins of the chip.
Optionally, the programmable logic module includes: a delay detection module and a time sequence calibration module;
the delay calibration instructions are divided into time sequences: a delay detection instruction and a timing calibration instruction;
the main control module of the digital test module is used for acquiring the delay detection instruction, under the control of the delay detection instruction, the main control module selects any one of the signal transmission channels as a reference channel, the signal transmission channels except the reference channel in the signal transmission channels are used as detected channels, the delay detection module is used for detecting and acquiring internal transmission time lengths of the reference channel and the detected channels and acquiring the integral transmission time length of a closed loop corresponding to each detected channel, wherein the closed loop is formed by the detected channels and the reference channel, and the internal transmission time length and the integral transmission time length are uploaded to the control terminal;
the control terminal is used for acquiring the time sequence difference of each tested channel relative to the reference channel according to the internal transmission time length and the overall transmission time length;
the control terminal is used for selecting a calibration time sequence and issuing a time sequence calibration command, the main control module is used for acquiring the time sequence calibration command, and under the control of the time sequence calibration command, the time sequence calibration module performs time sequence calibration on each signal transmission channel according to the calibration time sequence.
Optionally, the digital test module further comprises: a signal transfer module;
the delay detection instruction includes: a first control instruction;
the main control module is configured to obtain the first control instruction, and obtain internal transmission durations of the reference channel and the measured channel under control of the first control instruction, where the internal transmission durations include: a first time period and a second time period;
the main control module is used for selecting the reference channel, and controlling the delay detection module to detect and acquire a first time length occupied by the excitation signal in the reference channel to make a round trip from the programmable logic module to the signal transfer module, and a second time length occupied by the excitation signal in the detected channel to make a round trip from the programmable logic module to the signal transfer module.
Optionally, the relay array includes a control terminal;
the delay detection instruction further includes: a second control instruction; the overall transmission duration includes: a third time period and a fourth time period;
the main control module is used for acquiring the second control instruction, under the control of the second control instruction, the main control module sends a control signal to a control end of the relay array, the control end enables the relay array to be closed under the control of the control signal, a closed loop is formed by the reference channel and the tested channel, the main control module controls the delay detection module to detect and acquire a third time length occupied by the programmable logic module of the tested channel from the reference channel, and acquire a fourth time length occupied by the programmable logic module of the reference channel from the tested channel;
the main control module is used for uploading the first time length, the second time length, the third time length and the fourth time length to the control terminal.
Optionally, the control terminal is specifically configured to:
calculating the sending time sequence difference between the reference channel and the detected channel and the receiving time sequence difference between the reference channel and the detected channel according to the first time length, the second time length, the third time length and the fourth time length;
and selecting the calibration time sequence according to the sending time sequence difference and the receiving time sequence difference, and issuing the time sequence calibration instruction to the main control module.
Optionally, the control terminal is specifically configured to: acquiring a time sequence difference of the measured channel relative to the reference channel, selecting the maximum delay time length of the measured channel relative to the reference channel as the calibration time sequence, and issuing a time sequence calibration instruction;
the main control module is specifically used for: and receiving the time sequence calibration instruction, enabling the time sequence calibration module to be sequentially connected with the signal transmission channel, and sequentially carrying out time sequence calibration on the signal transmission channel according to the time sequence calibration instruction.
Optionally, the timing calibration module includes: an input/output serial-to-parallel converter and an input/output delay adjustment sub-module;
the input/output serial-to-parallel converter is connected with the input/output delay adjustment submodule and is used for performing first time sequence calibration on the plurality of signal transmission channels by adjusting the displacement of serial data of the plurality of signal transmission channels;
the input/output delay adjustment sub-module performs a second timing calibration for the plurality of signal transmission channels.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: according to the calibration system provided by the embodiment of the application, the control terminal is used for controlling the programmable logic module in the digital test module to detect, so that the internal transmission time length of each digital test module signal transmission channel and the overall transmission time length between any two signal transmission channels are obtained, the time difference between each signal transmission channel is determined according to the internal transmission time length and the overall transmission time length, and the programmable logic module is used for carrying out synchronous time sequence calibration on each signal transmission channel, so that a designer does not need to design a complex circuit to form, or a delay chip is added in each signal transmission channel.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a calibration system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a programmable logic module according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating signal transmission channel division of a digital test module according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a connection relationship between a signal transmission channel and a digital test module in an embodiment of the present application;
FIG. 5 is a schematic diagram of a timing calibration module according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a specific structure of a timing calibration module according to an embodiment of the present application;
fig. 7 is a schematic diagram of a connection relationship between a digital test module and a chip in an embodiment of the present application.
Reference numerals illustrate: the system comprises a 1-digital test module, a 2-control terminal, a 3-relay array, a 4-programmable logic module, a 5-main control module, a 6-signal transmission channel, a 7-delay detection module, an 8-time sequence calibration module, a 9-signal transfer module, a 10-input/output serial-parallel converter, an 11-input/output delay adjustment sub-module, a 12-working clock module and a 13-chip.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
As shown in fig. 1, an embodiment of the present application provides a calibration system, including: a digital test module 1, a control terminal 2 and a relay array 3.
The control terminal 2 may be a computer or a cloud server, and is mainly used for controlling the calibration process.
The digital test module comprises: a plurality of signal transmission channels 6, a programmable logic module 4 and a main control module 5.
Wherein, the programmable logic module 4 and the relay array 3 are respectively connected to the both ends of each signal transmission channel 6.
The main control module 5 is in communication connection with the control terminal 2, and the programmable logic module 4 is electrically connected with the relay array 3; the control terminal 2 is used for issuing a delay calibration instruction to the main control module 5; under the control of the delay calibration instruction, the main control module 5 controls the programmable logic module 4 to detect the internal transmission time length of each signal transmission channel 6 in the digital test module 1, any two signal transmission channels 6 form a closed loop through the relay array 3, and the main control module 5 is used for controlling the programmable logic module 4 to detect the whole transmission time length of the closed loop; the main control module 5 controls the programmable logic module 4 to perform synchronous time sequence calibration on the internal transmission time length and the whole transmission time length.
The digital test module 1 after synchronous time sequence calibration is used for testing pins of the chip 13.
In one particular embodiment, as shown in FIG. 2, the programmable logic module 4 includes: the delay detection module 7 and the time sequence calibration module 8 are connected with the time sequence calibration module 8;
the delay calibration instructions are time-sequentially divided into: a delay detection instruction and a timing calibration instruction;
the main control module 5 of the digital test module 1 is used for acquiring a delay detection instruction, under the control of the delay detection instruction, the main control module 5 selects any one signal transmission channel 6 in the plurality of signal transmission channels 6 as a reference channel, the signal transmission channels 6 except the reference channel in the plurality of signal transmission channels 6 are used as detected channels, the delay detection module 7 is used for detecting and acquiring internal transmission time lengths of the reference channel and the detected channels and acquiring the integral transmission time length of a closed loop corresponding to each detected channel, wherein the closed loop is formed by the detected channels and the reference channels, and the internal transmission time length and the integral transmission time length are uploaded to the control terminal;
the control terminal 2 is used for acquiring the time sequence difference of each tested channel relative to the reference channel according to the internal transmission time length and the overall transmission time length;
the control terminal 2 is used for selecting a calibration time sequence and issuing a time sequence calibration command, and the main control module 5 is used for acquiring the time sequence calibration command, so that the time sequence calibration module 8 performs time sequence calibration on each signal transmission channel according to the calibration time sequence under the control of the time sequence calibration command.
For example, as shown in fig. 3, the present application is illustrated by taking four signal transmission channels 6 of the digital test module 1 as an example for convenience of understanding, but not necessarily the number of the signal transmission channels 6 in the digital test module 1 is four, any number of signal transmission channels may be provided, and the number of the signal transmission channels 6 of the digital test module 1 is not specifically limited herein.
The four signal transmission channels 6 of the digital test module 1 are a first signal transmission channel, a second signal transmission channel, a third signal transmission channel and a fourth signal transmission channel from top to bottom in sequence, the main control module 5 selects the first signal transmission channel as a reference channel, and the second signal transmission channel, the third signal transmission channel and the fourth signal transmission channel are respectively used as a first tested channel, a second tested channel and a third tested channel, and the delay detection module respectively detects and acquires internal transmission time lengths of the reference channel, the first tested channel, the second tested channel and the third tested channel.
The choice of reference channel is not particularly limited here, and all signal transmission channels 6 may be used as reference channels.
The delay detection module 7 detects and obtains the overall transmission time length of the reference channel and the first detected channel, the overall transmission time length of the reference channel and the second detected channel, and the overall transmission time length of the reference channel and the third detected channel, and sends the internal transmission time length and the overall transmission time length to the control terminal 2.
The control terminal 2 obtains a first time sequence difference of the first measured channel relative to the reference channel according to the internal transmission time length of the reference channel, the internal transmission time length of the first measured channel and the overall transmission time length of the reference channel and the first measured channel.
The control terminal 2 obtains a second time sequence difference of the second measured channel relative to the reference channel according to the internal transmission time length of the reference channel, the internal transmission time length of the second measured channel and the overall transmission time length of the reference channel and the second measured channel.
The control terminal 2 obtains a third time sequence difference of the third measured channel relative to the reference channel according to the internal transmission time length of the reference channel, the internal transmission time length of the third measured channel and the overall transmission time length of the reference channel and the third measured channel.
The control terminal 2 selects an appropriate calibration timing according to the first timing difference, the second timing difference, and the third timing difference.
In a specific embodiment, as shown in fig. 4, the digital test module 1 further includes: a signal relay module 9;
the delay detection instruction includes: a first control instruction;
the main control module 5 is configured to obtain a first control instruction, and obtain internal transmission durations of the reference channel and the measured channel under the control of the first control instruction, where the internal transmission durations include: a first time period and a second time period;
the main control module 5 is used for selecting a reference channel, and the control delay detection module 7 is used for detecting and acquiring a first time length occupied by the excitation signal in the reference channel, which passes through the programmable logic module 4 and the signal transit module 9, and a second time length occupied by the excitation signal in the detected channel, which passes through the programmable logic module 4 and the signal transit module 9.
The first time period includes: the internal sending duration and the internal receiving duration of the reference channel, wherein the second duration comprises: the internal sending duration and the internal receiving duration of the detected channel.
In one embodiment, the relay array 3 includes a control terminal;
the delay detection instruction further includes: a second control instruction; the overall transmission duration includes: a third time period and a fourth time period;
the main control module 5 is used for acquiring a second control instruction, under the control of the second control instruction, the main control module 5 sends a control signal to the control end of the relay array 3, the control end enables the relay array 3 to be closed under the control of the control signal, a closed loop is formed by the reference channel and the tested channel, the main control module 5 controls the delay detection module 7 to detect and acquire a third time length occupied by the programmable logic module 4 of the tested channel from the reference channel, and acquire a fourth time length occupied by the programmable logic module 4 of the reference channel from the tested channel;
the main control module is used for uploading the first time length, the second time length, the third time length and the fourth time length to the control terminal.
The third time period includes: the method comprises the steps of internal sending time of a reference channel, external wiring time of the reference channel, external wiring time of a tested channel and internal receiving time of the tested channel.
The fourth time period includes: the method comprises the steps of internal sending time of a detected channel, external wiring time of the detected channel, external wiring time of a reference channel and internal receiving time of the reference channel.
In a specific embodiment, the control terminal is specifically configured to:
according to the first time length, the second time length, the third time length and the fourth time length, calculating the sending time sequence difference between the reference channel and the tested channel and the receiving time sequence difference between the reference channel and the tested channel;
according to the sending time sequence difference and the receiving time sequence difference, a calibration time sequence is selected, and a time sequence calibration instruction is issued to the main control module 5.
In specific implementation, the first time period is set to be T1, the second time period is set to be T2, the third time period is set to be T3, and the fourth time period is set to be T4.
The method comprises the steps of setting the internal sending time length of a reference channel to be A, the internal receiving time length of the reference channel to be B, the internal sending time length of a detected channel to be C, the internal receiving time length of the detected channel to be D, the external wiring time length of the reference channel to be E and the external wiring time length of the detected channel to be F.
Then there are: t1=a+b;
T2＝C+D；
T3＝A+E+F+D；
T4＝C+E+F+B；
transmission timing difference between reference channel and measured channel: a-c= (T1-T2-t3+t4)/2.
Reception timing difference between the reference channel and the channel under test: b-d= (t1+t2-T3-T4)/2.
If the time sequence difference value is negative, the time sequence difference value indicates that the sending or receiving delay of the tested channel is larger than that of the reference channel, namely the tested channel lags behind the reference channel.
If the time sequence difference value is positive, the time sequence difference value indicates that the sending or receiving delay of the tested channel is smaller than that of the reference channel, namely the tested channel is advanced to the reference channel.
In a specific embodiment, the control terminal 2 is specifically configured to: acquiring time sequence difference of a detected channel relative to a reference channel, selecting the maximum delay time length of the detected channel relative to the reference channel as a calibration time sequence, and issuing a time sequence calibration instruction;
the main control module 5 is specifically configured to: and receiving a time sequence calibration instruction, enabling the time sequence calibration module 8 to be sequentially connected with the signal transmission channel 6, and sequentially performing time sequence calibration on the signal transmission channel 6 according to the time sequence calibration instruction.
In general, to facilitate the calibration process of the digital test module 1, a maximum delay time length of the tested channel relative to the reference channel is selected, or the maximum delay time length is delayed to be used as a calibration time sequence.
For example, the digital test module 1 is provided with four signal transmission channels, the delay time length of the first tested channel relative to the reference channel is 10ns (nanosecond), the delay time length of the second tested channel relative to the reference channel is 5ns, the advance time length of the third tested channel relative to the reference channel is 2ns, the delay time length of the first tested channel is selected by the control terminal to be a calibration time sequence, and the digital calibration module carries out time sequence on the reference channel, the second tested channel and the third tested channel: the reference channel lag is 10ns, the second measured channel lag is 5ns and the third measured channel lag is 12ns, so that synchronous time sequence calibration of the digital test module 1 is realized.
In one particular embodiment, as shown in fig. 5, the timing calibration module 8 includes: an input/output serial-to-parallel converter 10 and an input/output delay adjustment sub-module 11;
the input/output serial-to-parallel converter 10 is connected to the input/output delay adjustment sub-module 11, and the input/output serial-to-parallel converter 10 performs a first timing calibration on the plurality of signal transmission channels 6 by adjusting the displacement of serial data of the plurality of signal transmission channels 6;
the input/output delay adjustment sub-module 11 performs the second timing calibration for the plurality of signal transmission channels 6.
The first time sequence calibration is a coarse calibration stage, ns-level calibration is carried out by adjusting serial data displacement, the second time sequence calibration is a fine calibration stage, and the second time sequence calibration is generally used for carrying out ps (picosecond) -level fine adjustment on the time sequence after the coarse calibration stage, so that excitation signals in all signal transmission channels 6 in the digital test module 1 are ensured to reach the tested chip 13 at the same time, and the accuracy of the data test module 1 to test the chip 13 is ensured.
In particular, as shown in fig. 6, the timing calibration module 8 further includes: the working clock module 12 performs coarse adjustment by adjusting the displacement of the serial data between the signal transmission channels 6, that is, "1" and "0" on the left side of the input/output serial-parallel converter in the figure are adjusted, so that the time of the "1" output is changed, the period of the working clock module 12 with the adjustment unit of 1/8 is the period of the working clock module 12 with the adjustment unit of 1/8 only for the convenience of understanding, the adjustment unit of the displacement of the serial data is not specifically limited, a proper adjustment unit can be selected according to the actual situation, and next, ps-level fine adjustment is performed by the input/output delay adjustment sub-module 11.
Taking the deviation between the signal transmission channel 6 and the calibration time sequence as an example, the displacement of the channel output serial-parallel converter by adjusting 2 bits can be compensated by 1.25ns under the adjustment of 800MHz of the working clock, and the fine adjustment of 0.1ns can be realized through the delay setting of the output delay adjustment submodule, so that the synchronism of the digital signals of each channel reaching the pins of the chip to be tested can be finally realized.
In a specific embodiment, as shown in fig. 7, the digital test module 1 after the calibration of the synchronous time sequence of the calibration system of the present application is connected to the pins of the chip 13 through the signal transmission channel 6 to test the chip 13.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A calibration system, comprising: the digital test module, the control terminal and the relay array;
the digital test module comprises: the system comprises a plurality of signal transmission channels, a programmable logic module and a main control module;
the two ends of each signal transmission channel are respectively connected with the programmable logic module and the relay array;
the main control module is in communication connection with the control terminal, and the programmable logic module is electrically connected with the relay array;
the control terminal is used for issuing a delay calibration instruction to the main control module;
the main control module is used for controlling the programmable logic module to detect the internal transmission time length of each signal transmission channel in the digital test module under the control of the delay calibration instruction, any two signal transmission channels form a closed loop through the relay array, and the main control module is used for controlling the programmable logic module to detect the integral transmission time length of the closed loop;
the main control module controls the programmable logic module to perform synchronous time sequence calibration on the internal transmission time length and the integral transmission time length;
the digital test module after the synchronous time sequence calibration is used for testing pins of the chip;
wherein the programmable logic module comprises: a delay detection module and a time sequence calibration module;
the delay calibration instructions are divided into time sequences: a delay detection instruction and a timing calibration instruction;
the main control module of the digital test module is used for acquiring the delay detection instruction, under the control of the delay detection instruction, the main control module selects any one of the signal transmission channels as a reference channel, the signal transmission channels except the reference channel in the signal transmission channels are used as detected channels, the delay detection module is used for detecting and acquiring internal transmission time lengths of the reference channel and the detected channels and acquiring the integral transmission time length of a closed loop corresponding to each detected channel, wherein the closed loop is formed by the detected channels and the reference channel, and the internal transmission time length and the integral transmission time length are uploaded to the control terminal;
the control terminal is used for acquiring the time sequence difference of each tested channel relative to the reference channel according to the internal transmission time length and the overall transmission time length;
the control terminal is used for selecting a calibration time sequence and issuing a time sequence calibration command, the main control module is used for acquiring the time sequence calibration command, and under the control of the time sequence calibration command, the time sequence calibration module performs time sequence calibration on each signal transmission channel according to the calibration time sequence.
2. The system of claim 1, wherein the digital test module further comprises: a signal transfer module;
the delay detection instruction includes: a first control instruction;
the main control module is configured to obtain the first control instruction, and obtain internal transmission durations of the reference channel and the measured channel under control of the first control instruction, where the internal transmission durations include: a first time period and a second time period;
the main control module is used for selecting the reference channel, and controlling the delay detection module to detect and acquire a first time length occupied by the excitation signal in the reference channel to make a round trip from the programmable logic module to the signal transfer module, and a second time length occupied by the excitation signal in the detected channel to make a round trip from the programmable logic module to the signal transfer module.
3. The system of claim 2, wherein the relay array comprises a control terminal;
the delay detection instruction further includes: a second control instruction; the overall transmission duration includes: a third time period and a fourth time period;
the main control module is used for acquiring the second control instruction, under the control of the second control instruction, the main control module sends a control signal to a control end of the relay array, the control end enables the relay array to be closed under the control of the control signal, a closed loop is formed by the reference channel and the tested channel, the main control module controls the delay detection module to detect and acquire a third time length occupied by the programmable logic module of the tested channel from the reference channel, and acquire a fourth time length occupied by the programmable logic module of the reference channel from the tested channel;
the main control module is used for uploading the first time length, the second time length, the third time length and the fourth time length to the control terminal.
4. A system according to claim 3, wherein the control terminal is specifically configured to:
calculating the sending time sequence difference between the reference channel and the detected channel and the receiving time sequence difference between the reference channel and the detected channel according to the first time length, the second time length, the third time length and the fourth time length;
and selecting the calibration time sequence according to the sending time sequence difference and the receiving time sequence difference, and issuing the time sequence calibration instruction to the main control module.
5. The system of claim 4, wherein the control terminal is specifically configured to: acquiring a time sequence difference of the measured channel relative to the reference channel, selecting the maximum delay time length of the measured channel relative to the reference channel as the calibration time sequence, and issuing a time sequence calibration instruction;
the main control module is specifically used for: and receiving the time sequence calibration instruction, enabling the time sequence calibration module to be sequentially connected with the signal transmission channel, and sequentially carrying out time sequence calibration on the signal transmission channel according to the time sequence calibration instruction.
6. The system of claim 1, wherein the timing calibration module comprises: an input/output serial-to-parallel converter and an input/output delay adjustment sub-module;
the input/output serial-to-parallel converter is connected with the input/output delay adjustment submodule and is used for performing first time sequence calibration on the plurality of signal transmission channels by adjusting the displacement of serial data of the plurality of signal transmission channels;
the input/output delay adjustment sub-module performs a second timing calibration for the plurality of signal transmission channels.
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| CN114646870B (en) * | 2022-02-07 | 2024-03-12 | 苏州华兴源创科技股份有限公司 | Time sequence calibration method and system |
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