CN115792769B - Signal calibration method and system of semiconductor test equipment and computer equipment - Google Patents
Signal calibration method and system of semiconductor test equipment and computer equipment Download PDFInfo
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Abstract
The application relates to a signal calibration method and system of semiconductor test equipment and computer equipment. In one embodiment, the sampling data of a plurality of channels of the test device are transmitted to the programmable logic controller, the programmable logic controller can analyze and obtain the sampling data of each target channel, and then further perform inverse operation on the sampling data according to the output circuit of each target channel to obtain available restored data, and a calibration value can be obtained from the restored data according to a calibration algorithm. Therefore, the data of a plurality of target channels can be simultaneously analyzed and restored by presetting corresponding programs in the programmable logic controller, and the calibration value is rapidly calculated, so that the signal calibration speed of the test equipment is greatly increased, the calibration efficiency is improved, and more plentiful time is provided for the subsequent test process.
Description
Technical Field
The disclosure relates to the field of testing, and in particular, to a signal calibration method, a system and a computer device for a semiconductor test device.
Background
With the development of chip technology, the precision degree of the tip chip is higher and higher, and the requirement on a circuit is also higher and higher. Particularly, in the process of manufacturing and testing a chip, in order to keep the voltage or current at two ends of the chip to be tested to meet the standard, an output end of a chip testing device is required to provide a sufficiently stable and accurate voltage or current. ATE (Automatic Test Equipment ) is a chip test device used in the semiconductor industry, and a main control chip of the ATE can provide various chip test schemes according to different requirements, and is matched with a high-precision power supply board, so that the ATE is often used for testing the performance of chips.
However, even if the semiconductor test apparatus can provide an accurate output signal, some factors such as line impedance, device disturbance, etc. in the circuit may affect the output voltage and current. In addition, performance degradation may also occur in the internal chips or devices of the test equipment due to time and other factors. In the prior art, the accuracy problem is solved by calibrating the output signal, but high-efficiency calibration is difficult to realize in the actual process flow. The semiconductor test equipment has a plurality of output channels, and the mode of carrying out sampling calibration channel by channel has complicated process and long time consumption.
Disclosure of Invention
Based on the above, a signal calibration method, system and computer device for a semiconductor test device are provided. The technical scheme of the present disclosure is as follows:
according to an aspect of the disclosed embodiments, there is provided a signal calibration method of a semiconductor test apparatus, applied to a programmable logic controller electrically connected to the test apparatus, including:
acquiring target sampling data; the target sampling data are obtained by sampling signals output by all target channels of the test equipment;
Carrying out channel analysis on the target sampling data to obtain sampling data matched with each target channel;
performing inverse operation processing on the sampling data matched with each target channel based on the logic output circuit of each target channel to obtain first restored data;
performing data precision conversion on the first restored data to obtain second restored data;
and calibrating the second restored data according to a preset calibration algorithm to obtain a calibration value.
In one embodiment, the programmable logic controller includes a divider, and the performing data precision conversion on the first restored data to obtain second restored data includes:
inputting the first restored data as a dividend into the divider; wherein the divider stores a preset divisor;
and controlling the divider to divide the dividend and the divisor, and taking the obtained quotient as second restored data.
In one embodiment, before inputting the first restored data as the dividend into the divider, the method further comprises:
expanding the first reduction data by a designated multiple to obtain expanded first reduction data;
The step of inputting the first reduction data as a dividend into the divider, controlling the divider to divide the dividend and the divisor, and taking the obtained quotient as second reduction data comprises the following steps:
inputting the expanded first reduction data into the divider as a dividend, and controlling the divider to divide the dividend and the divisor to obtain a quotient;
and reducing the quotient by the specified multiple to obtain second reduction data.
In one embodiment, the target sampling data is obtained by sampling signals output by each target channel of the test device for a preset number of times, and the performing channel analysis on the target sampling data to obtain sampling data matched with each target channel includes:
carrying out channel analysis on the target sampling data to obtain initial sampling data of the preset times matched with each target channel;
and taking the average value of the initial sampling data of the preset times as sampling data matched with each target channel.
In one embodiment, the programmable logic controller is further electrically connected to an upper computer, and the upper computer is electrically connected to the test device; the upper computer is used for selecting a test value of a target number according to the output range of the test equipment; controlling the test equipment to sequentially output test signals of the test values;
The acquiring target sampling data includes:
acquiring sampling data corresponding to the test signals by using a programmable logic controller; the upper computer is further used for calibrating the sampling data according to the programmable logic controller to obtain calibration values of the target number, and generating a calibration curve; acquiring an actual signal value corresponding to the test signal, and generating an actual signal curve; comparing the calibration curve with the actual signal curve, and performing interval calibration on the part of the calibration curve, the error of which exceeds a preset standard, so as to generate interval calibration parameters.
In one embodiment, the upper computer is further configured to set a start value and a step size according to an output range of the test device; selecting a starting value as a first test value, and sequentially increasing step sizes on the basis of the starting value to obtain the rest test values; the test value does not exceed the output range of the test device.
According to another aspect of the embodiments of the present disclosure, there is provided a signal calibration system of a semiconductor test apparatus, including:
the data acquisition module is used for acquiring target sampling data; the target sampling data are obtained by sampling signals output by all target channels of the test equipment;
The channel analysis module is used for carrying out channel analysis on the target sampling data to obtain sampling data matched with each target channel;
the data conversion module is used for carrying out inverse operation processing on the sampling data matched with each target channel based on the logic output circuit of each target channel to obtain first restored data;
the precision conversion module is used for carrying out data precision conversion on the first restored data to obtain second restored data;
and the calibration module is used for calibrating the second restored data according to a preset calibration algorithm to obtain a calibration value.
According to another aspect of the embodiments of the present disclosure, there is also provided a computer device including a memory storing a computer program and a processor implementing the steps of the above method when the processor executes the computer program.
According to another aspect of the disclosed embodiments, there is also provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the above method.
According to another aspect of the disclosed embodiments, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of the above method.
According to the technical scheme provided by the embodiment of the disclosure, the sampling data of a plurality of channels of the test equipment are transmitted to the programmable logic controller, the programmable logic controller can analyze and obtain the sampling data of each target channel, and then the sampling data are inversely operated according to the output circuit of each target channel to obtain available restored data, and a calibration value can be obtained from the restored data according to a calibration algorithm. Therefore, the data of a plurality of target channels can be simultaneously analyzed and restored by presetting corresponding programs in the programmable logic controller, and the calibration value is rapidly calculated, so that the signal calibration speed of the test equipment is greatly increased, the calibration efficiency is improved, and more plentiful time is provided for the subsequent test process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the following description will briefly explain the embodiments or the drawings used in the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present description, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of calibrating signals of a test device in one embodiment;
FIG. 2 is a flow diagram of data precision conversion of first restored data in one embodiment;
FIG. 3 is a flow diagram of channel resolution of target adoption data in one embodiment;
FIG. 4 is a block diagram of the execution of a calibration process by a programmable logic controller in one embodiment;
FIG. 5 is a flow diagram of segment interval calibration of test equipment in one embodiment;
FIG. 6 is an effect diagram of two-stage calibration according to the method shown in FIG. 5 in one embodiment;
FIG. 7 is an effect diagram of four-stage calibration according to the method shown in FIG. 5 in one embodiment;
FIG. 8 is a schematic diagram of a signal calibration system of a test device in one embodiment;
FIG. 9 is a schematic diagram of the internal architecture of a computer device in one embodiment.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.
It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, it is not excluded that additional identical or equivalent elements may be present in a process, method, article, or apparatus that comprises a described element. For example, if first, second, etc. words are used to indicate a name, but not any particular order.
The terms "vertical," "horizontal," "left," "right," "upper," "lower," "front," "rear," "circumferential," "direction of travel," and the like as used herein are based on the orientation or positional relationship shown in the drawings and are merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or", "at least one of …" as used herein includes any and all combinations of one or more of the associated listed items. The connection, etc. described in the present disclosure may be a direct connection through an interface or a pin between devices, or may be a connection through a wire, or may be a wireless connection (communication connection).
In general, calibration of ATE test equipment may correct output signal errors of ATE equipment by adjusting calibration registers within the ATE chip, and set signals may be calibrated primarily by gain and bias factors of the calibration registers. However, the output channels of the ATE test apparatus are numerous, the Gain (Gain) and Offset (Offset factor) used for calibration of different channels are different, and the ATE test apparatus may use different types of power boards such as SMU (Source Measure Unit, source measurement unit) boards to provide a high-precision and multi-range power output interface. However, the types of DAC chips used for output in different power boards are different, and each output chip provides a plurality of output interfaces according to its internal circuit structure, which results in that the calibration process of the output channels of the ATE equipment is not uniform, and even though the calibration is performed by software, different calibration algorithms are designed to calibrate the test equipment. Therefore, calibration of the output signal of ATE test equipment is often time consuming and laborious due to the diverse nature of its output channels.
In order to solve the above problems, as shown in fig. 1, a signal calibration method of a test device is provided, which can be applied to a programmable logic controller connected to the test device, and the method includes:
Step S202, acquiring target sampling data; the target sampling data are obtained by sampling signals output by all target channels of the test equipment. For example, the test device typically uses a DAC chip to output signals to each channel, and the signals output by the DAC may be sampled by an ADC sampling chip, and the data obtained by the ADC sampling may be sent to an FPGA connected to the DAC.
Specifically, data obtained by sampling output signals of each target channel of the test equipment by the sampling chip in the ATE test equipment can be sent to the programmable logic controller. The target channels are a plurality of output channels for sampling and calibrating at the moment, the signals output by the target channels are voltages or currents, and the target sampling data are a series of data in a digital signal format which represents the voltages and/or currents output by the target channels. The programmable logic controller may be an FPGA (Field Programmable Gate Array ).
Step S204, carrying out channel analysis on the target sampling data to obtain sampling data matched with each target channel.
Specifically, after receiving the target adoption data sent by the sampling chip, the programmable logic controller can analyze the target sampling data through a serial-parallel conversion function, and restore the target sampling data containing serial modes of all channels into sampling data matched with each target channel. The serial mode target sampling data refers to data obtained by sampling by the sampling chip, wherein the data are mixed by a plurality of target channel data.
Step S206, based on the logic output circuit of each target channel, performing inverse operation processing on the sampling data matched with each target channel to obtain first restored data.
The logic output circuit can be an internal circuit of which the output chip of the test equipment controls the corresponding output channel to output signals outwards. For example, when the output chip of the test device is a DAC chip, the logic output circuit may be an output parameter described in the DAC chip usage manual, and the output parameter may be used to represent output logic of the DAC chip. The inverse operation processing is to convert the sampling data according to the circuit logic of the output signal of each channel, and restore the sampling value to the actual value of the output signal.
Specifically, after the data of each target channel is obtained, the internal logic output circuit of the output chip and the corresponding expression formula can be obtained by referring to the instruction manual of the output chip of the test equipment, and the expression formula is input into the programmable logic controller, and the sampling data of each target channel is converted from a digital signal into first computable restored data according to the formula. The first reduction data is an output voltage value or a current value of each target channel. In some other embodiments, if the output chip is a DAC, the DAC parameters may be obtained by referring to a manual, and the sampled data of each target channel sampled by the ADC may be inversely calculated and restored to obtain an actual output value according to the DAC parameters, so as to restore the obtained actual output value as the first restored data.
It should be noted that, since the integer data is used when the programmable logic controller processes the digital signal, the data of nA (nanoampere) level or μv (microvolts) level is used when the sampled data of each target channel is converted from the digital signal according to the formula, and the converted first recovery data is also data of nA (nanoampere) level or μv (microvolts) level. Wherein nA (nanoampere) is a current unit.
And step S208, performing data precision conversion on the first restored data to obtain second restored data.
The programmable logic controller may implement conversion of the numerical precision by using a software algorithm and/or a hardware circuit, for example, converting the nA-level current value obtained in step S204 into an a-level current value.
In particular, the first reduction data may be converted from nA (nanoampere) level or μv (microvolt) level to second reduction data of a (ampere) level or V (volt) level by a divider function of the programmable logic controller. The divider function can be realized by an FPGA software function or a hardware circuit.
Step S210, calibrating the second restored data according to a preset calibration algorithm to obtain a calibration value.
The preset calibration algorithm comprises a calibration parameter and a calibration formula of each target channel, wherein the calibration parameter comprises a gain and a bias factor.
Specifically, the second restored data of each target channel may be calibrated by the following calibration formula:
D 1 =D 2 ×G+F （1）
in the above formula (1), D 1 For the calibrated value, D 2 For the second restored data, G is the gain and F is the bias factor. In some specific implementations, the format of the second recovery data may also be converted prior to calibration, as required by the calibration algorithm or calibration formula. For example, when the calibration algorithm or the calibration formula performs the calibration operation in the form of floating point number, if the second recovery data is the fixed point number, the second recovery data may be converted from the fixed point number to the floating point number, and then the corresponding calibration operation is performed to obtain the calibration value.
According to the technical scheme provided by the embodiment of the disclosure, the sampling data of a plurality of channels of the test equipment are transmitted to the programmable logic controller, the programmable logic controller can analyze and obtain the sampling data of each target channel, and then the sampling data are inversely operated according to the output circuit of each target channel to obtain available restored data, and a calibration value can be obtained from the restored data according to a calibration algorithm. Therefore, the data of a plurality of target channels can be simultaneously analyzed and restored by presetting corresponding programs in the programmable logic controller, and the calibration value is rapidly calculated, so that the signal calibration speed of the test equipment is greatly increased, the calibration efficiency is improved, and more plentiful time is provided for the subsequent test process.
In one embodiment, as shown in fig. 2, the programmable logic controller includes a divider, and the performing data precision conversion on the first restored data to obtain second restored data includes:
step S2082, inputting the first restored data as a dividend into the divider; wherein the divider stores a preset divisor.
Specifically, the first restored data may be used as a dividend of the divider, and the pre-calculated precision may be set as a divisor whose value may be determined by the data units before and after the conversion. For example, when the first reduction data is converted from nA units to a units, the divisor may be set to 1000000000. The divider is a functional circuit used for realizing division operation in the programmable logic controller.
And S2084, controlling the divider to divide the dividend and the divisor, and taking the obtained quotient as second restored data.
Specifically, the programmable logic controller may control the divider to perform division operation after the dividend and the divisor are set, and use the quotient obtained by the division operation as the second reduction data.
In the above embodiment, the current value of the nanoampere level or the voltage value of the microvolt level may be converted into the current value of the ampere level or the voltage value of the volt level by the divider, respectively. Therefore, the data format of each target channel can be unified with the format of the programmable logic controller running the calibration algorithm, and the calibration speed is further increased.
The output of ATE test equipment can be divided into several different gears according to its range, for example, using SMU power board card can output current of 80mA (milliamp) level in high current gear and 5 μa (microampere) level in low current gear. In the above calibration method, since the divider has a bit width limitation, in some conventional dividers, the dividend occupies a bit width of at most 64 bits, and the symbol bit is removed to leave 63 bits. In addition, the bit width occupied by the divisor is limited in order to be compatible with the current calculation requirements of different gears. For example, in a specific application process of a divider, if it is desired to ensure the calculation accuracy of 80mA (milliamp) class current, the bit width of the divisor needs at least 30 bits, and the available bit width of the current representing the quotient is: 63-30=33, the removal of the sign bit leaving 32 bits can be used to represent current accuracy. However, when the output current is μa, the number of bits actually required by the corresponding divisor is less than 20 bits, and the divisor bit width is set to 30 bits under the condition of considering a large current range, so that a spare bit width is generated at this time, the bit width is wasted, and the minimum current precision of the ATE equipment is limited.
In one embodiment, before inputting the first restored data as the dividend into the divider, further comprising:
And expanding the first reduction data by a designated multiple to obtain expanded first reduction data.
Specifically, when the target sampling data is a current value in a small current gear range, the first reduction data may be multiplied by M to obtain a product of the first reduction data and M. Wherein M is a positive number.
The step of inputting the first reduction data as a dividend into the divider, controlling the divider to divide the dividend and the divisor, and taking the obtained quotient as second reduction data comprises the following steps:
inputting the expanded first reduction data into the divider as a dividend, and controlling the divider to divide the dividend and the divisor to obtain a quotient;
and reducing the quotient by the specified multiple to obtain second reduction data.
Specifically, after the divider performs the division operation, the obtained quotient is divided by M and then used as the second restoration data.
It should be noted that, the method of expanding the first reduction data by a specified multiple in this embodiment may be applied to a case where the sampled data is in the low current gear range of the power board, so that the bit width of the divider may be fully utilized. And the first restored data obtained from the sampled data in the high-current gear may not be changed. The expansion specified multiple in this embodiment may be determined according to the utilization degree of the divider bit width by the first reduction data formed under different current levels. The definition of the low current gear may also be determined based on the degree of utilization of the divider bit width.
In the above embodiment, by expanding the first restored data by a given multiple M, the spare bit width of the divider can be fully utilized in a small gear of the ATE test apparatus, and the multiple can be reduced after the divider operation is completed. In the original mode, the minimum current can only be used for the nanoampere level, and the minimum current can be used for 1/M nanoampere level after the method is used. Therefore, the processing precision of the small current is improved by M times under the condition that the divider structure is not changed, and the signal calibration precision of the test equipment is further improved.
In one embodiment, the target sampling data is obtained after sampling the signals output by each target channel of the test device for a preset number of times, as shown in fig. 3, and the performing channel analysis on the target sampling data to obtain sampling data matched with each target channel includes:
step S2041, carrying out channel analysis on the target sampling data to obtain initial sampling data of the preset times matched with each target channel.
The initial sampling data of each channel obtained through analysis comprises sampling data of preset times of the same output signal.
Step S2042, taking the average value of the initial sampling data of the preset times as the sampling data matched with each target channel.
Specifically, after obtaining the sampling data of the preset times of each target channel, the programmable logic controller can accumulate the multiple sampling data of the single channel, divide the accumulated value by the sampling times to obtain an average value, and use the average value as the sampling data matched with each target channel.
In the above embodiment, the data sampled multiple times are summed and averaged, and the average value is used as the reference for the subsequent conversion calculation, so that errors possibly caused by single sampling can be effectively avoided, and the sampling precision is improved.
In the prior art, the calibration of the test equipment is usually performed once in the full range, that is, the calibration parameters stored in the test equipment are the same in the full range. Because the measuring range of the full-range is larger, the error at certain measuring ranges after calibration is smaller, and the error at other measuring ranges is larger, so that the accuracy requirement in the full-range cannot be ensured.
In one embodiment, the programmable logic controller is further electrically connected with an upper computer, and the upper computer is electrically connected with the test equipment; the upper computer is used for selecting a test value of a target number according to the output range of the test equipment; and controlling the test equipment to sequentially output test signals of the test values.
Specifically, according to the output range of the target channel of the test equipment, a plurality of test values can be selected through the upper computer. In some other implementations, the test values may be selected uniformly across the span according to the accuracy requirements of the calibration in order to perform a segmented interval calibration of the full span. For example, the range of the output voltage of the target channel of the test equipment is-8V, and the output voltage value with the step length of 1V can be set. The output voltage may be set to: -8V, -7V, -6V, -5V, -4V, -3V, -2V, -1V, 0V, 1V, 2V, 3V, 4V, 5V, 6V, 7V, 8V are test values of the output voltage; the testing equipment sequentially outputs corresponding voltages under the control of the upper computer. The upper computer can be an electronic device with data processing function and control function, such as a computer, a singlechip and the like which are connected with the programmable logic controller and the testing device.
The acquiring the sampling data includes:
acquiring sampling data corresponding to the test signals by using a programmable logic controller; the upper computer is further used for calibrating the sampling data according to the programmable logic controller to obtain calibration values of the target number, and generating a calibration curve; acquiring an actual signal value corresponding to the test signal, and generating an actual signal curve; comparing the calibration curve with the actual signal curve, and performing interval calibration on the part of the calibration curve, the error of which exceeds a preset standard, so as to generate interval calibration parameters.
Specifically, after the test device outputs the voltage, the output voltage can be sampled through sampling chips such as an ADC chip and the like inside the test device, and the sampled data is transmitted to the programmable logic controller under the control of the upper computer. Under the control of the upper computer, the programmable logic controller can calibrate the sampling data according to the method from step S202 to step S210, and obtain a corresponding calibration value. The upper computer can generate a calibration curve corresponding to the output voltage according to the calibration value, and can also acquire the actual value of the output voltage and generate an actual voltage curve. The actual value of the obtained output voltage can be obtained by measuring the output voltage through an external measuring instrument. Further, the upper computer can compare and analyze the calibration curve and the actual voltage curve by utilizing an algorithm, and divide the part of the calibration curve, which is beyond the preset range, into error sections independently by taking the actual voltage curve as a reference, and recalibrate the error sections to calculate the section calibration parameters of each error section. The interval calibration parameters may be stored in an upper computer for subsequent calibration of signals within the interval.
In the above embodiment, the upper computer selects a plurality of test values according to the measuring range of the test device, and can obtain the corresponding calibration value through the programmable logic controller, further obtain the calibration curve of the full-range, and find the part with overlarge error in the full-range calibration mode through comparing with the actual output curve. Therefore, the interval calibration parameters are calculated independently for the part with overlarge error in the output range of the test equipment, and the accuracy of the output signal of the test equipment is improved.
In one embodiment, the upper computer is further configured to set a start value and a step size according to an output range of the test device; selecting a starting value as a first test value, and sequentially increasing step sizes on the basis of the starting value to obtain the rest test values; the test value does not exceed the output range of the test device.
Specifically, the upper computer may also select a test value in the output range of the test device according to a specific program. For example, when selecting the test value of the output voltage, the minimum measurement range value may be set as a start value, and 0.5V may be set as a step length, and 0.5V may be sequentially increased based on the start value to continue obtaining the test value.
In order to further embody the beneficial effects of the present solution, the following describes the above calibration method with reference to a specific application scenario:
Taking a certain SMU power card for providing power for test equipment as an example, when the power board is loaded with an AD5522 type chip, 4 independent output channels (also called Force channels) can be provided, and each channel can output current from +/-5 μa to +/-80 mA levels. The AD5522 type chip outputs corresponding current through a specific parameter combination logic circuit, and the specific parameter combination logic circuit outputs the corresponding current in a mathematical expression mode and is recorded in a use manual of the chip. The upper computer sets the power board card as measurement current output, controls an ADC sampling chip in the power board card to sample the output current of each channel for preset times, and sends sampling data to a programmable logic controller connected with the ATE test equipment.
Fig. 4 is a block diagram of the execution of the calibration process after the programmable logic controller receives the above-described sample data. As shown in fig. 4:
step 301 represents the programmable logic controller acquiring sampling data of each channel by the ADC sampling chip.
Step 302 represents that after the programmable logic controller receives a specific Trigger command, preset parameters and instructions are automatically fetched from the FIFO (First In First Out) module. Wherein, trigger command can be sent out by the upper computer; the FIFO module is a storage module connected with the programmable logic controller; the parameters include calibration parameters of each channel and a logic output formula of each channel, wherein the logic output formula is a mathematical expression used for representing a logic output circuit of the channel and recorded in an application manual of an AD5522 chip.
Step 303 represents that the programmable logic controller respectively accumulates the sampled data of each channel, divides the accumulated sum by the sampling times, and uses the calculated sampling average value as effective data.
Step 304 represents that the programmable logic controller performs inverse operation processing on the sampling average value of each channel according to the logic output formula of each channel, so as to obtain a fixed point value of the output current of each channel, wherein the fixed point value unit of the output current is nanoampere.
Step 305 represents the programmable logic controller converting the unit of output current from nanoampere to ampere and converting the fixed point value to a single precision floating point value.
Step 306 represents the programmable logic controller calculating a current calibration value for each channel from the floating point value of the current according to a calibration algorithm.
In the above embodiment, each channel of the power panel card can be sampled at one time through the sampling chip inside the test equipment, and each channel is calibrated quickly by using the programmable logic controller, and the calibration process is realized through the internal circuit of the programmable device, so that the calibration speed is greatly accelerated.
In one embodiment, the process involving the division operation in steps 305 and 306 of fig. 4 may also be accomplished using a Remainder mode (remainders) of the divider IP core. Further, when the output current is in the low current range, the dividend is expanded by M times before the divider performs the division operation, the floating point value is further reduced by M times in step 306, and the reduced value is used for calculation of the calibration algorithm. Wherein M is a positive number.
In one embodiment, this embodiment takes a 32 channel SMU power measurement board as an example: when the DUT (Device Under Test, to-be-tested device) end of the DAC chip is externally connected with a 1G omega resistor and the Force (output) voltage is set to be 0.8V, the current value should be stabilized at 1nA theoretically, but the original value of the current acquired by the ADC chip is stabilized at about 0.229nA due to the accuracy limit of the chip. When this current value passes the calibration, the calibrated data becomes jumped between +0.545nA and-0.39 nA, i.e. there is a jump close to 1nA, since the accuracy is limited to 1nA before no accuracy improvement scheme is added. In this case, the accuracy of the current is improved by using the expansion and contraction methods, and the obtained current jumps between 1.146nA and 0.854nA, so that the accuracy is greatly improved as compared with the prior art.
In the above embodiment, the divider is used to process the sampled data, and the data processed by the divider is multiplied and reduced, so that the bit width of the divider is fully utilized, and the accuracy of current processing is improved.
FIG. 5 is a flow diagram of segment interval calibration of test equipment in one embodiment, including:
In step S401, each mode is calibrated once in the full range.
Wherein, each mode comprises a voltage mode and a current mode. The voltage mode and the current mode can be further subdivided into a plurality of sub-modes according to different gear positions.
Step S402, after calibration, obtaining calibration curves of all modes.
Step S403, analyzing the calibration curve, and performing interval calibration on the part with larger error.
Specifically, an actual value corresponding to the output signal can be obtained, an actual curve is formed, and a calibration curve is compared with the actual curve to obtain a part with larger error.
Step S404, the first interval calibration is started.
Step S405, setting a test value and controlling the test device to output a test signal.
Step S406, sampling the test signal and sending the obtained sampling data to the programmable logic controller.
Step S407, analyzing the sampling data to obtain information such as current, voltage, data range, channel number and the like.
Step S408, start calibration of the current interval calibration.
Step S409, the current interval calibration is ended.
Step S410, whether all the intervals in the full range are calibrated.
Step S411, start the next interval calibration.
Specifically, if the calibration is not finished, the process goes to step S405 to set the test value of the next section.
In step S412, the full-scale calibration is ended.
FIG. 6 is an effect diagram of performing a two-stage calibration according to the method shown in FIG. 5, in one embodiment. This embodiment also takes a 32 channel SMU power measurement board as an example: the voltage output range of the board card is-8V, if the error in the range is larger, the voltage output range of the board card is selected to be a first interval, and the voltage output range of the board card is selected to be a second interval. After the actual values of the three output voltages of-8V, 0V and 8V are respectively measured, the first interval and the second interval are calibrated according to a calibration algorithm.
After calibration, the calibration effect can be checked by the following checking method:
setting-8V as an initial value and 1V as a step length, selecting 17 test values in total, and obtaining corresponding calibration values after the calibration of a programmable logic controller; and then the actual value of the output voltage is measured by connecting the output voltage of each test value to an SMU (source measurement unit) instrument, and finally the effect diagram shown in fig. 6 is obtained. Wherein the line graph represents the error of the calibration value from the actual value.
FIG. 7 is an effect diagram of four-stage calibration according to the method shown in FIG. 5 in one embodiment. This embodiment also takes a 32 channel SMU power measurement board as an example: the voltage output range of the board card is-8V, if the error in the range is larger, the voltage output range is selected from-8V to-4V as a first interval, from-4V to 0V as a second interval, from 0V to 4V as a third interval, and from 4V to 8V as a third interval. And respectively measuring the actual values of five output voltages of-8V, -4V, 0V, 4V and 8V, and calibrating the four intervals according to a calibration algorithm.
After the calibration is completed, the calibration effect is checked by the checking mode, and finally, an effect diagram shown in fig. 7 is obtained.
In the above embodiment, as can be seen from the comparison of fig. 6 and fig. 7, the error of the calibration of the segment interval is smaller, the error is significantly improved, and the more segments, the more obvious the calibration effect, the more accurate the value.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
In one embodiment, as shown in fig. 8, a signal calibration system of a test device is provided, which can be applied to a programmable logic controller connected to the test device, the system comprising:
a data acquisition module 502, configured to acquire target sampling data; the target sampling data are obtained by sampling signals output by all target channels of the test equipment;
the channel analysis module 504 is configured to perform channel analysis on the target sampling data to obtain sampling data that is matched with each target channel;
the data conversion module 506 is configured to perform inverse operation processing on the measurement data based on the logic output circuit of each target channel, so as to obtain first restored data;
the precision conversion module 508 is configured to perform data precision conversion on the first restored data to obtain second restored data;
and the calibration module 510 is configured to calibrate the second recovery data according to a preset calibration algorithm, so as to obtain a calibration value.
For specific limitations of the above calibration system, reference may be made to the above limitations of the above calibration method, according to which the calibration system may add steps in implementing corresponding method embodiments of the first module, the second module, etc. The various modules in the calibration system described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
According to another aspect of the embodiments of the present disclosure, there is provided a computer device, which may be a terminal, and an internal structure diagram thereof may be as shown in fig. 9. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by the processor to implement the above-mentioned measuring method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by persons skilled in the art that the architecture shown in fig. 9 is merely a block diagram of some of the architecture relevant to the present inventive arrangements and is not limiting as to the computer device to which the present inventive arrangements are applicable, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In an embodiment, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.
According to another aspect of the disclosed embodiments, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
According to another aspect of the disclosed embodiments, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration, and not limitation, RAM can take many forms, such as static Random access memory (Static Random Access Memory, SRAM) or Dynamic Random access memory (Dynamic Random AccessMemory, DRAM), among others. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.
Claims (8)
1. A signal calibration method for a semiconductor test device, the method being applied to a programmable logic controller electrically connected to the test device, the programmable logic controller including a divider having a predetermined divisor stored therein, the calibration method comprising:
acquiring target sampling data; the target sampling data are obtained by sampling signals output by all target channels of the test equipment;
carrying out channel analysis on the target sampling data to obtain sampling data matched with each target channel;
performing inverse operation processing on the sampling data matched with each target channel based on the logic output circuit of each target channel to obtain first restored data;
expanding the first reduction data by a designated multiple to obtain expanded first reduction data;
inputting the expanded first reduction data into the divider as a dividend, and controlling the divider to divide the dividend and the divisor to obtain a quotient;
the quotient is reduced by the designated multiple and then is used as second reduction data;
and calibrating the second recovery data according to a preset calibration parameter to obtain a calibration value.
2. The calibration method according to claim 1, wherein the target sampling data is obtained by sampling a signal output by each target channel of the test device for a preset number of times, and the performing channel analysis on the target sampling data to obtain sampling data matched with each target channel includes:
carrying out channel analysis on the target sampling data to obtain initial sampling data of the preset times matched with each target channel;
and taking the average value of the initial sampling data of the preset times as sampling data matched with each target channel.
3. The method of claim 1, wherein the programmable logic controller is further electrically connected to a host computer, and the host computer is electrically connected to the test device; the upper computer is used for selecting a test value of a target number according to the output range of the test equipment; controlling the test equipment to sequentially output test signals of the test values;
the acquiring target sampling data includes:
acquiring sampling data corresponding to the test signals by using a programmable logic controller; the upper computer is further used for calibrating the sampling data according to the programmable logic controller to obtain calibration values of the target number, and generating a calibration curve; acquiring an actual signal value corresponding to the test signal, and generating an actual signal curve; comparing the calibration curve with the actual signal curve, and performing interval calibration on the part of the calibration curve, the error of which exceeds a preset standard, so as to generate interval calibration parameters.
4. A calibration method according to claim 3, wherein the host computer is further configured to set a start value and a step size according to an output range of the test device; selecting a starting value as a first test value, and sequentially increasing step sizes on the basis of the starting value to obtain the rest test values; the test value does not exceed the output range of the test device.
5. A signal calibration system for a semiconductor test apparatus, the system being applied to a programmable logic controller electrically connected to the test apparatus, the programmable logic controller including a divider storing a predetermined divisor, the calibration system comprising:
the data acquisition module is used for acquiring target sampling data; the target sampling data are obtained by sampling signals output by all target channels of the test equipment;
the channel analysis module is used for carrying out channel analysis on the target sampling data to obtain sampling data matched with each target channel;
the data conversion module is used for carrying out inverse operation processing on the sampling data matched with each target channel based on the logic output circuit of each target channel to obtain first restored data;
The precision conversion module is used for expanding the first restored data by a designated multiple to obtain expanded first restored data; the method is also used for inputting the expanded first reduction data into the divider as a dividend, controlling the divider to divide the dividend and the divisor to obtain a quotient, and reducing the quotient by the specified multiple to be used as second reduction data;
and the calibration module is used for calibrating the second recovery data according to preset calibration parameters to obtain a calibration value.
6. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 4 when the computer program is executed.
7. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
8. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the method of any of claims 1 to 4.
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