JP4776094B2 - Semiconductor test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test apparatus that can test an LCD driver at high speed.
[0002]
[Prior art]
The configuration and operation of an example of a conventional semiconductor test apparatus will be described with reference to FIGS.
As shown in FIG. 3, the main parts of the conventional semiconductor test apparatus are multiplexers 21, 22, ... 2n, digitizers 31, 32, ... 3n, serial / parallel converters 41, 42, ... .., 5n, memories 61, 62,... 6n, computer 10, control unit 70, and address counter 72.
Then, the semiconductor test apparatus executes a test program to test the DUT 90 that is a device under test.
However, the configuration of the semiconductor test apparatus for input pins other than the driver pins of the DUT 90 is omitted for the sake of simplicity of the drawings and description.
[0003]
The LCD driver as the DUT 90 has, for example, a 128-pin driver output, and each has 256 step voltage outputs.
[0004]
The multiplexers 21, 22,... 2n are selection output means for selecting and outputting one from a large number of inputs by a pin selection signal PSEL.
For example, when the driver output pin of the DUT 90 is 128 pins, 16 multiplexers (n = 16) of 8 channel selection inputs are used.
[0005]
The digitizers 31, 32,... 3n are analog-to-digital converters that receive the analog voltage output signals from the multiplexers 21, 22,. Is output.
For example, each of the digitizers 31, 32,..., 3n uses a 16-bit AD converter.
[0006]
The serial / parallel converters 41, 42,..., 4n are synchronized with a clock (not shown) from the digitizers 31, 32,. It is a means to convert into.
For example, the serial / parallel converters 41, 42,... 4n convert and output 1-bit serial data as 16-bit parallel signals.
[0007]
The flip-flops 51, 52,... 5n latch and output the multi-bit parallel data of the serial / parallel converters 41, 42,.
For example, 16-bit parallel data of the serial / parallel converters 41, 42,..., 4n are latched and output as 16-bit data.
[0008]
.., 6n store the p-bit output data of the flip-flops 51, 52,..., 5n at the address of the address signal from the address counter 72, respectively.
[0009]
The computer 10 is a calculation means that reads data in the memories 61, 62,... 6n via the bus 100 and performs calculation analysis processing.
[0010]
The control unit 70 outputs an initialization signal INIT, a pin selection signal PSEL, and a serial data end signal END.
[0011]
The address counter 72 clears the counter with the initialization signal INIT from the control unit 70, and outputs the address incremented with the end END signal of the serial data.
[0012]
Next, a gradation deviation test and a settling test, which are test items when testing the driver output pin of the LCD driver as the DUT 90, will be described.
FIG. 4 is an example of gradation deviation characteristics for eight output pins of the LCD driver, and FIG. 5 is an example of characteristics of the settling test.
[0013]
The gradation deviation test (pin increment test) tests whether the deviation of each output pin is within a predetermined voltage range with respect to the average voltage of each gradation of all output pins of the LCD driver.
For example, in a certain gradation, all driver output voltages are measured and the average voltage is calculated. If the average voltage is within a range of ± 10 mV, a pass is determined.
[0014]
In the settling test (step / increment test), a certain gradation is set in a certain pin of the LCD driver, and it is tested whether the output voltage of the LCD driver becomes a value as set within a specified time.
For example, a settling test is performed according to the following test procedure.
(1) Set the gradation.
(2) Wait for a specified time.
(3) Measure the output voltage of the LCD driver.
(4) Judgment is made based on whether or not the set value ± allowable value.
[0015]
Next, contents stored in the memories 61, 62,... 6n by the gradation deviation test and the settling test will be described.
[0016]
First, the case of the gradation deviation test of the LCD driver will be described.
In the gradation voltage step 1, the multiplexers 21, 22,... 2n shown in FIG. 3 select and output the first (1) to the eighth (8), respectively. ... 6n are stored as shown in the column of step 1 in FIG.
[0017]
In the gradation voltage step 2, the multiplexers 21, 22,... 2n shown in FIG. 3 select and output the first ((1)) to the eighth ((8)), respectively. 62,... 6n are stored as shown in the column of step 2 in FIG.
[0018]
Similarly, in the gradation voltage step m, when the multiplexers 21, 22,..., 2n shown in FIG. 3 select and output the first (1) to the eighth (8), respectively, the memory 61 , 62,... 6n are stored as shown in the column of step m in FIG.
[0019]
6n is stored in the memories 61, 62,... 6n shown in FIG. 6 as pre-processing performed by the computer 10 via the bus 100 shown in FIG. Steps 1 to 1 to 128 are arranged in the order of addresses, and are similarly rearranged in the order of addresses up to step m and stored in the memory of the computer 10 to facilitate calculation of the deviation test.
[0020]
Next, the case of the LCD driver settling test will be described.
When the multiplexers 21, 22,... 2n shown in FIG. 3 select and output the first ((1)), respectively, and increment output from step 1 to m of the gradation voltage, the memories 61, 62,. 6n is stored as shown in the column of MPX (1) in FIG.
[0021]
.., 2n shown in FIG. 3 selectively outputs the second ((2)), and increments the gradation voltage from step 1 to m. .. 6n is stored as shown in the column of MPX (2) in FIG.
[0022]
Similarly, in step m, the multiplexers 21, 22,... 2n shown in FIG. 3 select and output the eighth ((8)), respectively, and increment the gradation voltages from step 1 to m. 61n are stored as shown in the column of MPX {circle over (8)} in FIG.
[0023]
7n is stored in the memories 61, 62,... 6n shown in FIG. 7 as pre-processing performed by the computer 10 via the bus 100 shown in FIG. Step 1 of pins 1 to 128 is arranged in the order of addresses, and similarly arranged in order of addresses up to step m and stored in the memory of the computer 10 to facilitate the calculation of the settling test.
[0024]
That is, since the conventional semiconductor test apparatus stores the addresses in the memory addresses in the order of measurement, the address of the pin number and the storage address of the number of steps differ each time.
Therefore, as a pre-processing for the calculation of each test, the calculation processing is facilitated by rearranging the addresses at predetermined addresses corresponding to the pins and steps.
[0025]
[Problems to be solved by the invention]
As described above, the conventional semiconductor test apparatus rearranges in order of predetermined addresses as pre-processing for the calculation of each test to facilitate the calculation process.
Accordingly, the present invention has been made in view of these problems, and an object of the present invention is to provide a semiconductor test apparatus in which the calculation time is shortened by storing the data at a predetermined address in the memory without preprocessing of the calculation of each test. There is to do.
[0026]
[Means for Solving the Problems]
That is, the first of the present invention made to achieve the above object is
In semiconductor test equipment for testing LCD drivers,
A memory map is provided in which the address of the LCD driver output pin and the address for storing the data for each step voltage is provided in advance, and stored in the address of the corresponding address in the memory map regardless of the test data pin and step loading order. The gist of the featured semiconductor test equipment.
[0027]
The second aspect of the present invention made to achieve the above object is as follows.
A multiplexer that receives a plurality of driver outputs of the LCD driver and selectively outputs one by a pin selection signal;
N digitizers that receive the multiplexer output and convert it to digital data;
N serial-to-parallel converters for converting the digitizer serial output into a multi-bit parallel output;
N flip-flops which receive a multi-bit parallel output of the serial-parallel converter and latch-output with a serial data end signal;
In a semiconductor test apparatus for testing an LCD driver,
A multiplexer that receives an output of each of the plurality of n flip-flops and selectively outputs a plurality of bits of one flip-flop using a channel selection signal;
An address generator for receiving the channel selection signal and generating an address in synchronization with the pin selection signal;
A memory for receiving the address signal and storing a plurality of bits of the multiplexer;
The gist of the semiconductor test apparatus is characterized by comprising:
[0028]
DETAILED DESCRIPTION OF THE INVENTION
The configuration and operation of an example of the semiconductor test apparatus of the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 4, and FIG.
As shown in FIG. 1, the semiconductor test apparatus according to the present invention includes a computer 10, multiplexers 21, 22,... 2n, digitizers 31, 32,... 3n, and a serial / parallel converter 41. , 42,... 4n, flip-flops 51, 52,... 5n, a memory 60, a control unit 71, a multiplexer 20, and an address generation unit 73.
Then, the semiconductor test apparatus executes a test program to test the DUT 90 that is a device under test.
However, the configuration of the semiconductor test apparatus for the input pins other than the driver pins of the DUT 90 is omitted for the sake of simplicity of the drawings and description as in the description of the prior art.
[0029]
The LCD driver as the DUT 90 has, for example, an output pin of a driver of 128 channels and 8192 gradations.
[0030]
The multiplexers 21, 22, ... 2n, the digitizers 31, 32, ... 3n, the serial / parallel converters 41, 42, ... 4n, and the flip-flops 51, 52, ... 5n are conventional. Since it is the same as the technical component, description is abbreviate | omitted.
[0031]
The multiplexer 20 receives the n-channel p-bit output of the flip-flops 51, 52,... 5n, and receives one channel in response to the channel selection signal CHSEL (0, 1, 2,... (N−1)). The p bits of are selectively output.
[0032]
The memory 60 stores the p-bit output data of the multiplexer 20 at the address of the address by the address signal from the address generator 73, respectively.
[0033]
The computer 10 is an arithmetic unit that reads out data in the memory 60 via the bus 100 and performs arithmetic analysis processing.
[0034]
The control unit 71 outputs an initialization signal INIT, a pin selection signal PSEL, a serial data end signal END, and a channel selection signal CHSEL.
[0035]
The address generation unit 73 generates an address synchronized with the pin selection signal and the channel selection signal by the initialization signal INIT from the control unit 71, the pin selection signal PSEL, the serial data end signal END, and the channel selection signal CHSEL. To do.
[0036]
For example, as shown in FIG. 2, when the driver output of the DUT 90 is 128 pins and the maximum step of the gradation voltage is m, the gradation voltage step 1 from the 1-pin data to the 128-pin data, then the gradation voltage From the 1st pin data of step 2 to the 128th pin data, similarly, from the 1st pin data of the gradation voltage step m to the 128th pin data are stored in the order of addresses.
That is, addresses to be stored corresponding to device pins and gradation voltage steps are determined in advance as a memory map.
Therefore, the same address is generated from the address generation unit 73 for the same step as the same pin even if the data output order of the test output pin and the test step is different.
[0037]
Next, an example of storing in the memory 60 by the gradation deviation test and the settling test will be described.
[0038]
Since the definition of the gradation deviation test (pin increment test) and the settling test (step increment test) has been described in the related art, description thereof will be omitted.
[0039]
First, the case of the gradation deviation test of the LCD driver will be described.
In the gradation voltage step 1, the multiplexers 21, 22,..., 2n shown in FIG. As shown in FIG. 2, the memory 60 selects Step 1 (1-1) of Pin 1, Step 1 of Pin 9,... Step 1 (121-1 of Pin 121), as shown in FIG. ) Are sequentially stored at the addresses of the corresponding addresses.
[0040]
Then, in step 1 of the gradation voltage, each of the multiplexers 21, 22,... 2n shown in FIG. 1 selects and outputs the second ((2)), and the multiplexer 20 outputs from the flip-flop 51 to the flip-flop 5n. When the p-bit output is selected and output, the memory 60, as shown in FIG. 2, the step 1 (2-1) of the pin 2, the step 1 (10-1) of the pin 10,. It is stored in the address of each corresponding address in step 1 (122-1).
[0041]
Similarly, in step 1 of the gradation voltage, each of the multiplexers 21, 22,... 2n shown in FIG. 1 selects and outputs the eighth ((8)), and the multiplexer 20 switches from the flip-flop 51 to the flip-flop 5n. In the case of selectively outputting the p-bit output up to the above, the memory 60, as shown in FIG. 2, the step 1 (8-1) of the pin 8, the step 1 (16-1) of the pin 16,. It is stored in the address of each corresponding address in step 1 (128-1) of the pin.
[0042]
As described above, the p-bit data from pin 1 to pin 128 in step 1 of the gradation deviation test is stored in the memory 60 in the order of addresses.
Similarly, each data from step 2 to step m is stored at an address of a predetermined address as a memory map as shown in FIG.
[0043]
Next, the case of the LCD driver settling test will be described.
1, each of the multiplexers 21, 22,... 2n selects the first (1) and increments the gradation voltage from step 1 to m, and the multiplexer 20 selects and outputs the flip-flop 51. As shown in FIG. 2, the memory 60 stores data up to step 1 of pin 1, step 2 of pin 1,.
[0044]
Then, the multiplexers 21, 22,... 2n shown in FIG. 1 respectively select the first (1) and increment the gradation voltage from step 1 to m, and the multiplexer 20 causes the flip-flop 52 to be output. As shown in FIG. 2, the memory 60 stores the data up to step 1 of pin 9, step 2 of pin 9,.
[0045]
Similarly, each of the multiplexers 21, 22,... 2n shown in FIG. 1 selects the first (1) and increments the gradation voltage from step 1 to m, so that the multiplexer 20 is a flip-flop. As shown in FIG. 2, the memory 60 stores data up to step 1 of the pin 121, step 2 of the pin 121,..., Step m of the pin 121.
[0046]
Similarly, the multiplexers 21, 22,... 2n shown in FIG. 1 perform the operation of selecting the second ((2)) to the eighth ((8)) in the same manner as described above. As shown, in the memory map of the memory 60, it is stored at the address of a predetermined pin and step address.
[0047]
In other words, since the semiconductor test apparatus of the present invention stores directly at the address of the predetermined memory map, the address of the storage address of the memory corresponding to the pin number and the number of steps is the same regardless of the test item fetching order. Thus, the same effect as that of a pseudo-independent digitizer (per-pin digitizer) is provided for each driver output pin.
Therefore, when performing arithmetic processing for each test, pre-processing for rearranging in order of predetermined addresses becomes unnecessary, and the arithmetic processing time can be shortened.
[0048]
【The invention's effect】
The present invention is implemented in the form as described above, and has the following effects.
That is, since the semiconductor test apparatus of the present invention directly stores in the memory at the address of the predetermined memory map, the storage address corresponding to the pin number and the number of steps is the same regardless of the test item loading order.
Therefore, when performing arithmetic processing for each test, preprocessing for rearranging in the order of a predetermined address is unnecessary, and there is an effect that the arithmetic processing time can be shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor test apparatus of the present invention.
FIG. 2 is a memory map of the semiconductor test apparatus of the present invention.
FIG. 3 is a block diagram of a conventional semiconductor test apparatus.
FIG. 4 is a data diagram of a gradation deviation test of the LCD driver.
FIG. 5 is a data diagram of an LCD driver settling test.
FIG. 6 is a memory storage diagram of a deviation test of a conventional semiconductor test apparatus.
FIG. 7 is a memory storage diagram of a settling test of a conventional semiconductor test apparatus.
[Explanation of symbols]
10 Computer 20 Multiplexer 21, 22, ... 2n Multiplexer 31, 32, ... 3n Digitizer 41, 42, ... 4n Serial / parallel converter 51, 52, ... 5n Flip-flop 60 Memory 61, 62 , ... 6n Memory 70, 71 Controller 72 Address counter 73 Address generator 90 DUT
100 buses

Claims (2)

A multiplexer that receives a plurality of driver outputs of the LCD driver and selectively outputs one by a pin selection signal;
N digitizers which receive the output of the multiplexer and convert it into digital data;
N serial-to-parallel converters for converting the digitizer serial output into a multi-bit parallel output;
N flip-flops which receive a multi-bit parallel output of the serial-parallel converter and latch-output with a serial data end signal;
A controller for outputting an initialization signal, the pin selection signal, a serial data end signal, and a channel selection signal;
In a semiconductor test apparatus for testing an LCD driver,
A multiplexer for the n receiving the output of each multiple-bit flip-flop, selectively outputs a plurality of bits of one flip-flop in the channel selection signal,
An address generator that receives the initialization signal, the pin selection signal, the end signal of the serial data, and the channel selection signal, and generates an address in synchronization with the pin selection signal and the channel selection signal ;
A memory for receiving the address signal and storing a plurality of bits of the multiplexer;
The address generation unit is a semiconductor test apparatus that generates the same address for the same step of the same test output pin regardless of the data acquisition order of the step of the gradation voltage to be tested with the test output pin.   A gradation deviation test that measures the driver output of all the test output pins of the LCD driver for each gradation voltage step, and a settling test that measures the driver output while incrementing the gradation voltage step for each test output pin The address generator generates the same address for the same step of the same test output pin regardless of the data acquisition order of the test output pin and the step of the gradation voltage to be tested. Semiconductor test equipment.

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