JP2002350510A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus which stores data in a predetermined address of a memory without preprocessing of calculating each test to shorten a calculating time. SOLUTION: The semiconductor testing apparatus for testing an LCD driver comprises a memory map for previously designating an address for storing the data at each output pin and step voltage of the LCD driver to store the data in the address corresponding to the memory map irrespective of the capturing order of the pins and the steps of the test data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test apparatus capable of testing an LCD driver at high speed.

[0002]

2. Description of the Related Art The configuration and operation of an example of a conventional semiconductor test apparatus will be described with reference to FIGS. As shown in FIG. 3, the main parts of the conventional semiconductor test apparatus include multiplexers 21, 22,... 2n, digitizers 31, 32,... 3n, and serial / parallel converters 41, 42,. 4n and flip-flop 5
, 5n and memories 61, 62,.
n, the computer 10, the control unit 70, and the address counter 72. Then, the semiconductor test apparatus executes the test program to execute the device under test D
Test UT90. However, the configuration of the semiconductor test apparatus for input pins other than the driver pins of the DUT 90 is omitted for simplicity of the drawings and description.

The LCD driver as the DUT 90 has, for example, a driver output of 128 pins, and each of the drivers has 25 pins.
There are six gradation step voltage outputs.

[0004] Multiplexers 21, 22, ... 2n
Is a selection output means for selecting and outputting one of many inputs by a pin selection signal PSEL. For example, DUT
When 90 driver output pins are 128 pins, 16 select-input multiplexers of 8 channels (n = 16)
use.

The digitizers 31, 32,... 3n are analog-to-digital conversion means for receiving the analog voltage output signals of the multiplexers 21, 22,. Outputs the clock of the signal. For example, digitizers 31, 32,.
n uses a 16-bit AD converter.

The serial / parallel converters 41, 42,.
.. 4n are means for converting 1-bit serial signals into p-bit parallel signals in synchronization with clocks (not shown) from digitizers 31, 32,. For example, a serial / parallel converter 4
, 4n convert and output 1-bit serial data as 16-bit parallel signals.

The flip-flops 51, 52,... 5n
Are serial-parallel converters 41, 42,... 4n
Are latched and output at the same timing of the serial data end signal END. For example, serial / parallel converters 41, 42,.
.. 4n 16-bit parallel data is latched and output as 16-bit data.

The memories 61, 62,..., 6n store the p-bit output data of the flip-flops 51, 52,.

The computer 10 has memories 61, 62,
... Reading out 6n data via the bus 100,
This is an arithmetic means for performing arithmetic analysis processing.

The control unit 70 includes an initialization signal INIT, a pin selection signal PSEL, and a serial data end signal EN.
D is output.

The address counter 72 clears the counter by the initialization signal INIT from the control unit 70 and outputs an address incremented by the end END signal of the serial data.

Next, a description will be given of a gradation deviation test and a settling test, which are test items when testing a driver output pin of an LCD driver as the DUT 90. FIG. 4 is an example of gradation deviation characteristics for eight output pins of the LCD driver, and FIG. 5 is an example of characteristics of a settling test.

The gradation deviation test (pin increment test) tests whether the deviation of each output pin is within a predetermined voltage range with respect to the average voltage of each gradation of all output pins of the LCD driver. For example, in a certain gradation, all driver output voltages are measured, an average voltage is calculated, and if the average voltage is within a range of ± 10 mV, a pass is determined.

In the settling test (step increment test), a certain gradation is set to a certain pin of the LCD driver, and it is checked whether the output voltage of the LCD driver has reached a set value within a specified time. test. For example, a settling test is performed according to the following test procedure. (1) Set the gradation. (2) Wait for the specified time. (3) Measure the output voltage of the LCD driver. (4) It is determined whether or not the set value is within the allowable range.

Next, the contents stored in the memories 61, 62,... 6n by the gradation deviation test and the settling test will be described.

First, the case of the gradation deviation test of the LCD driver will be described. In step 1 of the gradation voltage, the multiplexers 21, 22,... 2n shown in FIG.
, 6n, when the first () through the eighth () are selected and output, respectively, the memories 61, 62,.
It is stored as shown in the column of step 1 of (a).

Then, in step 2 of the gradation voltage,
2n shown in FIG.
When the first () to eighth () are selected and output, the memories 61, 62,..., 6n are stored as shown in the column of step 2 in FIG.

Similarly, in the step m of the gradation voltage,
2n shown in FIG.
.. 6n are stored as shown in the column of step m in FIG. 6 (a).

The memories 61, 62,... Shown in FIG.
.. The data stored in 6n is stored in the bus 100 shown in FIG.
As shown in FIG. 6 (b), step 1 of pins 1 to 128 is arranged in order of address as shown in FIG. To facilitate the calculation of the deviation test.

Next, the case of the settling test of the LCD driver will be described. Multiplexer 2 shown in FIG.
, 2n respectively select and output the first (), and when the gradation voltages are incremented from step 1 to step m, the memories 61, 62,. Is stored as shown in the column of MPX.

The multiplexer 21 shown in FIG.
, 2n respectively select and output the second (), and when the gradation voltages are incremented from step 1 to m, the memories 61, 62,.
It is stored as shown in the column of MPX in (a).

Similarly, in step m, the multiplexers 21, 22,... 2n shown in FIG.
(M) is selected and output, and steps 1 to m
When the output is incremented up to, the memories 61, 62,
.. 6n are stored as shown in the column of MPX in FIG.

The memories 61, 62,... Shown in FIG.
.. The data stored in 6n is stored in the bus 100 shown in FIG.
As shown in FIG. 7B, step 1 of pins 1 to 128 is arranged in the order of addresses as shown in FIG. To facilitate the calculation of the settling test.

In other words, the conventional semiconductor test apparatus stores the addresses of the memory in the order of measurement in the order of measurement, so that the pin number and the address of the storage address of the step number are different each time. For this reason, as pre-processing for the operation of each test, the data is rearranged into addresses of predetermined addresses corresponding to the pins and the steps, so that the arithmetic processing is facilitated.

[0025]

As described above, the conventional semiconductor test apparatus rearranges the order of predetermined addresses as a pre-processing for the operation of each test to facilitate the arithmetic processing. Accordingly, the present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor test apparatus in which a calculation time is shortened by storing data in a predetermined address of a memory without preprocessing for calculation of each test. Is to do.

[0026]

That is, a first aspect of the present invention, which has been made to achieve the above object, is to store data for each output pin of an LCD driver and a step voltage in a semiconductor test apparatus for testing an LCD driver. A gist of the present invention is a semiconductor test apparatus characterized by providing a memory map in which addresses are specified in advance, and storing the addresses in the addresses of the corresponding addresses in the memory map irrespective of the order of taking in the pins and steps of the test data.

A second aspect of the present invention to achieve the above object is a multiplexer that receives a plurality of driver outputs of an LCD driver and selects and outputs one according to a pin selection signal, and a multiplexer that receives the multiplexer output. N digitizers for converting to digital data, n serial-to-parallel converters for converting the serial output of the digitizer to a multi-bit parallel output, and receiving the multi-bit parallel output of the serial-to-parallel converter A semiconductor test apparatus for testing an LCD driver by providing an n number of flip-flops that latch and output a serial data end signal. A multiplexer for selecting and outputting a plurality of bits of one flip-flop; An address generation unit that receives a selection signal and generates an address in synchronization with the pin selection signal, and a memory that receives the address signal and stores a plurality of bits of output of the multiplexer. The gist is a semiconductor test device.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of an example of a semiconductor test apparatus according to the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 4, and FIG. As shown in FIG. 1, the essential parts of the semiconductor test apparatus of the present invention include a computer 10, multiplexers 21, 22,... 2n, digitizers 31,
2, 3n and serial / parallel converters 41, 4
2, 4n and flip-flops 51, 52,.
5n, a memory 60, a control unit 71, a multiplexer 20, and an address generation unit 73. Then, the semiconductor test apparatus executes the test program to test the DUT 90 as the device under test. However, DUT
The configuration of the semiconductor test apparatus for input pins other than the 90 driver pins is omitted for the sake of simplicity of the drawing and the description, similarly to the description of the prior art.

The LCD driver as the DUT 90 has, for example, an output pin of a driver of 128 channels and 8192 gradations.

Multiplexers 21, 22,... 2n
, Digitizers 31, 32,.
The parallel converters 41, 42,... 4n and the flip-flops 51, 52,.

The multiplexer 20 receives the n-channel p-bit outputs of the flip-flops 51, 52,... 5n, and receives the channel selection signals CHSEL (0, 1,.
, (N-1)), and selectively outputs p bits of one channel.

The memory 60 stores the p-bit output data of the multiplexer 20 at the address of the address according to the address signal from the address generator 73.

The computer 10 is an arithmetic means for reading data from the memory 60 via the bus 100 and performing arithmetic analysis processing.

The control unit 71 includes an initialization signal INIT, a pin selection signal PSEL, and a serial data end signal EN.
D and a channel selection signal CHSEL.

The address generator 73 includes an initialization signal INIT from the controller 71, a pin selection signal PSEL, a serial data end signal END, and a channel selection signal C.
The HSEL generates an address synchronized with the pin selection signal and the channel selection signal.

For example, as shown in FIG. 2, when the driver output of the DUT 90 is 128 pins and the maximum step of the gradation voltage is m, the 1st pin data of the gradation voltage step 1 is converted to the 128 pin data, The 1st pin data to the 128th pin data of step 2 of the adjustment voltage and the 1st pin data to the 128th pin data of the step m of the gradation voltage are stored in the order of addresses. That is, the addresses to be stored corresponding to the device pins and the steps of the gradation voltage are determined in advance as a memory map. Therefore, the same address is generated from the address generation unit 73 for the same pin and the same step, even if the test output pin and the data acquisition order of the test step are different.

Next, an example in which data is stored in the memory 60 by a gradation deviation test and a settling test will be described.

The definitions of the gradation deviation test (pin increment test) and the settling test (step increment test) have already been described in the prior art, and therefore the description is omitted.

First, the case of the gradation deviation test of the LCD driver will be described. In step 1 of the gradation voltage, the multiplexers 21, 22,... 2n shown in FIG.
Respectively select and output the first (), and the multiplexer 20 outputs the flip-flop 51 to the flip-flop 5.
When sequentially selecting and outputting p-bit outputs up to n, the memory 60, as shown in FIG.
-1), step 1 of pin 9,..., Are sequentially stored at the addresses of the corresponding addresses in step 1 (121-1) of pin 121.

Then, in step 1 of the gradation voltage,
The multiplexers 21, 22,... 2n shown in FIG.
The second () is selected and output, and multiplexer 2 is output.
0 selects and outputs a p-bit output from the flip-flop 51 to the flip-flop 5n.
As shown in FIG. 2, step 1 (2-
1), step 1 (10-1) of pin 10,... Are stored in the addresses of the corresponding addresses of step 1 (122-1) of pin 122.

Similarly, in step 1 of the gradation voltage, the multiplexers 21, 22,... 2n shown in FIG.
Respectively select and output the eighth (), and the multiplexer 20 outputs the flip-flop 51 to the flip-flop 5.
When selecting and outputting p-bit outputs up to n, the memory 6
0 indicates the step 1 (8-) of the pin 8 as shown in FIG.
1), step 1 (16-1) of pin 16,... Are stored at the addresses of the corresponding addresses of step 1 (128-1) of pin 128.

As described above, the p-bit data of the pins 1 to 128 in the step 1 of the gradation deviation test is stored in the memory 60 in the order of the addresses. Similarly, as shown in FIG. 2, each data from step 2 to step m is stored at an address of a predetermined address as a memory map.

Next, the case of the settling test of the LCD driver will be described. Multiplexer 2 shown in FIG.
.., 2n select the first () and increment and output the gradation voltage from step 1 to m.
, And the memory 60 stores data up to the step 1 of the pin 1, the step 2 of the pin 1,..., The step m of the pin 1, as shown in FIG.

The multiplexer 21 shown in FIG.
22,... 2n each select the first (),
The gradation voltage is incremented from step 1 to step m, the multiplexer 20 selects and outputs the flip-flop 52, and the memory 60 stores the step 1 of the pin 9 and the step 2 of the pin 9 as shown in FIG. -Store data up to step m of pin 9.

Similarly, the multiplexer 2 shown in FIG.
, 2n select the first () and increment and output the gradation voltage from step 1 to m, and the multiplexer 20 outputs the flip-flop 5n.
, And the memory 60 stores the step 1 of the pin 121, the step 2 of the pin 121,... As shown in FIG.
Data is stored up to the step m of the pin 121.

Similarly, the multiplexer 2 shown in FIG.
1, 22,... 2n are the second () to 8 respectively.
The operation of selecting the (th) is performed in the same manner as described above, and is stored in the memory map of the memory 60 at the address of a predetermined pin and step address as shown in FIG.

In other words, the semiconductor test apparatus of the present invention stores data directly in the address of a predetermined memory map, so that the storage address of the memory corresponding to the pin number and the number of steps is irrespective of the order in which test items are fetched. The addresses are the same, which is the same effect as providing an independent digitizer for each driver output pin in a pseudo manner (per pin digitizer). Therefore, when performing the arithmetic processing of each test, the preprocessing for rearranging the addresses in a predetermined order is unnecessary, and the arithmetic processing time can be reduced.

[0048]

The present invention is embodied in the form described above and has the following effects. That is,
In the semiconductor test apparatus of the present invention, since the data is directly stored in the memory at a predetermined address of the memory map, the storage address corresponding to the pin number and the number of steps is the same regardless of the order in which the test items are fetched. Therefore, when performing the arithmetic processing of each test, there is no need to perform the pre-processing of rearranging the addresses in a predetermined order, and thus there is an effect that the arithmetic processing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor test apparatus according to the present invention.

FIG. 2 is a diagram of a memory map of the semiconductor test device of the present invention.

FIG. 3 is a block diagram of a conventional semiconductor test apparatus.

FIG. 4 is a data diagram of a gradation deviation test of an LCD driver.

FIG. 5 is a data diagram of a settling test of an LCD driver.

FIG. 6 is a memory storage diagram of a deviation test of a conventional semiconductor test apparatus.

FIG. 7 is a memory storage diagram of a settling test of a conventional semiconductor test apparatus.

[Explanation of symbols]

 10 Computer 20 Multiplexers 21, 22, ... 2n Multiplexers 31, 32, ... 3n Digitizers 41, 42, ... 4n Serial / parallel converters 51, 52, ... 5n Flip-flops 60 Memory 61, 62 6n memories 70, 71 control unit 72 address counter 73 address generation unit 90 DUT 100 bus

Claims (2)

[Claims] 1. A test data storage address specifying method in a semiconductor test apparatus for testing an LCD driver, wherein an address of a memory for storing test data is determined by an output pin number and a step voltage number of the LCD driver. 2. A multiplexer that receives a plurality of driver outputs of an LCD driver and selects and outputs one according to a pin selection signal; n digitizers that receive the multiplexer output and convert the digital data into digital data; and a serial output of the digitizer. N serial-to-parallel converters for converting the data into a parallel output of a plurality of bits, n flip-flops for receiving the parallel output of the plurality of bits of the serial-parallel converter and latching and outputting the serial data end signal, A multiplexer for receiving an output of each of the plurality of bits of the n flip-flops and selecting and outputting a plurality of bits of one flip-flop by a channel selection signal; Receiving the selection signal, the address is synchronized with the pin selection signal. And a memory for receiving the address signal and storing a plurality of bits of the output of the multiplexer.