CN116755010A - Digital I/O channel calibration method for semiconductor test equipment - Google Patents
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Abstract
The application discloses a digital I/O channel calibration method of semiconductor test equipment, which comprises the following steps: s1, grouping digital I/O channels of semiconductor test equipment into a group according to at least 3, and then testing and solving signal transceiving delay among the digital I/O channels in each group by using a first calibration board; s2, regrouping the digital I/O channels in a staggered '1' mode, and then testing and solving signal receiving and transmitting delay among the digital I/O channels in each regrouped packet by utilizing a second calibration board; s3, constructing and solving a delay calculation expression of each digital I/O channel in the transmitting direction and the receiving direction respectively; s4, performing delay compensation on the corresponding digital I/O channels by taking the delay value obtained in the step S3 as a compensation basis, thereby realizing the calibration alignment of the digital I/O channels. The application solves the problem of signal asynchronism between digital I/O channels of test equipment on the premise of not increasing the design difficulty and the manufacturing cost of the calibration plate.
Description
Technical Field
The application relates to the technical field of I/O channel calibration, in particular to a digital I/O channel calibration method of semiconductor test equipment.
Background
In the field of semiconductor testing, aiming at digital chips such as an ASIC (Application Specific Integrated Circuit, special application integrated circuit, i.e. a special chip), a memory chip and the like, test equipment is connected to a tested pin of the chip by providing a digital I/O channel and gives an excitation signal meeting the time sequence requirement or receives a signal from the tested chip, so that the purposes of testing the functions, the time sequence parameters and the like of the chip are achieved. The digital I/O channels provided by the test equipment are generally more, and the delay of signals sent to the tested chip from the I/O channels or the delay of signals received from the tested chip are required to be equal or have a fixed difference in the test process, so that the receiving and sending of test signals can be synchronous, and particularly for the test of parallel interfaces, for example, when testing DDR chips, the time sequence requirements between the signals can be accurately controlled. Therefore, in order to achieve equal or fixed delay between the I/O channels, the I/O channels need to be calibrated before the test equipment leaves the factory, the delay of the signals sent from the I/O channels to the tested chip or the delay of the signals received from the tested chip is measured and compensated into the delay circuit of the signal sending or receiving, so as to achieve the synchronization of signal sending and receiving between the channels.
In the conventional general I/O channel calibration method, as shown in fig. 1, a calibration board 1 is designed to measure signal delay in a transmission direction of a digital I/O channel, and a TDC (Time-to-Digital Converter, i.e., a Time-to-digital converter, which is a commonly used Time interval measurement electronic circuit, and a commonly used high-precision Time measurement chip has a TDC-GP2, etc.) chip is used on the calibration board 1 to test signal delay between different I/O channels (the numbers "1" and "2" in fig. 1 respectively represent the I/O channels 1 and 2 on a test device). The calibration board 2 is used for measuring signal delay in the receiving direction of the digital I/O channel, a synchronous signal Generator is adopted on the calibration board 2 to send out synchronous signals with phase alignment, and a TG (Timing Generator, generally implemented by an FPGA chip) measures the signal delay in the receiving direction. Finally, delay compensation is performed according to the measured signal delay in the two directions of transmission and reception between the I/O channels, so that the signals are synchronous.
However, the existing I/O channel calibration method has the following two technical problems:
1. the calibration plate is complex in design, the number of TDC and synchronization signal generators on the calibration plate is limited, and the number of channels on a single TDC chip and synchronization signal generator is also limited, typically 4, 8 or 16. Therefore, in the case of a large number of I/O channels, a larger number of TDC chips and synchronization signal generators need to be arranged on the calibration board, increasing the design difficulty and manufacturing cost of the calibration board.
2. Signal synchronization is also required between a plurality of TDC chips or between a plurality of synchronous signal generators on the calibration plate, the synchronization needs a uniform reference source REF_CLK, one or more stages of synchronous signal generators are added to the TDC chips for measuring delay or the generators for generating synchronous signals, and although the synchronism between signals generated by each synchronous signal generator is higher, a certain synchronous error exists, and the error is amplified through multistage accumulation, so that the calibration precision of the calibration plate is affected.
Disclosure of Invention
The application provides a digital I/O channel calibration method of semiconductor test equipment, which aims to solve the problem of signal dyssynchrony between I/O channels of the test equipment on the premise of not increasing the design difficulty and the manufacturing cost of a calibration board.
To achieve the purpose, the application adopts the following technical scheme:
there is provided a digital I/O channel calibration method for a semiconductor test apparatus, comprising the steps of:
s1, grouping digital I/O channels of semiconductor test equipment into a group according to at least 3, and then testing and solving signal receiving and transmitting delay among the digital I/O channels in each group by using a first calibration board;
s2, regrouping the digital I/O channels in a staggered mode of '1' so as to establish a delay calculation relation between groups obtained in the step S1, and then testing and solving signal receiving and transmitting delay between the digital I/O channels in each regrouped group by using a second calibration board;
s3, designating the signal delay of any digital I/O channel in the transmitting direction or the receiving direction as a common variable of a delay calculation expression, constructing the delay calculation expression of each digital I/O channel in the transmitting direction and the receiving direction respectively, and solving;
s4, performing delay compensation on the corresponding digital I/O channels by taking the delay value obtained in the step S3 as a compensation basis, thereby realizing calibration alignment of the digital I/O channels.
In step S1, as a preferred embodiment of the present application, the number of digital I/O channels on the test device are divided into a plurality of groups by grouping 3.
As a preferred embodiment of the present application, the wiring length of each of the digital I/O channels in each group divided in step S1 is the same between the semiconductor test apparatus and the first calibration board.
As a preferred embodiment of the present application, a method of testing and solving a signal transceiving delay between the digital I/O channels within each packet using the first calibration board or the second calibration board is expressed by the following formula (1):
D trij =ti+rj+2m equation (1)
In the formula (1), D trij Representing the signal reception delay between a digital I/O channel I and a digital I/O channel j within the same packet;
ti represents the delay of the digital I/O channel I in the signal transmission direction;
rj represents the delay of the digital I/O channel j in the signal receiving direction;
m is the delay of the test signal from the connector to the PCB wiring connection point on the first calibration board or the second calibration board.
As a preferred embodiment of the present application, in step S2, the method for regrouping the groups obtained in step S1 in an error "1" manner is as follows:
s21, sequencing each group obtained in the step S1;
s22, after finishing grouping sequencing, sequencing each digital I/O channel in each group to form a sequence arranged in sequence;
s23, starting from the second digital I/O channel in the sequence, and re-dividing the digital I/O channels of the semiconductor test equipment into a plurality of groups.
As a preferred embodiment of the present application, in step S23, the digital I/O channels of the semiconductor test apparatus are re-divided into several groups in the same grouping unit as step S1 starting from the digital I/O channel of the second in the sequence.
As a preferred embodiment of the present application, in step S2, the wiring length of each of the digital I/O channels in each group divided in an error "1" manner is the same between the semiconductor test apparatus and the second calibration board.
In a preferred embodiment of the present application, in step S2, 3 digital I/O channels on the test device are regrouped into a group.
As a preferred aspect of the present application, the wiring length of the digital I/O channel between the semiconductor test apparatus and the first calibration board includes a wiring length from an I/O interface of the semiconductor test apparatus to a connector and a wiring length from the connector to a PCB wiring connection point on the first calibration board;
the length of the wiring from each I/O interface to the connector is the same and the length of each wiring led out from the connector and connected to the PCB wiring connection point of the first calibration board is the same.
As a preferred aspect of the present application, the wiring length of the digital I/O channel between the semiconductor test apparatus and the second calibration board includes a wiring length from an I/O interface of the semiconductor test apparatus to a connector and a wiring length from the connector to a PCB wiring connection point on the second calibration board;
the length of the wiring from each I/O interface to the connector is the same and the length of each wiring led out from the connector and connected to the PCB wiring connection point of the second calibration board is the same.
The digital I/O channel calibration method of the semiconductor test equipment provided by the application is simple, solves the problem of signal dyssynchrony between the digital I/O channels of the test equipment on the premise of not additionally increasing the design difficulty and the manufacturing cost of the calibration board, and has accurate and reliable calibration result.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below. It is evident that the drawings described below are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a prior art method of calibrating a digital I/O channel;
FIG. 2 is a diagram showing steps for implementing a digital I/O channel calibration method for a semiconductor test apparatus according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a method for testing signal transceiver delays between digital I/O channels in a group and between digital I/O channels in different groups using two calibration boards according to the present application;
FIG. 4 is a schematic diagram of a method for testing signal transmission and reception delays between digital I/O channels in a group.
Detailed Description
The technical scheme of the application is further described below by the specific embodiments with reference to the accompanying drawings.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to be limiting of the present patent; for the purpose of better illustrating embodiments of the application, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the application correspond to the same or similar components; in the description of the present application, it should be understood that, if the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, only for convenience in describing the present application and simplifying the description, rather than indicating or implying that the apparatus or elements being referred to must have a specific orientation, be constructed and operated in a specific orientation, so that the terms describing the positional relationships in the drawings are merely for exemplary illustration and should not be construed as limiting the present patent, and that the specific meaning of the terms described above may be understood by those of ordinary skill in the art according to specific circumstances.
In the description of the present application, unless explicitly stated and limited otherwise, the term "coupled" or the like should be interpreted broadly, as it may be fixedly coupled, detachably coupled, or integrally formed, as indicating the relationship of components; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between the two parts or interaction relationship between the two parts. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
The implementation principle of the digital I/O channel calibration method of the semiconductor test equipment provided by the embodiment of the application is as follows: grouping digital I/O channels of a semiconductor test apparatus (hereinafter referred to as test apparatus) into a group of at least 3 (preferably 3), and designing two calibration boards (i.e., calibration board 1 and calibration board 2 in fig. 3) for testing the delay of the digital I/O channels, wherein the calibration board 1 is used for testing the signal transceiving delay (delay between signal transmission and signal reception) between the digital I/O channels in each group; the calibration board 2 is used to test the signal transceiving delay between the digital I/O channels of different packets. And then, calculating the signal receiving and transmitting delay between the digital I/O channels measured by the two calibration boards to obtain the delay values of all the digital I/O channels of the test equipment in the signal transmitting direction and the signal receiving direction. Finally, the calculated delay value is used as compensation basis to carry out delay compensation on the receiving and transmitting signals of each digital I/O channel, thereby achieving the aim of calibrating and aligning the digital I/O channels.
Specifically, as shown in fig. 2, the digital I/O channel calibration method of the semiconductor test device provided in the embodiment of the present application includes:
step S1, grouping the digital I/O channels of the semiconductor test equipment (namely the bidirectional IO channel test resource board shown in the figure 3) into a group according to at least 3, and then testing and solving signal transceiving delay among the digital I/O channels in each group by using a first calibration board;
grouping the digital I/O channels in at least 3 units is used for facilitating the subsequent steps of solving and calculating the time delay of the digital I/O channels in the signal transmitting direction and the signal receiving direction; as a preferred grouping, all digital I/O channels of the test equipment are grouped into groups of 3. The 3 digital I/O channels in each group are interconnected together, for example, the 3 digital I/O channels, namely, channel 1, channel 2 and channel 3, denoted by the numerical values "1", "2", "3", are interconnected together, the 3 digital I/O channels, namely, channel 4, channel 5 and channel 6, denoted by the numerical values "4", "5" and "6", are also interconnected together, and mutual signal transceiving can be realized among the digital I/O channels in each group.
The difference in the wiring length between the I/O interface of the test device and the calibration board additionally brings about an unsynchronization of the signal transmission/reception between the channels, so that in order to avoid such an additionally brought out unsynchronization, the wiring length of each digital I/O channel in each group between the test device and the calibration board is equal. As shown in fig. 4, the routing length of each digital I/O channel between the test equipment and the calibration board includes the wire length from the I/O interface of the test equipment to the connector, and the wire length from the connector to the PCB trace connection point on the calibration board. For more accurate signal synchronization, it is more preferable that the length of the connection of each I/O interface on the test equipment to the connector is the same and the length of each connection from the connector to the PCB trace connection point on the calibration board is the same.
The method for testing and solving the signal receiving and transmitting delay between the digital I/O channels in each group by using the first calibration board specifically comprises the following steps:
taking the digital I/O channels 1, 2, 3 in fig. 4 as an example, where T1 represents the delay of channel 1 in the signal transmission direction, this delay does not include the delay of the signal of channel 1 from the connector to the PCB trace connection point on the calibration board 1 (the same applies to R1, T2, R2, T3, R3 described below), and R1 is the delay of channel 1 in the signal receiving direction; t2 is the delay of the channel 2 in the signal transmitting direction, and R2 is the delay of the channel 2 in the signal receiving direction; t3 is the delay of the channel 3 in the signal transmitting direction, and R3 is the delay of the channel 2 in the signal receiving direction; a is the delay of the signal from the connector to the connection point of the PCB trace on the calibration board 1. Since the wiring lengths of the 3 digital I/O channels in the same group from the connector to the PCB trace connection point on the calibration board 1 are equal, the delay values a of the 3 digital I/O channels in the same group are all the same, and the fixed delay value a can be obtained by measurement.
After the delays T1, T2 and T3 of the channels 1, 2 and 3 in the signal sending direction and the delays R1, R2 and R3 in the signal receiving direction and the fixed delay value a are measured, the signal receiving and sending delay between every two digital I/O channels in the same group is calculated through the following formula (1):
D trij =ti+rj+2a equation (1)
In the formula (1), D trij Representing the signal reception delay from channel i to channel j;
ti represents the delay of channel i in the signal transmission direction;
rj represents the delay of channel j in the signal receiving direction;
a is the delay of the signal from the connector to the connection point of the PCB trace on the calibration board 1.
Taking fig. 4 as an example, a test signal is sent from channel 1, received from channel 2, and the signal transmit-receive delay D measured on TG tr12 ＝T1+R2+2a；
The test signal is sent from channel 1, received from channel 3, and the signal transmit-receive delay D measured on TG tr13 ＝T1+R3+2a；
The test signal is sent from channel 2, received from channel 1, and the signal transmit-receive delay D measured on TG tr21 ＝T2+R1+2a；
The test signal is sent from channel 2, received from channel 3, and the signal transmit-receive delay D measured on TG tr23 ＝T2+R3+2a；
The test signal is sent from channel 3, received from channel 1, and the signal transmit-receive delay D measured on TG tr31 ＝T3+R1+2a；
The test signal is sent from channel 3, received from channel 2, and the signal transmit-receive delay D measured on TG tr32 ＝T3+R2+2a。
Then according to D tr12 、D tr13 、D tr21 、D tr23 、D tr31 、D tr32 Designating common variables of signal delay calculation expressions of any digital I/O channel in transmitting direction or receiving directionDelay calculation expressions of each digital I/O channel in the transmission direction and the reception direction are constructed. For example, the delay R2 of the channel 2 in the signal receiving direction is designated as a common variable of the expression, and the delay calculation expression of the channel 1 in the signal transmitting direction is constructed as follows:
T1＝D tr12 -R2-2a；
the delay calculation expression of the channel 2 in the signal transmission direction is constructed as follows:
T2＝D tr21 -(D tr31 -D tr32 +R2)-2a；
the delay calculation expression of the channel 3 in the signal transmission direction is constructed as follows:
T3＝D tr32 -R2-2a；
the delay calculation expression of the channel 1 in the signal receiving direction is constructed as follows:
R1＝D tr31 -D tr32 +R2；
the delay calculation expression of the channel 3 in the signal receiving direction is constructed as follows:
R3＝D tr13 -D tr12 +R2。
thus, delay values of all channels in the signal transmission direction and the signal reception direction of the 3 channels of the channels 1, 2 and 3, which take the signal delay R2 of the channel 2 in the receiving direction as a common variable, are obtained.
In order to establish a connection between the groups separated in step S1 for delay calculation, as shown in fig. 2, the digital I/O channel calibration method of the semiconductor test apparatus provided in this embodiment further includes:
s2, regrouping the digital I/O channels in a staggered mode in a '1' mode to establish a delay calculation relation between the groups obtained in the step S1, and then testing and solving signal transceiving delay between the digital I/O channels in each regrouped group by using a second calibration board;
step S3, designating the signal delay of any digital I/O channel in the transmitting or receiving direction as a common variable of a delay calculation expression, constructing the delay calculation expression of each digital I/O channel in the transmitting direction and the receiving direction respectively, and solving;
and S4, performing delay compensation on the corresponding digital I/O channels by taking the delay value obtained in the step S3 as a compensation basis, thereby realizing the calibration alignment of the digital I/O channels.
The method of regrouping in an error "1" manner is described in detail below in conjunction with fig. 4:
the left-hand diagram of fig. 4 shows interconnected lanes 1, 2, 3 as a first packet from step S1 and interconnected lanes 4, 5, 6 as a second packet from step S1. It is assumed that delay calculation expressions of all 3 channels in the first packet in the signal transmission direction and the signal reception direction use signal delay R2 of channel 2 in the receiving direction as a common variable, and delay calculation expressions of all 3 channels in the second packet in the signal transmission direction and the signal reception direction use signal delay R5 of channel 5 in the receiving direction as a common variable. Because the signal receiving and transmitting delay calculation expressions of the digital I/O channels of the first packet and the second packet adopt different common variables, the signal receiving and transmitting delay between the digital I/O channel in the first packet and the digital I/O channel in the second packet cannot be directly solved. So to solve this problem we have established a link for delay computation from group to group, as obtained in step S1, to achieve a direct computation of signal delays between different groups of digital I/O channels.
The delay calculation connection is established among groups, and the method adopted by the method is as follows: the groups obtained in step S1 are regrouped in an error "1" manner. The following describes the error "1" grouping scheme with reference to fig. 3:
first, each packet obtained in step S1 is sorted, for example, assuming that there are 9 digital I/O channels on the test device, step S1 divides the 9 channels into 3 groups of 3 groups, i.e., a first packet, a second packet, and a third packet, where we can sort the first packet first, sort the second packet after the first packet, and sort the third packet after the second packet.
After the packet ordering is completed, the digital I/O channels in each packet are ordered. For example, the order numbers given to the 3 digital I/O channels in the first packet are 1, 2, 3, the order numbers given to the 3 digital I/O channels in the second packet are 4, 5, 6, and the order numbers given to the 3 digital I/O channels in the third packet are 7, 8, 9, respectively, forming an order sequence {1, 2, 3, 4, 5, 6, 7, 8, 9};
the digital I/O channels of the semiconductor test device are then re-grouped into sets starting with the digital I/O channel ordered second in the sequence. For example, lane 2, lane 3 and lane 4 in the first packet are regrouped, lane 5, lane 6 and lane 7 in the second packet are regrouped, lane 8, lane 9 and lane 1 in the third packet are regrouped.
After regrouping all digital I/O channels of the test equipment in such a wrong "1" manner, a delay calculation association is established between the groups obtained in step S1.
After the connection of delay calculation is established among the groups obtained in the step S1, the second calibration board is used for testing and solving the signal receiving and transmitting delay among the digital I/O channels in each newly obtained group, and the solving method is consistent with the principle of the method for solving the signal receiving and transmitting delay among the digital I/O channels in each group obtained in the step S1 by using the first calibration board.
A method for testing and resolving the signal transceiving delay between the digital I/O channels within each re-divided packet using the second calibration board is briefly described below with reference to fig. 3:
for example, the test signal transmitted by channel 3 shown in FIG. 3 is received by channel 2, and the delay D between transmission and reception is measured on TG tr32 ' T3+ R2+2b, b represents the delay from the connector to the PCB trace connection point on the second calibration board (i.e. calibration board 2 in fig. 3). From step S1, it has been obtained: t3=d tr32 -R2-2a, from which 2b=d can be calculated tr32 ′-D tr32 +2a。
If the channel 4 transmits the test signal to be received by the channel 2, the delay D between transmission and reception is measured on TG tr42 Since the calculation formula of 2b is known, =t4+r2+2b, t4=d can be calculated tr42 -(D tr32 ′-D tr32 +2a)-R2。
Through the above calculations, a connection between channels 1, 2, 3 and channels 4, 5, 6 is established. The existing results solved in step S1 can be used to represent the calculation expressions of the transmission delay and the reception delay of the channels 1-6 by using the reception delay R2 of the channel 2 as a common variable.
Continuing to test other packets, and so on, an expression of delay calculation in the transmit and receive directions for all channels with R2 as a common variable is obtained. And finally solving each expression to obtain a corresponding delay value of each channel, and carrying out delay compensation on the communication between the channels by taking the solved delay values as compensation basis, thereby aligning signals between the channels in the transmitting direction and the receiving direction.
In summary, the calibration board of the digital I/O channel is designed through three-wire interconnection, and the delay calculation expression with common variables is constructed and solved for each digital I/O channel, so that the design difficulty and the manufacturing cost of the calibration board are reduced, and the calibration precision of the digital I/O channel is improved.
It should be understood that the above description is only illustrative of the preferred embodiments of the present application and the technical principles employed. It will be apparent to those skilled in the art that various modifications, equivalents, variations, and the like can be made to the present application. However, such modifications are intended to fall within the scope of the present application without departing from the spirit of the present application. In addition, some terms used in the description and claims of the present application are not limiting, but are merely for convenience of description.
Claims (10)
1. A method for calibrating a digital I/O channel of a semiconductor test apparatus, comprising the steps of:
s1, grouping digital I/O channels of semiconductor test equipment into a group according to at least 3, and then testing and solving signal receiving and transmitting delay among the digital I/O channels in each group by using a first calibration board;
s2, regrouping the digital I/O channels in a staggered mode of '1' so as to establish a delay calculation relation between groups obtained in the step S1, and then testing and solving signal receiving and transmitting delay between the digital I/O channels in each regrouped group by using a second calibration board;
s3, designating the signal delay of any digital I/O channel in the transmitting direction or the receiving direction as a common variable of a delay calculation expression, constructing the delay calculation expression of each digital I/O channel in the transmitting direction and the receiving direction respectively, and solving;
s4, performing delay compensation on the corresponding digital I/O channels by taking the delay value obtained in the step S3 as a compensation basis, thereby realizing calibration alignment of the digital I/O channels.
2. The method for calibrating digital I/O channels of semiconductor test apparatus according to claim 1, wherein in step S1, a plurality of digital I/O channels on the test apparatus are divided into a plurality of groups in groups of 3.
3. The method for calibrating a digital I/O channel of a semiconductor test apparatus according to claim 1, wherein a wiring length of each of the digital I/O channels in each group divided in step S1 is the same between the semiconductor test apparatus and the first calibration board.
4. The method of calibrating digital I/O channels of a semiconductor test apparatus according to claim 1, wherein the method of testing and solving signal transceiving delay between the digital I/O channels within each packet using the first calibration board or the second calibration board is expressed by the following formula (1):
D trij =ti+rj+2m equation (1)
In the formula (1), D trij Representing the signal reception delay from digital I/O lane I to digital I/O lane j within the same packet;
ti represents the delay of the digital I/O channel I in the signal transmission direction;
rj represents the delay of the digital I/O channel j in the signal receiving direction;
m is the delay of the test signal from the connector to the PCB wiring connection point on the first calibration board or the second calibration board.
5. The method for calibrating a digital I/O channel of a semiconductor test apparatus according to claim 1, wherein in step S2, the method for regrouping the groups obtained in step S1 in an error "1" manner is as follows:
s21, sequencing each group obtained in the step S1;
s22, after finishing grouping sequencing, sequencing each digital I/O channel in each group to form a sequence arranged in sequence;
s23, starting from the second digital I/O channel in the sequence, and re-dividing the digital I/O channels of the semiconductor test equipment into a plurality of groups.
6. The method according to claim 5, wherein in step S23, each of the digital I/O channels of the semiconductor test apparatus is re-divided into a plurality of groups in the same grouping unit as step S1 from the digital I/O channel of the second ordered in the sequence.
7. The method according to claim 5, wherein in step S2, the wiring length of each of the digital I/O channels in each group divided in an error "1" manner between the semiconductor test apparatus and the second calibration board is the same.
8. The method of calibrating digital I/O channels of a semiconductor test apparatus according to claim 5, wherein in step S2, the digital I/O channels on the test apparatus are regrouped in groups of 3.
9. A digital I/O channel calibration method of a semiconductor test apparatus according to claim 3, wherein the wiring length of the digital I/O channel between the semiconductor test apparatus and the first calibration board comprises the wiring length from the I/O interface of the semiconductor test apparatus to a connector and the wiring length from the connector to a PCB trace connection point on the first calibration board;
the length of the wiring from each I/O interface to the connector is the same and the length of each wiring led out from the connector and connected to the PCB wiring connection point of the first calibration board is the same.
10. The method of calibrating a digital I/O channel of a semiconductor test apparatus of claim 7, wherein a wiring length of the digital I/O channel between the semiconductor test apparatus and the second calibration board includes a wiring length from an I/O interface of the semiconductor test apparatus to a connector and a wiring length from the connector to a PCB trace connection point on the second calibration board;
the length of the wiring from each I/O interface to the connector is the same and the length of each wiring led out from the connector and connected to the PCB wiring connection point of the second calibration board is the same.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114137394A (en) * | 2021-12-01 | 2022-03-04 | 上海御渡半导体科技有限公司 | Synchronous calibration device and method for trigger signal sending direction |
| CN118093465A (en) * | 2024-04-28 | 2024-05-28 | 西安智多晶微电子有限公司 | Data word alignment method for DDR PHY |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114137394A (en) * | 2021-12-01 | 2022-03-04 | 上海御渡半导体科技有限公司 | Synchronous calibration device and method for trigger signal sending direction |
| CN114137394B (en) * | 2021-12-01 | 2024-01-16 | 上海御渡半导体科技有限公司 | Synchronous calibration device and calibration method for trigger signal transmitting direction |
| CN118093465A (en) * | 2024-04-28 | 2024-05-28 | 西安智多晶微电子有限公司 | Data word alignment method for DDR PHY |
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