CN219016560U - Channel delay calibration equipment and system - Google Patents
Channel delay calibration equipment and system Download PDFInfo
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- CN219016560U CN219016560U CN202222810512.7U CN202222810512U CN219016560U CN 219016560 U CN219016560 U CN 219016560U CN 202222810512 U CN202222810512 U CN 202222810512U CN 219016560 U CN219016560 U CN 219016560U
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Abstract
The utility model discloses a channel delay calibration device and a system. The channel delay calibration device comprises: a switch array board card and an upper computer; the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array; the upper computer is connected with each stage of switching element group and is used for controlling the switching states of the front stage of switching element group and the rear stage of switching element group and taking any switch gating channel as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with a preset transmission channel and a target gating channel in the reference board card. The utility model solves the technical problems of low efficiency and high cost caused by using external instruments such as oscilloscopes to perform manual calibration when performing time delay calibration in the related technology.
Description
Technical Field
The utility model relates to the technical field of digital equipment calibration, in particular to channel delay calibration equipment and a system.
Background
In the industrial production process, a general-purpose digital board card generally has a plurality of channels, and is mainly used for outputting and inputting digital signals. Because the delay of each channel is inconsistent, calibration compensation is often needed to be carried out on the transmission channels of the digital board card, so that the synchronicity of the output and the input of all channels within a certain error range is achieved. In the manual calibration scheme, when calibrating output, taking a 0 channel as a reference, comparing output waveform delay of other channels by using an oscilloscope; when the input is calibrated, the signal generator output waveform is used to compare the reception delays of the various channels. In the automatic calibration scheme, a set of special Timing (delay) calibration tool is designed, and has the functions of measuring similar to an oscilloscope and outputting a signal generator, and the automatic calibration is carried out after all channels of a digital board card are accessed.
Currently, when calibrating delay deviation among channels, there are two schemes of manual calibration and automatic calibration, in the manual calibration scheme, the waveform delay of each transmission channel is calibrated by using external instruments such as an oscilloscope, a signal generator and the like, and the calibration efficiency is low; in the automatic calibration scheme, a set of special Timing (delay) calibration tool is designed, and has the functions of measuring similar to an oscilloscope and outputting a signal generator, and the automatic calibration is performed after all channels of a digital board card are accessed, so that the operation is complex and the cost is high.
In view of the above problems, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the utility model provides a channel delay calibration device and a system, which at least solve the technical problems of low efficiency and high cost caused by using external instruments such as an oscilloscope to perform manual calibration when delay calibration is performed in the related technology.
According to one aspect of the embodiment of the utility model, a channel delay calibration device and a system are provided, wherein the device comprises a switch array board card and an upper computer; the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array; the upper computer is connected with each stage of switching element group and is used for controlling the switching states of the front stage of switching element group and the rear stage of switching element group and taking any switch gating channel as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with a preset transmission channel and a target gating channel in the reference board card.
Optionally, a reference switch array board card is connected in series between the switch array board card and the reference board card; the reference switch array board card comprises a reference switch array, wherein the reference switch array comprises a plurality of stages of reference switch element groups which are sequentially connected, and a plurality of reference switch gating channels are arranged in the reference switch array; the upper computer is also used for controlling the switching state of the front and rear stage reference switching element groups, and gating any reference switching gating channel is used as a target reference gating channel, and the target reference gating channel is connected with the target gating channel and a preset transmission channel in the reference board card.
Optionally, the coaxial line is used for connecting the reference switch array board card with the switch array board card.
Optionally, the switch array board card inner structure is the same as the reference switch array board card inner structure.
Optionally, each stage of switching element group further comprises a target transmission line, wherein each section of target transmission line comprises two endpoints, and the endpoints are used for electrically connecting with the target switching elements or the signal transmission channels; each target switching element comprises a selection end and a transmission end, wherein the transmission end is connected with the first end points, the transmission ends are in one-to-one correspondence with the first end points, the selection end is corresponding to the second end points and is used for selecting one second end point from the second end points to be electrically connected, the first end point is an end point of a target transmission line in a switching element group where the target switching element is located, and the second end point is an end point of a target transmission line outside the switching element group where the target switching element is located.
Optionally, the switch array board card further includes an interface transmission line, where the interface transmission line is a target transmission line connected to the signal transmission channel, and the multi-stage switch element group includes: a first switching element group, a second switching element group, and at least one third switching element group located between the first switching element group and the second switching element group; and, the first switching element group includes: the first switching elements are target switching elements positioned in the first switching element group, the first transmission lines are target transmission lines positioned in the first switching element group, the first transmission lines correspond to the first switching elements one by one, and each first switching element corresponds to second endpoints of a preset number of interface transmission lines; the second switching element group includes: the second switching element is a target switching element positioned in the second switching element group, the second transmission line is a target transmission line positioned in the second switching element group, the second transmission line corresponds to the second switching element, the second switching element corresponds to a preset number of second endpoints, and the second switching element is communicated with the reference board card through the second transmission line; the third switching element group includes: the third switching elements are target switching elements positioned in a third switching element group, the third transmission lines are target transmission lines positioned in the third switching element group, the third transmission lines correspond to the third switching elements one by one, and each third switching element corresponds to a preset number of second endpoints.
Optionally, the number of the target switching elements in each switching element group is obtained by rounding up the ratio of N to M, where N is the number of signal transmission channels in the board to be calibrated or the number of the target switching elements in the previous switching element group of the current switching element group, and M is the preset number of second endpoints corresponding to each target switching element in the current switching element group.
Alternatively, the target switching elements in the same-stage switching element group are identical in structure.
Optionally, the lengths of the target transmission lines in the same-level switch element groups are consistent, and the lengths of the interface transmission lines in the switch array board cards are consistent.
According to another aspect of the embodiment of the application, there is also provided a channel delay calibration system, including an upper computer, a reference board card and a switch array board card; the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array; the upper computer is connected with each stage of switching element group and is used for controlling the switching states of the front stage of switching element group and the rear stage of switching element group and taking any switch gating channel as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with a preset transmission channel and a target gating channel in the reference board card; the reference board card is connected with the board card to be calibrated through the switch array board card, wherein a plurality of signal transmission channels are arranged in the board card to be calibrated, and each signal transmission channel corresponds to one target gating channel in the switch array board card.
In an embodiment of the present utility model, a channel delay calibration device and system are provided, including: a switch array board card and an upper computer; the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array; the upper computer is connected with each stage of switching element group and is used for controlling the switching states of the front stage of switching element group and the rear stage of switching element group and taking any switch gating channel as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with a preset transmission channel and a target gating channel in the reference board card. Any signal transmission channel in the reference board card is controlled to be sequentially communicated with each signal transmission channel in the board card to be calibrated by adjusting the switching state of the target switching element in the switch array, so that delay deviation among the signal transmission channels in the board card to be calibrated is calibrated, the purposes of measuring output and input delay of all channels of a plurality of digital board cards mutually and performing Picosecond (PS) level precision compensation calibration are achieved, and the technical problems of low efficiency and high cost caused by the fact that external instruments such as oscilloscopes are used for manual calibration in the time delay calibration of related technologies are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a limitation on the utility model. In the drawings:
fig. 1 is a schematic structural diagram of a channel delay calibration device and a system according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of an internal structure of a switch array board card according to an embodiment of the present utility model;
fig. 3 is a schematic structural diagram of an eight-channel delay calibration device according to an embodiment of the present utility model.
Reference numerals illustrate: 10-digital board card 1 (board card to be calibrated), 12-switch array board card, 14-host computer, 16-coaxial line, 18-reference switch array board card, 20-digital board card 2 (reference board card), 102-signal transmission channel, 122-first type interface in switch array board card, 124-switch array, 1242-switch element group, 126-second type interface in switch array board card, 128-interface transmission line in switch array board card, 142-communication interface, 182-first type interface in reference switch array board card, 184-reference switch array, 1842-reference switch element group, 186-second type interface in reference switch array board card, 188-interface transmission line in reference switch array board card, 202-target switch element, 204-target transmission line, 206-selection end, 208-transmission end.
Detailed Description
In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an embodiment of the present utility model, an embodiment of a channel delay calibration device is provided, and fig. 1 is a schematic structural diagram of a channel delay calibration device and a system provided according to an embodiment of the present utility model, as shown in fig. 1, where the channel delay calibration device includes: a switch array board 12 and an upper computer 14; the switch array board card 12 comprises a switch array 124, wherein the switch array 124 comprises a multi-stage switch element group 1242 which is connected in sequence, and a plurality of switch gating channels are arranged in the switch array 124; the upper computer 14 is connected with each stage of switching element group and is used for controlling the switching state of the front stage of switching element group 1242 and the back stage of switching element group 1242 so as to gate any switch gating channel as a target gating channel; the upper computer 14 includes a communication interface 142, which is used for connecting with the board 10 to be calibrated and the reference board 20, and sequentially controlling each signal transmission channel 102 in the board 10 to be calibrated to be connected with a preset transmission channel and a target gating channel in the reference board 20.
Specifically, the switch array may be an array formed by any controllable switch element group, and in this embodiment, the switch array 124 is a relay array, and in the switch array board 12, different switch gating channels may be gated by changing the switching state of the target switch element.
It should be noted that, the board to be calibrated is the digital board for planning to calibrate the delay deviation between the signal transmission channels, the reference board is the digital board for assisting the board to be calibrated to calibrate by signal transmission with the board to be calibrated, the board to be calibrated and the reference board are both digital boards, as shown in fig. 1, the two digital boards can be mutually calibrated, and when the digital board 1 is used as the board to be calibrated, the digital board 2 is used as the reference board; when the digital board card 1 is used as a reference board card, the digital board card 2 is used as a board card to be calibrated, and when the actions of the two digital board cards are changed, the functions of the switch array board card and the reference switch array board card corresponding to the two digital board cards are also switched.
It should be noted that the board card to be calibrated and the reference board card may be other resource board cards, such as a radio frequency board card, a power board card, or an analog board card, which is not limited in this application.
In some embodiments of the present application, the digital board 1 is used as the board 10 to be calibrated, and the digital board 2 is used as the reference board 20.
As an alternative embodiment, a reference switch array board 18 is connected in series between the switch array board 12 and the reference board 20; the reference switch array board card 18 comprises a reference switch array 184, wherein the reference switch array 184 comprises a multi-stage reference switch element group 1842 which is sequentially connected, and a plurality of reference switch gating channels are arranged in the reference switch array; the upper computer 14 is further configured to control the switching states of the front and rear reference switching element groups 1842, so as to gate any reference switching channel as a target reference switching channel, where the target reference switching channel is connected to the target switching channel and a preset transmission channel in the reference board 20.
As an alternative embodiment, the upper computer 14 may be implemented by sending instructions to the switch array board and the controllers in the reference switch array board when controlling the switching states of the front and rear stage switching element groups 1242 and the front and rear stage reference switching element groups 1842, where the controllers for controlling the switching states of the switching elements are existing devices (not shown in the figure).
As an alternative embodiment, the target reference strobe channel may be connected to a pre-set transmission channel within the reference board 20 through a first type of interface 182 and interface transmission line 188 located in the reference switch array board.
In some embodiments of the present application, the switch array card 12 is internally structured the same as the reference switch array card 18. The switch array board card 12 and the reference switch array board card 18 are provided with the same number of interfaces, the same length of transmission lines and the same structure of switch array board cards.
In order to ensure that the two reference switch array cards 18 and the switch array card 12 can be mutually aligned, coaxial lines 16 are required to be arranged between the two reference switch array cards 18 and the switch array card 12, so that only one connecting path exists between the switch array card 12 and the reference switch array card 18.
Taking a board card to be calibrated and a reference board card as an example, when the digital board cards are calibrated by adopting channel delay calibration equipment, the space between the digital board cards is not limited to be provided with two switch array board cards with the same structure, a plurality of switch array board cards with the same structure can be connected at the same time, each switch array board card corresponds to one digital board card, and channel delay calibration can be carried out on two optional digital board cards among the digital board cards.
In addition, as an alternative embodiment, when the reference switch array board 18 is connected to the switch array board 12 through the coaxial line 16, the connection may be implemented by means of the second type of interface 126 located in the switch array board and the second type of interface 186 located in the reference switch array board as shown in fig. 1.
Fig. 2 is a schematic structural diagram of an internal structure of a switch array board according to an embodiment of the present utility model, as shown in fig. 2, each stage of switch element group 1242 in the switch array board 12 further includes a target transmission line 204, where each stage of the target transmission line 204 includes two end points, and the end points are used for electrically connecting with the target switch elements 202 or the signal transmission channels 102; each of the target switching elements 202 includes a selection end 206 and a transmission end 208, where the transmission end 208 is connected to a first end point, the transmission end 208 corresponds to the first end point one to one, and the selection end 206 corresponds to a plurality of second end points, and is used to select one second end point from the plurality of second end points to be electrically connected, where the first end point is an end point of the target transmission line 204 located in the switching element group where the target switching element 202 is located, and the second end point is an end point of the target transmission line 204 located outside the switching element group where the target switching element 202 is located.
In some embodiments of the present application, the switch array board 12 further includes an interface transmission line 128, where the interface transmission line 128 is a target transmission line 204 connected to the signal transmission channel 102, and the multi-stage switch element group 1242 includes: a first switching element group, a second switching element group, and at least one third switching element group located between the first switching element group and the second switching element group; and, the first switching element group includes: the first switching elements are target switching elements 202 located in a first switching element group, the first transmission lines are target transmission lines located in the first switching element group, the first transmission lines correspond to the first switching elements one by one, and each first switching element corresponds to second endpoints of a preset number of interface transmission lines 128; the second switching element group includes: the second switching element is a target switching element 202 positioned in the second switching element group, the second transmission line is a target transmission line positioned in the second switching element group, the second transmission line corresponds to the second switching element, the second switching element corresponds to a preset number of second endpoints, and the second switching element is communicated with the reference board card 20 through the second transmission line; the third switching element group includes: the third switching elements are target switching elements 202 located in a third switching element group, the third transmission lines are target transmission lines located in the third switching element group, the third transmission lines correspond to the third switching elements one by one, and each third switching element corresponds to a preset number of second endpoints.
Specifically, the third switching element groups are connected step by step, the third switching element group of the forefront stage is correspondingly connected with the first switching element group, and then the third switching element groups of the multistage are sequentially connected until the third switching element group of the last stage is connected with the second switching element group.
As an alternative embodiment, the connection may be made by means of the first type of interface 122 shown in fig. 1 when the interface transmission line 128 is connected to the signal transmission channel 102.
In this embodiment, only one switching element group may be present in the switching array, that is, the first switching element group, the second switching element group, and the third switching element group are the same switching element group.
In order to determine the number of switching elements in each stage of switching element group, the number of target switching elements 202 in each switching element group is obtained by rounding up the ratio of N to M, where N is the number of signal transmission channels 102 in the board to be calibrated 10 or the number of target switching elements 202 in the switching element group preceding the current switching element group, and M is the preset number of second endpoints corresponding to each target switching element 202 in the current switching element group.
In order to accurately measure the delay skew between the respective signal transmission channels 102 of the board card 10 to be calibrated, the structures of the target switching elements located in the same switching element group in the same board card 12 of the same opening Guan Zhen are identical, and the lengths of the target transmission lines located in the same switching element group in the same board card 12 of the switch array are identical.
Specifically, the target switching elements 202 in the same-level switching element group have identical structures, the switching elements of the same model should be adopted, and the electronic elements, lines, assembly structures, welding modes and the like in each switching element should be identical.
In order to accurately measure the delay skew between the signal transmission channels 102 of the board card 10 to be calibrated, the target transmission lines 204 in the same-stage switching element group are uniform in length, and the interface transmission lines 128 in the switch array board card 12 are uniform in length.
In the process of channel delay calibration, the upper computer 14 is used for controlling each signal transmission channel 102 of the board to be tested to be communicated with a certain channel of the reference board 20, specifically, the upper computer 14 is connected with the switch array 124 in each switch array board 12, and is used for controlling the signal transmission channel 102 in the board to be calibrated 10 to be communicated with one certain signal transmission channel 102 in the reference board 20 sequentially by adjusting the target switch element 202, so that delay deviation among the signal transmission channels 102 in the board to be calibrated 10 is calibrated according to delay when different signal transmission channels 102 are communicated.
In order to measure the delay of each signal transmission channel 102, the host computer 14 includes a communication interface 142, which is used to connect with the board card 10 to be calibrated and the reference board card 20, and is used to control the operation modes of the signal transmission channels 102, where the operation modes include: an input mode and an output mode; the upper computer 14 is also used for measuring delay deviation among the signal transmission channels 102 and performing delay calibration on the delay deviation.
In order to determine whether the delay deviation between the signal transmission channels 102 after the delay compensation is corrected, the upper computer 14 is further configured to control any signal transmission channel 102 in the reference board 20 to be sequentially communicated with each signal transmission channel 102 in the board 10 to be calibrated again, and check whether the delay deviation between each signal transmission channel 102 after the delay calibration is zero.
In this embodiment, when the host computer 14 is connected to the digital board card or the switch array board card 12, the command may be transmitted through the communication module, or the two may be directly connected through a signal line.
Taking a board card to be calibrated with 8 channels as an example to further describe the above-mentioned channel delay calibration device, fig. 3 is a schematic structural diagram of a principle structure of an eight-channel delay calibration device according to an embodiment of the present utility model, as shown in fig. 3, in this embodiment, the switch element is a relay, and the switch array board card and the reference switch array board card are relay array boards.
The relay array boards RA and RB are 2 identical circuit boards, on which the relays K are distributed, and are connected with 8 channels (namely the signal transmission channels) of the digital board card through the connector interface J (namely the first type interface). The wiring of all channels on the relay array board (i.e. the target transmission lines) must be equal in length, i.e. 8 paths in the T1 group are equal in length, 4 paths in the T2 group are equal in length, and 2 paths in the T3 group are equal in length, so as to eliminate delay differences caused by different paths.
When the channel outputs of RA are calibrated, the corresponding relays of RA are controlled to lead each channel to an interface D (namely the second type of interfaces) in sequence, the RB interface D is input through a coaxial line L, the corresponding relays of RB are controlled to lead to a channel 0, namely all the channel outputs of RA are measured by using the channel 0 of RB. TDAi represents the output delay of the internal channel i of the digital board where RA is located, TRAi represents the delay of the channel i on the RA board, TL represents the delay of the coaxial line L, TRB0 represents the delay of the channel 0 on the RB board, TCB0 represents the input delay of the digital board where RB is located, and the measurement result TXAi can be expressed as follows:
TXAi＝TDAi+TRAi+TL+TRB0+TCB0
since all channel path lengths of trail (i=0 to 7) are equal, tl+trb0+tcb0 is the same path, the difference between the measured delays TXAi, TXAj of any 2 channels i and j is equal to the difference between the output delays TDAi, TDAj inside the digital board:
TXAi–TXAj＝TDAi-TDAj
by compensating the difference, the output delay of all channels in the digital board is the same. The measurement is repeated once during verification, and all RA channel outputs reach RB channel 0 at the same time within the accuracy range, so that calibration is passed.
When the channel input of RA is calibrated, the same relay switching method is adopted when the calibration output is adopted, so that the channel 0 of RB is output, and all the channels of RA are sequentially measured. The measured difference value of any 2 channels delay TYAIs and TYAj is equal to the difference value of the input delays TCAIs and TCAj in the digital board where RA is located, and the input delays of all channels in the digital board are the same by compensating the difference value.
TYAi–TYAj＝TCAi-TCAj
Similarly, by compensating the difference value, the input delay of all channels in the digital board is the same. The measurement is repeated once during verification, and all RA channels simultaneously receive signals of RB channel 0 within the accuracy range, so that the calibration is passed.
Similarly, RA is used to calibrate the output and input Timing of the digital board where RB is located. Through the method, mutual calibration among a plurality of digital boards is realized. The calibration accuracy can be controlled within + -500 ps.
The relay array plate is used for switching channels among multiple plates, automatic calibration is achieved, an oscilloscope and a signal generator are not needed, calibration efficiency is improved, and compared with a special Timing calibration tool, the relay array plate is simple in principle, convenient to design and low in cost.
As an alternative embodiment, the relay array board has multiple functions, and the connection multimeter can realize voltage and current measurement and calibration, and the connection oscilloscope can measure waveform amplitude, frequency and the like.
According to an embodiment of the present utility model, there is also provided an embodiment of a channel delay calibration system, as shown in fig. 1, including: the device comprises an upper computer, a reference board card and a switch array board card; the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array; the upper computer is connected with each stage of switching element group and is used for controlling the switching states of the front stage of switching element group and the rear stage of switching element group and taking any switch gating channel as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with a preset transmission channel and a target gating channel in the reference board card; the reference board card is connected with the board card to be calibrated through the switch array board card, wherein a plurality of signal transmission channels are arranged in the board card to be calibrated, and each signal transmission channel corresponds to one target gating channel in the switch array board card.
It should be noted that, the explanation of the channel delay calibration device provided in this embodiment is also applicable to the embodiments of the present application, and is not repeated here.
Through the channel delay calibration equipment and the channel delay calibration system, any signal transmission channel in the reference board card is controlled to be sequentially communicated with each signal transmission channel in the board card to be calibrated by adjusting the on-off state of the target switch element in the switch array through the upper computer, so that delay deviation among all signal transmission channels in the board card to be calibrated is calibrated, the purposes of measuring output and input delay of all channels of a plurality of digital boards mutually and performing Picosecond (PS) level precision compensation calibration are achieved, and the technical problems of low efficiency and high cost caused by using external instruments such as oscilloscopes to perform manual calibration when the delay calibration is performed in the related technology are solved.
The foregoing is merely a preferred embodiment of the present utility model and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present utility model, which are intended to be comprehended within the scope of the present utility model.
Claims (10)
1. A channel delay calibration apparatus comprising: a switch array board card and an upper computer;
the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array;
the upper computer is connected with the switching element groups of each stage and used for controlling the switching states of the switching element groups of the front stage and the rear stage, and any switching gating channel is used as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with the preset transmission channel in the reference board card and the target gating channel.
2. The channel delay calibration apparatus of claim 1, further comprising:
the reference switch array board card is connected in series between the switch array board card and the reference board card; the reference switch array board card comprises a reference switch array, wherein the reference switch array comprises a plurality of stages of reference switch element groups which are sequentially connected, and a plurality of reference switch gating channels are arranged in the reference switch array;
the upper computer is further used for controlling the switching states of the reference switching element groups at the front stage and the rear stage, and gating any reference switching gating channel to serve as a target reference gating channel, wherein the target reference gating channel is connected with the target gating channel and a preset transmission channel in the reference board card.
3. The channel delay calibration apparatus of claim 2, further comprising:
and the coaxial line is used for connecting the reference switch array board card with the switch array board card.
4. The channel delay calibration apparatus of claim 2 wherein the switch array board card internal structure is identical to the reference switch array board card internal structure.
5. The channel delay calibration apparatus of claim 1 wherein each stage of said set of switching elements further comprises a target transmission line, wherein,
each section of the target transmission line comprises two endpoints, wherein the endpoints are used for being electrically connected with a target switching element or the signal transmission channel;
each target switching element comprises a selection end and a transmission end, wherein the transmission ends are connected with first end points, the transmission ends are in one-to-one correspondence with the first end points, the selection ends are corresponding to a plurality of second end points and are used for selecting one second end point from the plurality of second end points to be electrically connected, the first end point is the end point of the target transmission line in the switching element group where the target switching element is located, and the second end point is the end point of the target transmission line outside the switching element group where the target switching element is located.
6. The channel delay calibration apparatus of claim 5 further comprising an interface transmission line in the switch array board, wherein the interface transmission line is the target transmission line connected to the signal transmission channel, and wherein the multi-stage switching element group comprises: a first switching element group, a second switching element group, and at least one third switching element group located between the first switching element group and the second switching element group;
the first switching element group includes: the first switching elements are the target switching elements positioned in the first switching element group, the first transmission lines are the target transmission lines positioned in the first switching element group, the first transmission lines are in one-to-one correspondence with the first switching elements, and each first switching element corresponds to the second endpoints of a preset number of interface transmission lines;
the second switching element group includes: the second switching element is the target switching element positioned in the second switching element group, the second transmission line is the target transmission line positioned in the second switching element group, the second transmission line corresponds to the second switching element, the second switching element corresponds to a preset number of second endpoints, and the second switching element is communicated with the reference board card through the second transmission line;
the third switching element group includes: the third switching elements are the target switching elements located in the third switching element group, the third transmission lines are the target transmission lines located in the third switching element group, the third transmission lines are in one-to-one correspondence with the third switching elements, and each third switching element corresponds to a preset number of second endpoints.
7. The channel delay calibration apparatus of claim 6, wherein the number of the target switching elements in each switching element group is obtained by rounding up a ratio of N to M, where N is the number of the signal transmission channels in the board to be calibrated or the number of target switching elements in a preceding switching element group of a current switching element group, and M is the preset number of the second end points corresponding to each target switching element in the current switching element group.
8. A channel delay calibration apparatus as defined in claim 7 wherein the target switching elements in a group of switching elements of a peer are of uniform structure.
9. A channel delay calibration device as recited in claim 7, wherein the target transmission lines in the group of switching elements of a peer are uniform in length and the interface transmission lines in the switch array board are uniform in length.
10. A channel delay calibration system, comprising: the device comprises an upper computer, a reference board card and a switch array board card;
the switch array board card comprises a switch array, wherein the switch array comprises a multi-stage switch element group which is sequentially connected, and a plurality of switch gating channels are arranged in the switch array;
the upper computer is connected with the switching element groups of each stage and used for controlling the switching states of the switching element groups of the front stage and the rear stage, and any switching gating channel is used as a target gating channel; the upper computer comprises a communication interface which is used for being connected with the board card to be calibrated and the reference board card, and sequentially controlling each signal transmission channel in the board card to be calibrated to be connected with a preset transmission channel and the target gating channel in the reference board card;
the reference board card is connected with the board card to be calibrated through the switch array board card, wherein a plurality of signal transmission channels are arranged in the board card to be calibrated, and each signal transmission channel corresponds to one target gating channel in the switch array board card.
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| CN202222810512.7U CN219016560U (en) | 2022-10-24 | 2022-10-24 | Channel delay calibration equipment and system |
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