CN1540868A - Frequency synthesizer of using all-digit frequency detector and analogue phase detector - Google Patents
Frequency synthesizer of using all-digit frequency detector and analogue phase detector Download PDFInfo
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- CN1540868A CN1540868A CNA2004100332446A CN200410033244A CN1540868A CN 1540868 A CN1540868 A CN 1540868A CN A2004100332446 A CNA2004100332446 A CN A2004100332446A CN 200410033244 A CN200410033244 A CN 200410033244A CN 1540868 A CN1540868 A CN 1540868A
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Abstract
A frequency synthesizer suitable for integration in a low voltage digital CMOS process controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls the center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop, thus eliminating any static frequency error. In effect, the analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made much smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This gross parametric difference is used in the design of the VCO to allow two separate control inputs, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.
Description
Technical field
The present invention generally relates to the field of integrated frequency synthesizer and oscillator.Specifically, the low pressure digital CMOS process that is to use that the present invention relates to is realized the field of variable voltage oscillator.
Background technology
In Modern Communication System, the high-speed phase-locked loop road is used to multiple use, comprising the frequency synthesis operation that recovers and retime such such as clock generation, data.This frequency synthesizer is analog circuit normally, but in order to reduce cost, tends to use the low pressure digital CMOS process to realize sort circuit industrial at present.
Frequency synthesizer is controlled by voltage usually, therefore, when realizing frequency synthesizer in the low pressure digital CMOS process, can run into the problem of signal headroom (headroom) and retractility.Although there are these problems, owing to it obviously reduces benefit of operating voltage, therefore, the application still sustainable growth of advanced sub-micron digital CMOS process aspect generation of enforcement simulated clock simulation clock and recovery.
Yet along with the reduction of operating voltage, the voltage range amount or the voltage headroom that can be used for these analog circuits also obviously reduce.As a result, the voltage range that can be used for FREQUENCY CONTROL and correction signal greatly reduces, and this just requires oscillator more moving in the strict design parameter.Therefore, concerning analog circuit, the headroom of this minimizing has been forced a great constraints to circuit design in high frequency clock is synthetic.
Although the inevitable outcome of this trend is to obtain complicated digital function on the area of minimum, but well-known, the high-speed figure function of integrated complexity can cause the shake composition of parasitic frequency and Geng Gao near low clearance, high-gain simulated clock simulation clock assembly.
Therefore need a kind of being used for to implement a kind of analog circuit of shaking reduction and voltage headroom expansion at the low pressure digital CMOS process.
Summary of the invention
The present invention is intended to address these problems.
An object of the present invention is to provide a kind of voltage controlled oscillator VCO that is suitable for being integrated in the low pressure digital CMOS process, the voltage headroom of wherein said VCO does not reduce too many from its rail-to-rail (rail torail) voltage range.
Another object of the present invention is to provide a kind of the shake to reduce and the bigger simulation VCO of frequency lock-in range in the low pressure digital CMOS process.
In addition, another object of the present invention provides a kind of straightforward procedure of implementing a kind of VCO of simulation under the situation of CMOS technology at digital CMOS process not needing to revise of being used for.
In order to realize these purposes, the invention process a kind of frequency synthesizer, it has the double loop structure that comprises an analogue loop and a digital loop, so that control a voltage controlled oscillator VCO.Described digital loop comprises a digital beat frequency detector (FDD) that the centre frequency of VCO is controlled.This analogue loop then comprises an analogue phase frequency detector (PFD) and charge pump, and it can add phase coherence in the frequency control loop to, eliminates any static frequency error thus.In fact, analogue loop has reduced the noise of Digital Logic and VCO, and the digital control frequency that then provides keeps and very low bandwidth.The digital loop bandwidth is far smaller than the analogue loop bandwidth.Preferably, the analogue loop bandwidth is bigger 200 times than digital loop bandwidth at least.In VCO design, used this total parametric difference to allow two independent controls inputs, first simulation control input that provides by the PFD of analogue loop inside just and second digital controlled signal that provides by the FDD of digital loop inside.These two control input functions are separate each other.
In the first embodiment of the present invention, VCO is equipped with two kinds of difference independently in response to controlling the frequency adjusting mechanism of importing from the first control input of PFD with from second of FDD.The first frequency adjusting mechanism comprise one right in response to varactor from the first simulation control input of PFD.The second frequency adjusting mechanism then comprises an electric capacity/switch to array, and wherein each switch all sends independent bit line from the digital signal bus of second digital controlled signal of FDD in response to those.According to the second control input, these switches arrive its corresponding capacitor-coupled described VCO circuit conditionally or separate with it.
The numeral beat frequency detector comprises a n digit counter and the m digit counter to counting from the oscillator output signal cycle of VCO that the reference frequency cycle is counted, and wherein m is greater than n.All these two counters are all resetted together, are stopped and being started according to a control logic circuit.
Preferably, two memory cell that are implemented as latch to the n in the m digit counter and (n+1) position monitor, and write down n or (n+1) position time of changing logic high into.No matter the n of m digit counter inside or (n+1) position whether can in the process that the VCO output cycle is counted, transform back into logic low after a while, these two latchs all keep the state of their records, till control logic circuit resets it.Be transformed into logic high in response to the n position in the n digit counter, these two counters are stopped automatically.In this point, the current data content of m digit counter and the memory contents of these two memory cell are studied.The least significant bit (LSB) of ignoring the predetermined quantity of m digit counter inside is so that ignore any difference in the counting of the n digit counter that causes owing to the relative phase difference between VCO output signal and the reference frequency signal and m digit counter.According to the data content (LSB that gets rid of predetermined quantity) of this m digit counter and the set situation of these two memory cell, control logic circuit determines that the output frequency of VCO is faster, slower than or locks onto reference frequency signal, and to second appropriate control signal of VCO transmission, so that compensate as required.
The structure of FDD provides a kind of intrinsic low-pass filtering operation that is used for frequency difference between filtering reference frequency signal and the VCO output signal.By improving or reduce the digital step-length of the increment/decrement of the value of the n in the described n digit counter and second control signal that adjustment sends to VCO, can be regulated the bandwidth of the intrinsic low pass filter of FDD.
In conjunction with the drawings with reference to the following description book and claim, other purposes of the present invention, results are together with the more clear and better understanding that will become to more comprehensive understanding of the present invention.
Description of drawings
Fig. 1 is the block diagram according to the frequency synthesizer of first embodiment of the invention.
Fig. 2 is first execution mode in conjunction with voltage controlled oscillator of the present invention.
Fig. 3 is the block diagram according to digital frequency detector of the present invention.
Fig. 4 is the inearized model according to frequency synthesizer of the present invention.
Fig. 5 is second embodiment according to frequency synthesizer of the present invention.
Embodiment
Come the preferred embodiments of the present invention are described below with reference to accompanying drawing.
With reference to figure 1, comprise a variable oscillator 11 according to frequency synthesizer 10 of the present invention or clock synthesizer, wherein said oscillator is a voltage controlled oscillator (VCO) preferably, and it has the first control input end 11a and the second control input end 11b.VCO11 produces the oscillator output signal that a frequency depends on its first and second control input ends 11a and 11b.
Frequency synthesizer 10 also comprises an analogue phase detector 13 and a digital beat frequency detector (FDD) 15.Preferably, analogue phase detector 13 is also referred to as phase-frequency detector PFD sometimes, and it comprises a charge pump that does not show separately.Described analogue phase detector 13 has first and second phase-detection input 13a and the 13b, and can be used for producing one first control signal, described first control signal representative is applied to the phase difference of the signal of its first and second phase-detection input 13a and 13b.Numeral beat frequency detector 15 has first and second frequency detecting input 15a and the 15b, and it can be used for producing second control signal, and described second control signal representative is applied to the signal frequency difference of its first and second frequency detecting input 15a and 15b.Be coupled with the first and second control input end 11a and the 11b of VCO11 respectively from first and second control signals of analogue phase detector 13 and digital beat frequency detector 15.Preferably, first control signal of analogue phase detector 13 is coupled to the first control input end 11a of VCO11 via analog loop filter 27.
It should be understood that from first control signal of analogue phase detector or 13 outputs of analogue phase/frequency detector are analog signals, it can represent the phase difference of a variation by a signal strength signal intensity that changes in proportion.Be also to be understood that in addition from second control signal of digital beat frequency detector 15 outputs are digital signals, described digital signal outputs on a single lead or the signal bus and has the numerical value of an expression frequency difference.
The input node 10a of frequency synthesizer 10 receives a reference frequency signal, and under present case, described reference frequency signal embodies with a reference input clock signal.If desired, reference input clock signal can be applied directly to the first phase-detection input 13a and first frequency detects input 15a, but comparatively preferably at first makes reference input clock signal by first frequency divider 21 its frequency progressively be reduced.The output of the synchronous divider 21 of this reference clock is applied to analogue phase detector 13 and digital beat frequency detector 15.Be also to be understood that in addition using frequency divider is a kind of design alternative that is used to reduce design complexity, for the present invention, this is not crucial.
Can directly feed back to the second phase-detection input 13b and second frequency with a kind of similar manner from the oscillator output signal of VCO11 and detect input 15b, but comparatively preferably still be that at first to make this output signal be that the synchronous divider 23 of VCO progressively reduces its frequency by second frequency divider.Under present case, oscillator output signal is promptly exported synchronous divider 25 by another frequency divider and is transmitted, so that produce the synchronous clock output signal of quilt of frequency synthesizer 10.
After this manner, frequency synthesizer 10 has been introduced a kind of analog phase-locked look (PLL) structure of routine, and it is by constituting from analogue phase detector 13 to VCO11 and the path that turns back to analogue phase detector 13.The present invention has also added one second digital loop to conventional PLL structure.Described digital loop is to be limited by digital beat frequency detector 15 to VCO11 and the path that turns back to beat frequency detector 15.And comparatively preferably, make the digital loop bandwidth be far smaller than the analogue loop bandwidth.In current embodiment, the analogue loop bandwidth is bigger 200 times than digital loop bandwidth at least.This total parametric difference is used in the design of VCO11, so that allow two independent control inputs, one of them is from analogue loop, and another is then from digital loop.
Therefore, the present invention has realized a kind of double loop controlled frequency synthesizer, and one of them loop is a digital loop, and another then is an analogue loop.In the first current embodiment, digital loop comprises all-digit frequency detector 15, it is controlled the centre frequency of VCO11 and has reduced thus the needed voltage swing of first control signal from analogue loop, has improved the capture range (pulling range) of VCO in addition.Analogue loop then comprises the analogue phase detector/charge pump 13 of low gain, and it adds phase coherence in the frequency control loop to, has eliminated any static frequency error thus.In fact, analogue loop has reduced the noise of Digital Logic and VCO11.The digital control frequency that then provides keeps and very low bandwidth.
As previously mentioned, second control signal is exported from digital beat frequency detector FDD15, and it can be placed in one and provide on the numerically controlled signal bus for VCO11.With reference to figure 2, shown that wherein a kind of being suitable for receives the example execution mode of a digital control bus 31 as its second control input end 11b from FDD15.
Present embodiment used a current limliting, cross-linked phase inverter is to, LC and CMOS oscillator, wherein oscillator frequency is controlled by the first control input end 13a of the analog signal VCTL that sends self simulation phase detectors 13 and sends the second control input end 13b from the digital control bus signals of FDD15.First phase inverter INV1 (comprising PMOS transistor P1 and nmos pass transistor N1) and the second phase inverter INV2 (comprising PMOS transistor P2 and nmos pass transistor N2) cross-couplings.Flow through the current limited of phase inverter INV1 and INV in current source, i.e. electric current w tail (current tail) I1, wherein said current source comprises nmos pass transistor N3 and is set by a bias voltage signal Vbias.Inductor L1 is coupled by the output of cross-over connection INV1 and INV2.The frequency of VCO11 then is to regulate by adjusting two independent electric capacity parameters.
The first electric capacity parameter is embodied D1 and D2 by a variable capacitance diode, and described variable capacitance diode changes its capacitance according to control voltage VCTL.Variable capacitance diode has formed a LC oscillating circuit (LC tank) thus to D1/D2 and inductor L1 parallel coupled.
The second electric capacity parameter is by capacitor C
i～C
pArray connect and cut off that pierce circuit embodies, wherein to connect and cut off be according to the value on the respective bit line bi～bp that is included in digital control bus 31, undertaken by corresponding crystal pipe Mi～Mp.Therefore, the digital controlled signal from FDD15 is coupled to and is located away from this oscillating circuit with particular comparator array Ci～Cp selectively.In the present embodiment, the array of capacitor Ci～Cp is returned to the drain electrode of tail current transistor N3, just capacitor Ci～Cp is coupled to selectively the source electrode of transistor N3 from the output of INV1 and INV2.As selection, transistor/capacitor can also be returned to earth terminal to the array of Mi/Ci～Mp/Cp.This will enlarge tuning range, but might increase the noise in the oscillator.
The FDD15 of Fig. 1 can implement with distinct methods.For example, FDD15 can have such one type, wherein directly determines reference clock frequency and produce one array of capacitors and the needed digital control value of control switch Mi/Ci～Mp/Cp are set.Yet this need use the equivalent of the coefficient set of the frequency of oscillation that makes each numerical value be related to VCO11, and this utmost point depends on manufacturing process, voltage and variations in temperature.Therefore, what current preferred FDD embodiment taked is a kind of diverse ways, and has only produced a frequency difference designator, so that the capacitance of the array of increasing or decreasing capacitor Ci～Cp.
With reference to figure 3, block structure according to digital beat frequency detector FDD15 of the present invention preferably includes two binary system ripple counters 41 and 43, these two all has the RESET input that is controlled by sequential state machine 45, and described state machine is a part that is used for control logic circuit that the operation of the various logic parts that constitute FDD15 is coordinated. Ripple counter 41 and 43 is to increase progressively on the edge (rise or decline logic edge) at the signal that is applied to its respective input.The reference frequency signal (or frequency divider 21 provide its expression that progressively descends) that is applied to Fig. 1 input 10a be coupled to first with the reference clock input of door 47.First with door 47 that serve as is a shield door (masking gate), be used for allowing selectively to be applied to the reference frequency signal process of its reference clock input, and make it perhaps to stop this reference frequency signal selectively and stop increasing progressively of ripple counter 41 according to by RUN/STOP (moving/stop) the control signal 51 determined inputs that are applied to ripple counter 41 like that from sequential state machine 45.Equally, be coupled with a VCO input end of clock of door 49 with second from the oscillator output signal of VCO11 (or its progressively reduction that provides of frequency divider 23 is represented), described and door serves as a secondary shielding door, so that optionally allow the oscillator output signal process, and as RUN/STOP control signal 51 is determined, it is applied to the input of ripple counter 43, or stops oscillator output signal selectively and stop increasing progressively of ripple counter 43.
After this manner, ripple counter 41 and 43 is counted the reference frequency signal (at reference clock input node) and the cycle of oscillator output signal (at the VCO clock input node) respectively.Counter 41 is binary counters of a n position, and 43 in counter is the binary counter of a m position, and wherein m is more than or equal to n+1.Two latchs 53 and 55 then serve as memory cell, so that monitor n and (n+1) position in the m position of counter 43, remember that in addition those any of reference count through position n and n+1 overflow.Latch 53 and 55 records be when n bit and/or (n+1) individual bit of counter 43 is transformed into logical one (supposing that counter 43 is count-up counters) from logic low 0.
Preferably, on the reference clock input, each rising edge of signal will cause counter 41 to increase progressively its counting, and on the VCO input end of clock, each rising edge of signal will cause counter 43 to increase progressively its counting.No matter when, as long as make the position, n position of counter 43 because increasing progressively counting operation, promptly become logic high, then set latch 53 and maintenance set, till it being removed by sequential state machine 45, and no matter whether the n position can change back to logic low because of the continuous counter of counter 43 after a while.No matter when, as long as set is carried out in (n+1) position to counter 43 owing to increase progressively counting operation, just become logic high, then latch 55 is carried out set and keeps set, till sequential state machine 45 is removed it.
The count value of counter 41 monitors that by a combinational logic network 57 described network is sent to sequential state machine 45 with information.Specifically, the n of combinational logic network 57 supervision counters 41 and (n-1) position.Reset (just becoming logic low again) in the n position of setting counter 41 (just being transformed into logic high) and to its n-1 position thus indicate when the n-1 position spills into the n position, sequential state machine 45 is to shield door 47 and 49 issue RUN/STOP signals, so that stop the counting operation that increases progressively of counter 41 and 43.This has freezed the count content of counter 41 and 43.
When stopping counter 41, the set situation of the count content of this counter and latch 53 and 55 is examined, and is used to determine as respectively in the relative frequency of reference clock input and observed reference frequency signal of VCO input end of clock and oscillator output signal.In current example, this judgement is made by one second combinational logic network 61.It should be understood that sequential state machine 45, first combinational logic circuit 57 and second combinational logic circuit 61 can be the integration sections of the general controls logical circuit of FDD15.If combinational logic network 61 determines that the oscillator output signal frequency is higher than the reference frequency signal frequency, it can send to first latch 1 with signal FAST (soon) so.If combinational logic network 61 determines that the oscillator output signal frequency is lower than the frequency of reference frequency signal, it can send to second latch 2 with signal SLOW (slowly) so.If combinational logic network 61 determines that the oscillator output frequency is locked in the frequency of reference frequency signal, it can send to the 3rd latch L3 with signal LOCK (locking) so.In response to from sequential state machine 45 issued command samples of signal, latch L1, L2 and L3 lock the signal that is sent out from combinational logic network 61.
If latch 53 and 55 is not set all, then the frequency from the oscillator output signal of VCO11 is defined as less than reference frequency signal.Must close latch 55 in addition, to guarantee not occur as yet the complete cycle of more than one counter 43.
If the counting operation that carries out in the counter 43 is than also many in the counter 41, then will be defined as frequency from the frequency of the oscillator output signal of VCO11 greater than reference frequency signal.If satisfied any one condition in two conditions, situation is like this.If set latch 53 and 55, indicate the overflowing of n position of a counter 43 therefrom, if perhaps set latch 55 and in the 2nd～n of counter 43 level, have any logic high, then the frequency of oscillator output signal is greater than the frequency of reference frequency signal.Do not check least significant bit (LSB) (just the 1st grade), because in described counting, because therefore the relative phase difference between oscillator output signal and the reference frequency signal can have a potential difference value.Under present case, have only the 1st grade just minimum the position be left in the basket so that consider the phase difference that this is possible.But the least significant bit (that is to say for example the 1st and 2 grade) that also can ignore other quantity is considered the phase difference that this is possible.
As selection, if set latch 53 and do not have set latch 55, if and in being lower than any position of counter 43 n positions less than the set logic height (except because possible phase difference and the uncared-for LSB position), then be defined as oscillator clock signal and reference frequency signal locked.
Making after this judges, can reset counter 41 and 43 and begin a new measuring period.The measurement of the relative frequency of or locked oscillator output signal and reference frequency signal fast, slow about the indication of storing among latch L1, L2 and the L3 will be sent to incremented/decremented counter 65.Then, sequential state machine 45 produces a clock signal that is used for incremented/decremented counter 65, so that the state that is latched is made response.
In the present embodiment, each of counter 65 is all controlled one among Fig. 2 corresponding switching transistor Mi～Mp.Described measurement is used to the described incremented/decremented counter 65 of increasing or decreasing, so that proofread and correct the centre frequency of VCO11.The change direction of incremented/decremented counter 65 depends on traction (pulling) slope of curve of VCO11.Slope among Fig. 2 is negative exemplary oscillator structure, if the frequency of the frequency ratio reference frequency signal of the oscillator output signal of described measurement indication VCO11 is slower, described counter then successively decreases.
More than describe demonstration, will carry out one-shot measurement every the individual reference clock input cycle of 2** (n-1).This measurement is the intrinsic low-pass filtering operation of frequency difference value.The real time constant of this filter response then depends on the reference clock input, i.e. the figure place of reference frequency signal [it determines to measure at interval], frequency difference and incremented/decremented counter 65.And filter bandwidht can be by increasing or reducing the figure place of counter and the incremented/decremented step-length of incremented/decremented counter is adjusted.
Can adjust the precision that frequency difference is measured by the figure place that changes in the counter 41 and 43, but in general, the figure place that is had there is no need far away more than the figure place in the incremented/decremented counter 65, i.e. the electric capacity step of oscillator.The figure place that changes counter 41 and 43 has also changed to be measured at interval.Between precision and filtering bandwidth, there is an inverse relationship.Increase and measure the capture time that has also increased loop at interval.Because measurement is to be determined by the transformation of reference clock input at interval, so losing of reference clock input can provide one to keep automatically for VCO11.In the dual-loop system of Fig. 1,, then must produce signal that an indication reference loses so that close the charge simulation pump if require to be kept.
With reference to figure 4, concerning dual loop frequency compositor system of the present invention, the inearized model of its simplification has an incoming frequency Fin who is applied to the first input end of frequency difference node 81, and described frequency is also converted to the relative phase of the first input end that is applied to phase difference node 85 by piece 83.Be applied to second input of frequency difference node 81 for the output of the VCO87 of Kv from gain.91 and 93 pairs of described frequency differences of level are taken a sample and are converted thereof into voltage with gain Kfdd.Convert a relative phase to by piece 95 and be applied to second input of phase difference node 85 from the output frequency of VCO87.This phase difference converts a voltage by level 97 to gain K φ, and wherein said level 97 can comprise phase detectors and the charge pump of Fig. 1.In level 99, level 97 output is with transfer function R (s) filtering and uses from the beat frequency detector output of level 93 and in summing junction 101 summations.The output of summing junction 101 is then controlled VCO87.
As shown, the frequency of VCO87 is exported 103 closures should numeral frequency difference loop, 105 closed analogue phase detector loops of its phase place output.This naive model can use on a circuit emulator, so that the effect of the formation bandwidth that comprises the VCO modulation bandwidth, filter characteristic, pump electric current etc. is checked.And the components values in the experiment test chip is selected in the emulation on the use step SPECTRE simulator.A frequency step input is applied to this model shows that then it all is the frequency step of a time delay that each frequency correction is measured, it makes this analogue loop make response.Selecting to measure interval, filter and pump electric current inadequately can make these two corrections vibrate in opposite direction.Yet, when the measurement that is used for digital frequency detector is that frequency sampling is compared with the bandwidth of analogue phase detection loop at interval when bigger at interval, can be when analogue loop is made response take the output Vf of frequency detector as a fixed value.Then, frequency transfer function becomes the fixed value and two sums [sKvVf/ (s+K φ R (s))]+[KvR (s) Fi/ (s+KfR (s))] that is used for the variable item of analog correction of FDD contribution.It is low to this means that gain K φ R must be retained as, so that allow the frequency detector loop arrange.
In order to test the frequency synthesizer structure that this is advised, used the Digital Logical Circuits technology of a kind of 0.18 μ m to construct chip here.In order to simplify oscillator design and to reduce needed inductor dimensions, two changes have been made at the VCO structure among Fig. 2 here.First change is to remove tail current source transistor N3.Concerning the inductor of constant magnitude, owing to increased the electric capacity to earth terminal of this gain transistor, so this has reduced frequency of oscillation.This has also increased the noise of oscillator.Yet the cross coupled inverters gain that increases on the oscillator of current limliting allows with the power filter that increases at the enterprising line operate of the voltage of a reduction.Second main variation is to use one 10 Bit-digital-analog converter (DAC113 among Fig. 5) and a voltage summing amplifier (115 among Fig. 5), so that produce the array (from Fig. 2) of an analog control voltage and removal transistor/capacitor Mi/Ci～Mp/Cp for oscillator.This is a simple design alternative, and it allows to reduce capture range and to increase noise is that cost is simplified the oscillator layout that is used for test chip.The diagram that has shown the test chip of being constructed in Fig. 5 is comprising the alternative embodiment of VCO11.
With reference to figure 5, all components similar to the assembly in Fig. 1～4 all has similar reference symbol and above obtaining description.In current preferred embodiment, the input reference frequency signal is implemented as a LVDS type signal that has the AC coupled of 100 ohm of R resistance difference terminations.As known in the art, Low Voltage Differential Signal (LVDS) is to use a kind of differential signal transmission technology to transmit information, and what wherein the first holding wire 135a carried is the true logic of signal, and what secondary signal line 135b carried is its logical inverse.Under present case, differential input signal 135a/135b has constituted reference frequency signal, and described differential input signal is by two capacitor Cin1 and Cin2 and be coupled to differential received machine 111 with capacitive way.Difference output driver 121 uses a kind of similar drive scheme that current drives is preferably 5mA that has.
In the present embodiment, differential received machine 111 converts the difference reference frequency signal of input 135a and 135b to the single-ended signal of the input 10a that is applied to frequency divider 21.This is a design alternative of having simplified the contrast of Fig. 5 embodiment and Fig. 1 embodiment.It should be understood that by using those appropriate difference modes structures that are used for its circuit block to come a differential input signal is not converted under the situation of single-ended signal, the embodiment of Fig. 1 and Fig. 5 can be used for this differential input signal is handled.
The same with the previous situation of Fig. 1, the single-ended reference frequency signal of Fig. 5 is applied to optional frequency divider 21, and the output of described frequency divider then is applied to analogue phase frequency detector 13 (having optional charge pump) and digital frequency detector 15.Similar to the embodiment of Fig. 1, the output of analogue phase detector 13 will submit to loop filter 27.Yet in present case, for simplified structure, the loop filter 27 on the charge pump output is made in chip exterior, and described loop filter is as comprising that the standard second order filter of capacitor Cf1, Cf2 and resistor R f1 implements.Under present case, it is second capacitor of 3pF that the parasitic capacitance of esd protection circuit (and not shown) has been used as filter 27 intermediate values.
In order to produce characteristic frequency, these three synchronous dividers 21,23 and 25 are implemented with a kind of shift register form rather than as binary divider.Divider 21,23 and 25 is built in two series connection parts synchronously, wherein first part can whole between 1 and 8 divide exactly than on produce 50% duty cycle pulse of nominal, described impulse feeding give can produce whole between 1 and 17 divide exactly than the second level.Here among the result who is reported, always the second level being set at is to remove by 1.
As indicated above, the output of digital FDD15 converts an analog representation to by digital to analog converter DAC113.115 pairs of outputs from digital FDD15 and simulation PFD13 of adder circuit are sued for peace, and described circuit produces a control signal 131, correspondingly adjusts the frequency of VCO11.
Also as mentioned above, VCO11 is simplified in current embodiment, and it has only comprised cross-linked phase inverter INV1 and INV2, varactor to D1/D2 and inductor L1.
The inductor that measures oscillator in the test chip of being constructed is at 3.1nH.Table I has shown some feature of experiment chip.Described chip is to operate on a voltage, has an independent input pin that is used for VCO Vdd.This power then is to arrive the simultaneously-measured of 1.1GHz at synthesizer lock.It should be noted that the summing amplifier passband has only 3MHz, and therefore represented the open-loop response upper limit of analogue phase detector loop.The size of frequency counter has then been determined the measurement interval of one 131 μ s, and it is used for the high frequency response minimum frequency step, 7.6KHz corresponding to one.
Table I experiment chip characteristics
| Technology | 18 μ m digital CMOSs | |
| Entire chip | Size is 2.8 * 2.8um | |
| Vdd | 1.8V | |
| Power [being in 1.1GHz] | Amount to | 100.8mw |
| VCO | 37mw | |
| Numeral FDD | 200μw | |
| The VCO frequency | Minimum 1.02GHz | Maximum 1.27GHz |
| The FDD characteristic | Area | 11mm[272×403μm] |
| Cycle rate counter | 17 | |
| Frequency | 10 | |
| The dead band | 1LSB | |
| Simulation PFD/CP | The pump electric current | 50μa |
| Summing amplifier | Bandwidth | 3MHz |
Measure to determine to operate simultaneously the influence that two loops are caused lock-in range and shake here.The lock-in range of operating with frequency loop separately is defined as stabilizing ring dataway operation zone.This is beat frequency detector indication locking and when only observing difference corresponding to 1 LSB in the frequency counter.Owing to, therefore do not used this definition here with the relevant phase place of this input.When these two loops were operated simultaneously, the zone of this locking was defined as and the relevant frequency range of this input.Shake then is to use an Agilent 86100A digital communication analyzer to measure, and described analyzer is combined into a measured numeral with shake deterministic and at random.
The inspection of the frequency spectrum of synthetic clock has been shown because frequency counter is carried out a large number of parasitic frequency composition that switch produced and the crossed product of these frequencies and reference clock frequency.This probably is because single power supply is used for analog-and digital-function and relative mistake ground separation number word noise causes.This has facilitated the shake of determining, and can not be with its separation in measured number.The low bandwidth of summing amplifier has limited analogue loop reduces this shake in combination manipulation mode ability.Yet as expected, shown a very big lock-in range through the line loop that makes up, and reduced the shake that causes owing to this analogue loop.
Table I I has shown the lock-in range and the shake of a function of the closed loop gain variation that is caused as change feedback divider ratio.The loop filter bandwidth that is used to simulate output is held constant at 1.6MHz, and the pump electric current also is like this, for use in the contrast purpose.In lock-in range, frequency than low value always between 1.02 to 1.03GHz.This demonstration: the operation of two loops has significantly improved lock-in range jointly, and has significantly improved the shake of RMS and peak to peak.The low bandwidth of digital frequency detector is coupled with the low gain of wide bandwidth analogue loop more, should improve at a jitter transfer function on the analogue loop of broadband only.
Table I I lock-in range and shake
| Gain | Has only FDD | FDD+ simulates PFD | ||||
| Lock-in range MHz | Shake RMS picosecond | Shake peak-to-peak value picosecond | Lock-in range MHz | Shake RMS picosecond | Shake peak-to- | |
| 1 | 35 | 5.8 | 16 | 6 | 3.8 | 15.6 |
| 2 | 170 | 4.2 | 8.5 | 155 | 2.5 | 6.8 |
| 3 | 182 | 4.2 | 8 | 209 | 3.7 | 6.9 |
| 4 | 184 | 4 | 8.2 | 246 | 3.2 | 6.6 |
| 5 | 180 | 3.8 | 21 | 196 | 1.5 | 6.6 |
Constructed a clock synthesizer in above-mentioned test chip, described synthesizer has used the digital beat frequency detector and the analogue phase detector/charge pump of operation simultaneously.Described digital beat frequency detector takies a negligible area and only expends considerably less power.Because the digital characteristic of described detector, so this detector is to provide the convergent-divergent possibility that is better than simple board design by photoetching technique.Even under the situation of not optimizing filtering, described test chip shows that small-sized analogue phase detector/charge pump has obviously improved the jittering characteristic of frequency controlled loop, but does not sacrifice any lock-in range.
The present invention describes with reference to the accompanying drawings and in conjunction with different preferred embodiments.According to the above description, different variations and modification all are conspicuous yet for a person skilled in the art.This change and modification are intended to the degree that falls into the claim scope and within the scope of the invention involved.
Claims (22)
1. frequency synthesizer comprises:
An input node is used to receive a reference frequency signal;
Variable oscillator with first input end and second input, it produces an oscillator output signal, and the frequency of described oscillator output signal depends on the described first and second control inputs;
Aanalogvoltage phase detectors, it has in response to the first phase-detection input of described reference frequency signal with in response to the second phase-detection input from the described oscillator output signal of described variable oscillator, described aanalogvoltage phase detectors can be used for producing first control signal of the phase difference between a described reference frequency signal of indication and the described oscillator output signal, described first control signal is coupled to first control input end of described variable oscillator, wherein analogue loop by along described first control signal from described aanalogvoltage phase detectors to described variable oscillator, and the signal path of getting back to described aanalogvoltage phase detectors along described oscillator output signal from described variable oscillator defines;
A digital beat frequency detector, it has in response to the first frequency detection input of described reference frequency signal and in response to the second frequency detection of described oscillator output signal imports, described digital beat frequency detector can be used for producing one second control signal, this second control signal is indicated the frequency difference between described reference frequency signal and the described oscillator output signal, described second control signal is coupled to described second control input end of described variable oscillator, wherein digital loop by along second control signal from described digital beat frequency detector to described variable oscillator, and the signal path of getting back to described digital frequency detector along described oscillator output signal from described variable oscillator defines;
The bandwidth of wherein said analogue loop is greater than the bandwidth of described digital loop.
2. the frequency synthesizer of claim 1, the bandwidth of wherein said analogue loop is bigger 200 times than the bandwidth of described digital loop at least.
3. the frequency synthesizer of claim 1, wherein said variable oscillator is a voltage controlled oscillator.
4. the frequency synthesizer of claim 1 also comprises a filter, and wherein said first control signal is via described filter coupled to described first control input end.
5. the frequency synthesizer of claim 1 also comprises one first frequency divider, wherein:
The described input node that is used to receive described reference frequency signal is coupled to an input of described first frequency divider, and the output of described first frequency divider is coupled to the described first phase-detection input of described aanalogvoltage phase detectors, and the first phase-detection input of described thus aanalogvoltage phase detectors is that the described reference frequency signal via described first frequency divider is made response.
6. the frequency synthesizer of claim 5, the described first frequency that the output of wherein said first frequency divider is coupled to described digital beat frequency detector detects input, and the first frequency of described digital beat frequency detector detection input is that the described reference frequency signal via described first frequency divider is made response thus.
7. the frequency synthesizer of claim 1, also comprise one second frequency divider, it has a coupling so that receive the input of described oscillator output signal from described variable oscillator, and have the output that described second a phase-detection input with described aanalogvoltage phase detectors is coupled, the second phase-detection input of described thus aanalogvoltage phase detectors is that the described oscillator output signal via described second frequency divider is made response.
8. the frequency synthesizer of claim 7, the described second frequency that the output of wherein said second frequency divider also is coupled to described digital beat frequency detector detects input, and the second frequency of described digital beat frequency detector detection input is that the described oscillator output signal via described second frequency divider is made response thus.
9. the frequency synthesizer of claim 1, described second control input end of being coupled to described variable oscillator via a D-A converter from described second control signal of described digital beat frequency detector wherein, described D-A converter provides an analog representation from the digital output end of described digital beat frequency detector to described second control input end.
10. the frequency synthesizer of claim 9, wherein said variable oscillator comprises an adder, is used for the control signal of its first and second control input end is added together, so that produce a synthetic frequency control signal.
11. the frequency synthesizer of claim 1, wherein first and second control input ends of variable oscillator are separate, and described variable oscillator has the first and second frequency adjusting mechanisms of importing in response to described first and second controls independently at least respectively.
12. the frequency synthesizer of claim 11, wherein said first frequency adjusting mechanism comprises a varactor in response to the described first control input, and wherein said second frequency adjusting mechanism comprises at least one capacitor, it is imported in response to described second control, and is coupled to described variable oscillator or separation with it conditionally.
13. the frequency synthesizer of claim 1, wherein said digital beat frequency detector comprises:
A n digit counter is used for the pulse that detects the input reception at described first frequency is counted, and described thus n digit counter keeps the step-by-step counting of described reference frequency signal;
A m digit counter is used for counting detect the pulse that input receives at described second frequency, and described thus m digit counter keeps the step-by-step counting of described oscillation output signal, and wherein m greater than n;
One first memory cell, be used for becoming first logic state and storing a set situation in response to the n bit map in the described m digit counter, and no matter described first logic state is left in the described n bit map in the described m digit counter, and keep described set situation;
One second memory cell is used for storing a set situation in response to the n+1 bit map in the described m digit counter becomes described first logic state, and no matter described first logic state is left in described n+1 bit map, and keep described set situation;
Wherein said n digit counter becomes described first logic state to be suspended with the n bit map that described m digit counter is in response in the described n digit counter; And
Wherein one suspends described n digit counter and described m digit counter, and described beat frequency detector is just determined:
If a) described first or second memory cell does not have the set situation of described storage; Then the output frequency of described variable oscillator is lower than described reference frequency signal; Perhaps
B) if described second memory cell has the set situation of described storage, then the output frequency of described variable oscillator is higher than described reference frequency signal; Perhaps
C) arbitrary position is set into described first logic state in the set situation of described storage and the described m digit counter except the least significant bit of predetermined quantity if described first memory cell has, and then the output frequency of described variable oscillator is higher than described reference frequency signal; Perhaps
D) described second memory cell does not have the set situation of described storage if described first memory cell has the set situation of described storage, and whom does not have be set into described first logic state in the described m digit counter except the least significant bit of described predetermined quantity, then the output frequency of described variable oscillator is locked into described reference frequency signal.
14. the frequency synthesizer of claim 13, wherein the described predetermined quantity of least significant bit is 1, one suspends described n digit counter and m digit counter thus, described digital beat frequency detector is just determined: if described first memory cell has and is higher than primary arbitrary position in the set situation of described storage and the described m digit counter and is set into described first logic state, the output frequency of so described variable oscillator is higher than described reference frequency signal.
15. the frequency synthesizer of claim 13, wherein:
Described first and second memory cell are respectively first and second latchs;
Described first and second latchs are by set, promptly lock, and described set situation is stored described set situation; And
Described first and second latchs can become reset case by set, and remove described set situation selectively.
16. the frequency synthesizer of claim 15, wherein said first and second latchs are set to described set situation by locking one of logic high state and logic low state, and described first and second latchs are to be set into described reset case by locking the described logic high state opposite with described set situation with another state in the logic low state.
17. the frequency synthesizer of claim 15, wherein said digital beat frequency detector also comprises a control logic circuit, and wherein:
Described first latch is in response to described control logic circuit and is reset;
Described second latch is in response to described control logic circuit and is reset; And
Described first and second latchs be the output frequency according to described variable oscillator be lower than, greater than or lock onto described reference frequency signal determine be reset.
18. the frequency synthesizer of claim 17, wherein said digital beat frequency detector also comprises:
One first shield door, it makes response to described control logic circuit, and can be used for as described that control logic circuit is determined to be detected input with described first frequency like that selectively and be coupled to or be located away from described n digit counter, wherein when described first shield door detects described first frequency input and is coupled to described n digit counter, described n digit counter is counted the pulse that detects the input reception at described first frequency, and when described first shield door detects described first frequency input and is located away from described n digit counter, described n digit counter stops the pulse that detects the input reception at described first frequency is counted, and suspends described n digit counter thus; And
A secondary shielding door, it makes response to described control logic circuit, and can be used for as described that control logic circuit is determined to be detected input with described second frequency like that selectively and be coupled to or be located away from described m digit counter, wherein when the described second frequency of described secondary shielding goalkeeper detects input and is coupled to described m digit counter, described m digit counter is counted the pulse that detects the input reception at described second frequency, and when the described second frequency of described secondary shielding goalkeeper detects input and is located away from described m digit counter, described m digit counter stops the pulse that detects the input reception at described second frequency is counted, and suspends described m digit counter thus.
19. the frequency synthesizer of claim 17, wherein said digital beat frequency detector also comprises an incremented/decremented counter, and described control logic circuit instructs described incremented/decremented counter:
Be higher than described reference frequency signal if determine the output frequency of described variable oscillator, then carry out a counting step change on the direction in the increasing or decreasing direction;
Be lower than described reference frequency signal if determine the output frequency of described variable oscillator, then carry out a counting step change on another direction in described increasing or decreasing direction; Perhaps
Lock onto described reference frequency signal if determine the output frequency of described variable oscillator, then remain unchanged;
The output of wherein said incremented/decremented counter is coupled to described variable oscillator.
20. the frequency synthesizer of claim 19, wherein:
The output frequency of described variable oscillator depends on enables or forbids a plurality of capacitors, and each capacitor in wherein said a plurality of capacitors is in response to corresponding electric capacity control input end and is activated and forbids, and
Described incremented/decremented counter places its current count value on the output bus, described output bus constitutes described second control signal, position independent in the wherein said output bus is coupled to independent electric capacity control input end, so that revise the frequency of described variable oscillator.
21. the frequency synthesizer of claim 19, wherein:
The output frequency of described variable oscillator depends on input is adjusted in a coupling with the frequency that receives described second control signal signal strength signal intensity;
The output of described incremented/decremented counter is applied to a D-A converter, so that produce described second control signal.
22. the frequency synthesizer of claim 19, wherein:
Described digital beat frequency detector provides an intrinsic low pass filter, is used for carrying out filtering to reference frequency signal and from the frequency difference between the oscillator output signal of described variable oscillator; And
The incremented/decremented step-length scalable of the bandwidth of described intrinsic low pass filter by increasing or reducing the value of the n in the described n digit counter and adjust described incremented/decremented counter.
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| Application Number | Priority Date | Filing Date | Title |
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| US45985403P | 2003-04-01 | 2003-04-01 | |
| US60/459854 | 2003-04-01 | ||
| US10/796,331 US7349514B2 (en) | 2003-04-01 | 2004-03-08 | Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector |
| US10/796331 | 2004-03-08 |
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| Publication Number | Publication Date |
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| CN1540868A true CN1540868A (en) | 2004-10-27 |
| CN100367672C CN100367672C (en) | 2008-02-06 |
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| CNB2004100332446A Expired - Fee Related CN100367672C (en) | 2003-04-01 | 2004-03-31 | Frequency synthesizer of using all-digit frequency detector and analogue phase detector |
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| Country | Link |
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| US (1) | US7349514B2 (en) |
| JP (1) | JP2004312726A (en) |
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Also Published As
| Publication number | Publication date |
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| JP2004312726A (en) | 2004-11-04 |
| US7349514B2 (en) | 2008-03-25 |
| CN100367672C (en) | 2008-02-06 |
| US20040223575A1 (en) | 2004-11-11 |
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