CN117716644A

CN117716644A - Clock synchronization method, device, system and chip

Info

Publication number: CN117716644A
Application number: CN202180100996.1A
Authority: CN
Inventors: 章成旻
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2024-03-15
Also published as: WO2023004576A1

Abstract

The application discloses a clock synchronization method, a clock synchronization device, a clock synchronization system and a clock synchronization chip, wherein the clock synchronization method comprises the following steps: the second pulse signal and the clock synchronization protocol message are received, the time stamp information can be obtained by analyzing the clock synchronization protocol message, and the fractional frequency division phase-locked loop circuit is utilized to divide the frequency of the first reference clock signal, so that a plurality of first sub-clock signals are obtained. Sampling the second pulse signals by using a plurality of first sub-clock signals to obtain a plurality of first sampling signals; taking a first jump edge of the first sampling signal as a sampling point, and determining a plurality of first sampling values of a plurality of first sampling signals at the sampling point; clock synchronization is achieved based on the time stamp information and the plurality of first sample values. After the decimal frequency division phase-locked loop circuit is adopted to divide the frequency of the first reference clock signal, the second pulse signal can be sampled with higher precision by utilizing a plurality of first sub-clock signals, the sampling precision can be improved, and then the clock synchronization precision is improved.

Description

Clock synchronization method, device, system and chip

Technical Field

The present disclosure relates to the field of distributed network technologies, and in particular, to a clock synchronization method, device, system, and chip.

Background

The clock synchronization system can accurately synchronize real-time clocks of all nodes in the distributed network communication, taking a clock synchronization system adopting a precision clock synchronization protocol standard (standard for a precision clock synchronization protocol for networked measurement and control systems, IEEE 1588) as an example, in the clock synchronization system, each node of the distributed network is provided with a clock module and a processing module, wherein the processing module is used for carrying out relevant protocol processing of IEEE 1588 messages and collecting time stamps, and sending the time stamps to the clock module, and the clock module is used for carrying out operation of clock information based on the time stamps sent by the processing module, so as to adjust the local real-time clock, thereby realizing clock synchronization of all nodes. The clock module periodically transmits time stamp information and Pulse Per Second (PPS) information to the processing module, thereby synchronizing the real-time clock of the processing module with the clock module.

The IEEE 1588 synchronous system has very high requirement on sampling precision, and the currently required sampling precision is in nanosecond level, wherein the sampling precision of second pulse information is an important factor affecting the precision of the whole IEEE 1588 synchronous system. The sampling accuracy of the second pulse information is completely dependent on the clock frequency of the sampling clock, that is, the sampling accuracy of the second pulse information can only be improved by increasing the clock frequency of the sampling clock. For example, to meet the accuracy requirement of the IEEE 1588 synchronization system, a sampling clock with a clock frequency of 1GHz is required to achieve 1ns of sampling accuracy of the second pulse information. However, under the existing clock processing technology, the implementation cost of the 1GHz clock is too high, but the sampling precision of the clock with lower cost processing is difficult to meet the precision requirement of the IEEE 1588 synchronous system. In view of this, it is a need in the art to ensure higher accuracy sampling requirements when the clock frequency of the sampling clock is low.

Disclosure of Invention

The application provides a clock synchronization method, a clock synchronization device, a clock synchronization system and a clock synchronization chip, which can ensure higher-precision sampling when the clock frequency of a sampling clock is lower.

In a first aspect, the present application provides a clock synchronization method, including: receiving a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information; dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; sampling the second pulse signals by using a plurality of first sub-clock signals to obtain a plurality of first sampling signals; determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking the first skip edge of each first sampling signal as the sampling point; clock synchronization is performed based on the time stamp information and the plurality of first sample values.

According to the clock synchronization method provided by the embodiment of the application, the decimal frequency division phase-locked loop circuit is adopted to divide the frequency of the first reference clock signal, and N first sub-clock signals clk 1-clkN can be obtained; and sampling the second pulse signal by using the first sub-clock signal to obtain first sampling signals Q1-QN. Determining a plurality of first sampling values of the plurality of first sampling signals at sampling points according to the first skip edges of the different first sampling signals Q1-QN as the sampling points; according to the jump edge position of the second pulse signal can be accurately determined according to the plurality of first sampling values, so that the current time can be accurately determined.

In some possible embodiments, sampling the second pulse signal with the plurality of first sub-clock signals includes: sampling the second pulse signal for N times by adopting a plurality of first sub-clock signals, and determining N groups of sampling results; wherein N is a positive integer; each set of sampling results includes a plurality of first sampling signals.

In practical application, the problem that the phase of the first sub-clock signals obtained by frequency division of the first reference clock signal may drift or be inaccurate may occur, after sampling the second pulse signal N times, if the phase of the first sub-clock signals does not drift, each set of sampling results in the N sets of sampling results are basically consistent, if the phase of the first sub-clock signals drift, the sampling average value may be determined through the total amount N of the sampling results and the multiple sets of sampling results, so that the problem that the sampling precision of the second pulse information is affected due to the drift or inaccuracy of the first sub-clock signals obtained after frequency division is avoided.

As one possible implementation, dividing the first reference clock signal by a fractional-n pll circuit to obtain a plurality of first sub-clock signals includes: four frequency division is carried out on the first reference clock signal by utilizing a fractional frequency division phase-locked loop circuit to obtain four first sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees.

As one possible implementation manner, the fractional frequency pll circuit includes: an inverter, a first frequency divider and a second frequency divider; an inverter for: generating a signal in phase opposition to the first reference clock signal based on the first reference clock signal; a first frequency divider for: dividing the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively 0 DEG and 180 DEG; a second frequency divider for: the signal with the opposite phase to the first reference clock signal is divided by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90 degrees and 270 degrees respectively.

In practical application, after the first reference clock signal is input into the inverter in the fractional-n phase-locked loop, the 0-degree and 180-degree phase clock signals are obtained, and the 0-degree and 180-degree phase clock signals respectively pass through the first frequency divider and the second frequency divider to obtain first sub-clock signals with initial phases of 0 °, 90 °, 180 ° and 270 ° respectively. In addition, the structure of the fractional-n pll circuit of the present application is not limited to this, and the inverter in the fractional-n pll circuit may also be a phase separation circuit, and the phase separation circuit may also generate a signal with a phase opposite to that of the first reference clock signal according to the first reference clock signal.

As a possible implementation, the first jump edge is a rising edge that jumps from low to high and/or a falling edge that jumps from high to low. Sampling the second pulse signal with a plurality of first sub-clock signals, comprising: the second pulse signal is sampled with a second trip edge of the plurality of first sub-clock signals, the second trip edge being a rising edge that trips from a low level to a high level and/or a falling edge that trips from a high level to a low level.

As a possible implementation manner, after obtaining the plurality of first sub-clock signals, the method further includes: a first multi-phase clock signal is generated from the plurality of first sub-clock signals, and the second pulse signal is sampled by the first multi-phase clock signal.

As a possible implementation manner, determining the timestamp information according to the plurality of second sampling values and the local time includes: when a sampling value with a set size appears in the second sampling values for the first time, determining the time stamp information according to the pulse period and the local time of the second pulse signal.

Because in the distributed network with higher precision requirement, the sampling error specified by the used clock synchronization protocol message is also lower. As a possible implementation, the sampling error specified by the clock synchronization protocol packet is not greater than ±0.5ns.

If the precision requirement of the IEEE 1588 synchronous system needs to be met, a sampling clock with the clock frequency of 1GHz is needed to sample the second pulse signal, the cost of producing a clock with the clock frequency of 1GHz is too high under the existing clock processing technology, and the existing clock with the clock frequency of 500MHz or less is common.

In a second aspect, the present application provides a clock synchronization method, applied to a master synchronization device, for dividing a second reference clock signal by using a fractional frequency pll circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; sampling the second pulse signals by using a plurality of second sub-clock signals to obtain a plurality of second sampling signals; determining a plurality of second sampling values of the second sampling signals at sampling points by taking the first jump edge of each second sampling signal as the sampling point; and determining the time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message which carries the time stamp information. The technical effects of the corresponding aspects in the second aspect may refer to the technical effects that may be obtained by the corresponding aspects in the first aspect, and the details will not be repeated.

As one possible implementation, sampling the second pulse signal with the plurality of second sub-clock signals includes: sampling the second pulse signal for N times by adopting a plurality of second sub-clock signals, and determining N groups of sampling results; wherein N is a positive integer; each set of sampling results includes a plurality of second sampling signals.

As a possible implementation manner, dividing the second reference clock signal by using a fractional frequency pll circuit to obtain a plurality of second sub-clock signals includes: four frequency division is carried out on the second reference clock signal by utilizing a fractional frequency division phase-locked loop circuit to obtain four second sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees.

As one possible implementation manner, the fractional frequency pll circuit includes: an inverter, a first frequency divider and a second frequency divider; an inverter for: generating a signal in phase opposition to the second reference clock signal based on the second reference clock signal; a first frequency divider for: dividing the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively 0 DEG and 180 DEG; a second frequency divider for: and dividing the signal with the phase opposite to that of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90 degrees and 270 degrees respectively.

As a possible implementation, the first jump edge is a rising edge that jumps from low to high and/or a falling edge that jumps from high to low.

As one possible implementation, sampling the second pulse signal with the plurality of first sub-clock signals includes: the second pulse signal is sampled with a second trip edge of the plurality of first sub-clock signals, the second trip edge being a rising edge that trips from a low level to a high level and/or a falling edge that trips from a high level to a low level.

As a possible implementation manner, after obtaining the plurality of first sub-clock signals, the method further includes: and generating a second multi-phase clock signal according to the plurality of second sub-clock signals, and sampling the second pulse signal by using the second multi-phase clock signal.

As a possible implementation, the sampling error specified by the clock synchronization protocol packet is not greater than ±0.5ns.

As a possible implementation, the clock frequency of the first reference clock signal is not higher than 500MHz.

In a third aspect, the present application further provides a clock synchronization device, including a packet and second pulse signal receiving module, configured to: receiving a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information; the frequency division module is used for: dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; a sampling module for: sampling the second pulse signals by using a plurality of first sub-clock signals to obtain a plurality of first sampling signals; a sampling value determining module, configured to: determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking the first skip edge of each first sampling signal as the sampling point; a clock synchronization module for: clock synchronization is performed based on the time stamp information and the plurality of first sample values. The technical effects of the corresponding aspects in the third aspect may refer to the technical effects that may be obtained by the corresponding aspects in the first aspect, and the details will not be repeated.

In a fourth aspect, the present application further provides a clock synchronization apparatus, including a frequency dividing module, configured to: dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; a sampling module for: sampling the second pulse signals by using a plurality of second sub-clock signals to obtain a plurality of second sampling signals; a sampling value determining module, configured to: determining a plurality of second sampling values of the second sampling signals at sampling points by taking the first jump edge of each second sampling signal as the sampling point; the message generation module is used for: and determining the time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message which carries the time stamp information. The technical effects of the corresponding aspects in the fourth aspect may refer to the technical effects that may be obtained by the corresponding aspects in the first aspect, and the details will not be repeated.

In a fifth aspect, the present application provides a chip comprising: the processor is connected with the memory, the memory stores an instruction program, and the processor is used for executing the following steps under the control of the instruction program: acquiring a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to acquire time stamp information; dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; sampling the second pulse signals by using a plurality of first sub-clock signals to obtain a plurality of first sampling signals; determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking the first skip edge of each first sampling signal as the sampling point; clock synchronization is performed based on the time stamp information and the plurality of first sample values. The technical effects of the corresponding aspects of the fifth aspect may be referred to the technical effects that may be obtained by the corresponding aspects of the first aspect, and the details will not be repeated.

In a sixth aspect, the present application provides a chip comprising: the processor is connected with the memory, the memory stores an instruction program, and the processor is used for executing the following steps under the control of the instruction program: dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; sampling the second pulse signals by using a plurality of second sub-clock signals to obtain a plurality of second sampling signals; determining a plurality of second sampling values of the second sampling signals at sampling points by taking the first jump edge of each second sampling signal as the sampling point; and determining the time stamp information according to the plurality of second sampling values and the local time, and generating a clock synchronization protocol message which carries the time stamp information. The technical effects of the corresponding aspects of the sixth aspect may be referred to the technical effects that may be obtained by the corresponding aspects of the second aspect, and the details will not be repeated.

In a seventh aspect, the present application provides a clock synchronization system, the clock synchronization system comprising: the second frequency division module is used for dividing the frequency of the second reference clock signal by utilizing the fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; the second sampling module is used for sampling the second pulse signals by using a plurality of second sub-clock signals to obtain a plurality of second sampling signals; the second sampling value determining module is used for determining a plurality of second sampling values of the second sampling signals at sampling points by taking the first skip edge of each second sampling signal as the sampling point; the message generating module is used for determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message to the message and second pulse signal receiving module, wherein the clock synchronization protocol message carries the time stamp information; the message and second pulse signal receiving module is used for receiving the second pulse signal sent by the message generating module and the clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information; the first frequency division module is used for dividing the frequency of the first reference clock signal by utilizing the fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; the first sampling module is used for sampling the second pulse signals by utilizing a plurality of first sub-clock signals to obtain a plurality of first sampling signals; the first sampling value determining module is used for determining a plurality of first sampling values of the first sampling signals at sampling points by taking the first skip edge of each first sampling signal as the sampling point; and the clock synchronization module is used for carrying out clock synchronization according to the time stamp information and the plurality of first sampling values. The technical effects of the corresponding aspects of the seventh aspect may be referred to the technical effects that may be obtained by the corresponding aspects of the first aspect and the second aspect, and the details will not be repeated.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

FIG. 1 is a flow chart of a clock synchronization method;

FIG. 2 is a timing diagram corresponding to a clock synchronization method;

FIG. 3 is a schematic diagram of a fractional-N PLL circuit;

FIG. 4 is a second flow chart of a clock synchronization method;

FIG. 5 is a schematic diagram of a clock synchronization device;

fig. 6 is a schematic diagram of another clock synchronization apparatus.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings. It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the embodiment of the present application, "and/or" describing the association relationship of the association object indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. Reference to at least one in this application refers to one or more; plural means two or more. In addition, it should be understood that in the description of this application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.

In a distributed network, one node among a plurality of nodes serves as a master synchronization device (master), and the other nodes serve as slave synchronization devices (slave), and the master synchronization device can synchronize reference time to all the slave synchronization devices. The master synchronization device sends an IEEE 1588 protocol message, the slave synchronization device can collect time stamp information according to the received protocol message, the slave synchronization device can determine time deviation between the slave synchronization device and the master synchronization device according to the time stamp information, and the slave synchronization device can adjust a real-time clock of the slave synchronization device, so that a clock module of the slave synchronization device is time-synchronized with the master synchronization device. And then, the slave synchronization equipment sends the time stamp information and the second pulse information to the processing module, and the slave synchronization equipment adjusts the real-time clock according to the time stamp information and the second pulse information, so that clock synchronization is finally realized.

However, in some distributed networks with high precision requirements, the sampling error specified by the clock synchronization protocol packet used will also be low. For example, to meet the accuracy requirement of the IEEE 1588 synchronization system, a sampling clock with a clock frequency of 1GHz is required to sample the second pulse signal, so that the sampling accuracy reaches 1ns. However, under the existing clock processing technology, the cost of producing a clock with the frequency of 1GHz is too high, and more common clocks with the frequency of less than 500MHz are also used, but the sampling precision of the clocks with the lower cost processing technology is difficult to meet the precision requirement of an IEEE 1588 synchronous system. In view of this, it is a urgent need in the art to ensure higher accuracy sampling requirements when the clock frequency of the sampling clock is low.

Fig. 1 is a flowchart of a clock synchronization method provided in an embodiment of the present application, fig. 2 is a timing chart corresponding to the clock synchronization method provided in an embodiment of the present application, and when the clock synchronization method in an embodiment of the present application is applied to a slave synchronization device in conjunction with fig. 1 and fig. 2, the method may include the following steps:

s101: and receiving the second pulse signal and the clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain the time stamp information.

The clock synchronization protocol message may include: high precision time synchronization protocol (precision time protocol, PTP) messages, universal precision time protocol (generalized precision time protocol,802.1 AS) messages, sync messages, follow_up follow messages, delay_req delay request messages or delay_resp delay response messages, etc. The sampling error specified by the clock synchronization protocol packet may be no greater than ±0.5ns, and a PTP type packet is used herein as an example, but the present application is not limited thereto, and those skilled in the art should understand that any clock synchronization protocol (no greater than ±0.5ns) with a high accuracy requirement may be applied in the present application, and the present application is not limited thereto too much. The second pulse signal can be generated by an external clock device or can be sent together with the master synchronous device.

The time stamp information master synchronization device is determined based on the current time, which is not limited to the world standard time (universal time coordinated, UTC) time, the global positioning system (global positioning system, GPS) time, and the like, and is not particularly limited herein.

S102: the first reference clock signal is divided by a fractional frequency phase-locked loop circuit to obtain a plurality of first sub-clock signals. The period of each first sub-clock signal is the same.

Wherein the first reference clock signal may be generated by an internal clock, optionally including: crystal oscillator, frequency multiplication circuit, phase discriminator, clock pulse circuit, input digital-to-analog converter, voltage controlled oscillator, etc. For example, the crystal oscillator may generate a clock signal at a reference frequency that is related to the particular structure of the crystal oscillator; the frequency doubling circuit is used for carrying out frequency doubling treatment on the reference frequency clock signal; the phase discriminator is used for carrying out phase discrimination on the frequency multiplication processed signal, the clock pulse circuit converts the phase discrimination signal into a clock pulse signal, the clock pulse signal is input into the digital-analog converter for converting the clock pulse signal into an analog clock pulse signal, and the voltage-controlled oscillator outputs a first reference clock signal according to the analog clock pulse signal. The above processing procedure of the clock signal of the reference frequency is only an example, and the connection relation of the devices in the internal clock is not limited, and the purpose of the processing procedure is to generate the clock signal of the specific frequency, and the specific generation manner is not limited, so those skilled in the art should know.

The existing frequency dividing circuit can divide the frequency of the first reference clock signal by adopting a delay loop (time to digital converter, TDC), if the TDC is used, the time counted after frequency division can be completely determined by a time counting chip (cell), but the time counting chip (cell) is dithered and has high uncertainty, and is greatly influenced by the condition of process voltage temperature (precess voltage temperature, PVT), so that the reliability of frequency division of the TDC is lower, 1.68% delay jitter is generated at most, and the delay jitter is accumulated due to the structure of the delay loop, so that larger error is caused.

The decimal frequency division phase-locked loop circuit is formed by adopting the analog device, is not influenced by process angle deviation and temperature, is of an open loop structure, can be better suitable for a high-speed clock scene, does not need to use a complex closed loop structure to realize the requirement of the high-speed clock scene, and has the advantages of low time delay and high precision.

With continued reference to fig. 2, as one possible implementation, the first reference clock signal is divided by four by a fractional-n pll circuit to obtain four first sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees. In fig. 2, the fractional-division pll circuit is used to divide the first reference clock signal by four, thereby obtaining four first sub-clock signals: a first sub-clock signal clk1, a first sub-clock signal clk2, a first sub-clock signal clk3, a first sub-clock signal clk4; wherein the phase difference of each adjacent clock signal is 90 deg.. It should be noted that, in the embodiment of the present application, the phase difference between the adjacent clock signals is 90 °, for example, the phase difference between the first sub-clock signal clk1 and the first sub-clock signal clk2 may have a certain deviation range, or in other words, the phase difference between the first sub-clock signal clk1 and the first sub-clock signal clk2 is approximately 90 °, and each first sub-clock needs to be kept synchronous. As a possible implementation, the clock frequency of the first reference clock signal is not higher than 500MHz. For example, for the purpose of improving the sampling accuracy, the number of the generated first sub-clock signals may be related to the clock frequency of the first reference clock signal, for example, when the clock frequency of the first reference clock signal is 500MHz, the fractional frequency division phase-locked loop circuit may divide the first reference clock signal by four to obtain four first sub-clock signals, and when the clock frequency of the first reference clock signal is 250MHz, the fractional frequency division phase-locked loop circuit may divide the first reference clock signal by eight to obtain eight first sub-clock signals.

S103: and sampling the second pulse signals by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals.

It should be noted that, in the embodiment of the present application, the second clock signal may be sampled by using the second transition edge, for example, the second transition edge may be a rising edge, that is, a transition edge from the low level (0) to the high level (1), and of course, the second transition edge may also be a falling edge, that is, a transition edge from the high level (1) to the low level (0), which is described herein by taking the second transition edge as an example for convenience of description. Illustratively, taking rising edge sampling as an example, the first sampling signal Q1 may be obtained after sampling the second pulse signal with the first sub-clock signal clk 1.

S104: and determining a plurality of first sampling values of the plurality of first sampling signals at the sampling points by taking the first skip edge of each first sampling signal as the sampling point.

And determining a first sampling value of the first sampling signal Q1 at the sampling point A by taking the first jump edge of the first sampling signal Q1 as the sampling point A. It should be noted that, in this embodiment of the present application, the sampling points refer to first transition edges of the first sampling signal, where the first transition edges are transition edges from the first value to the second value, for example, the first transition edges may be rising edges, that is, transition edges from low level (0) to high level (1), and of course, the first transition edges may also be falling edges, that is, transition edges from high level (1) to low level (0), which are all described herein for convenience of description.

S105: clock synchronization is performed based on the time stamp information and the plurality of first sample values.

After the plurality of first sampling values are obtained, determining the current time according to the sampling value of the time when the update is firstly acquired in the plurality of first sampling values and the time stamp information, thereby realizing clock synchronization.

In the distributed network, each device may include a clock synchronization module and a processing module, and the above steps S101 to S105 may be performed in the processing module, that is, the clock synchronization module periodically receives the time stamp information and the second pulse information from the master synchronization device and periodically transmits the time stamp information and the second pulse information to the processing module, and the processing module performs the above steps S101 to S105 after receiving the time stamp information and the second pulse information, thereby enabling the master synchronization device and the slave synchronization device to perform clock synchronization.

As a possible implementation manner, clock synchronization is performed according to the timestamp information and the plurality of first sampling values, which may be: when a sampling value with a set size appears in a plurality of first sampling values for the first time, determining the current time according to the pulse period of the second pulse signal and the time stamp information. By way of example, with continued reference to fig. 2, the embodiments of the present application may obtain four first sub-clock signals clk1 to clk4 by dividing the first reference clock by four; the second pulse signals are sampled by the four first sub-clock signals, so that first sampling signals Q1-Q4 can be obtained, and a plurality of first sampling values are obtained based on first transition edges of the first sampling signals Q1-Q4. For example, the pulse period of the second pulse signal is 1s, the time indicated by the time stamp information is 10:00:00, and when a sampling value of 1 occurs in the plurality of first sampling values, the current time change is determined to be 10:00:01 from the synchronization device. By using the mode, the jump edge position of the second pulse signal can be accurately determined, so that the current time can be accurately determined.

In addition, since the clock synchronization protocol message needs to consume a certain sending time from the master synchronization device to the slave synchronization device, when the real-time is calculated, the sending time can be taken as the compensation time and added into the time carried by the timestamp in advance, and then clock synchronization is performed after the compensation of the sending time; moreover, because the modes of sending the clock synchronization protocol messages are different, or the distances between the master synchronization device and the slave synchronization devices are different, the corresponding sending times are also different.

By way of example, the clock synchronization method provided in the embodiment of the present application uses a fractional frequency division phase-locked loop circuit to divide the first reference clock signal to obtain first sub-clock signals clk1 to clk4; the phase difference of each adjacent clock signal is 90 degrees, and the second pulse signals are sampled by the first sub-clock signals to obtain first sampling signals Q1-Q4. According to the first sampling values corresponding to different first sampling signals Q1-Q4, compared with the prior art, the method and the device for sampling the second pulse signal by using only one first reference clock signal, the sampling precision can be reduced to 1/N clock cycles of the first reference clock signals through N first sub-clock signals, and the sampling precision is improved to be N times of the original sampling precision.

In an actual scenario, the phase of the plurality of first sub-clock signals obtained by frequency division of the first reference clock signal may drift or be inaccurate, and as a possible implementation manner, the clock synchronization method provided in the embodiment of the present application may further include: sampling the second pulse signal for N times by adopting a plurality of first sub-clock signals, and determining N groups of sampling results; wherein N is a positive integer; each set of sampling results includes a plurality of first sampling signals.

That is, in the embodiment of the present application, after the steps S103 to S105 are performed N times, that is, after the second pulse signal is sampled N times by using the plurality of first sub-clock signals, if the phases of the plurality of first sub-clock signals do not drift, each set of sampling results in the N sets of sampling results are basically consistent, if the phases of the plurality of first sub-clock signals drift, the sampling average value may be determined by the total N of the sampling results and the plurality of sets of sampling results, so that the problem that the sampling accuracy of the second pulse information is affected due to drift or inaccuracy of the plurality of first sub-clock signals obtained after frequency division is avoided.

FIG. 3 is a schematic diagram of a fractional-N PLL circuit; referring to fig. 3, a first reference clock signal is input into an inverter in a fractional-n pll to obtain 0 ° and 180 ° phase clocks CLK0 and CLK1 thereof, CLK0 is passed through the first frequency divider to obtain CLK00 and CLK01 having a frequency of 1/2 and a phase of 0 ° and 180 °; CLK1 passes through the second frequency divider to obtain CLK10 and CLK11 with a frequency of 1/2, and phases of 90 ° and 270 °.

In addition, the structure of the fractional-n pll circuit is not limited to this, and the inverter in the fractional-n pll circuit may also be a phase separation circuit, where the phase separation circuit may also generate 0 ° and 180 ° phase clocks CLK0 and CLK1 according to the first reference clock signal, where the delay error of the phase separation circuit compared with the inverter is smaller, and the value of the phase separation circuit is generally less than 3ps, so that the phase separation circuit is more suitable for the high-precision clock synchronization protocol scenario of the present application.

As a possible implementation manner, after the obtaining the plurality of first sub-clock signals, the method further includes:

generating a first multi-phase clock signal according to the plurality of first sub-clock signals, and sampling the second pulse signal by using the first multi-phase clock signal.

Wherein the fractional-n pll circuit may further comprise: and the AND gate circuit is used for synthesizing a plurality of first sub-clock signals into a first multiphase clock. Illustratively, if CLK00, CLK01, CLK10 and CLK11 of the above embodiments are input to the and circuit, the and circuit obtains four-phase clocks having a frequency of half the first reference clock signal, a duty cycle of 25%, and an initial phase of 0 °,90 °,180 ° and 270 °.

Fig. 4 is a flowchart of a clock synchronization method provided in an embodiment of the present application, where the clock synchronization method in the embodiment of the present application is applied to a master synchronization device, may include:

s401: dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same;

s402: sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

s403: determining a plurality of second sampling values of the plurality of second sampling signals at the sampling points by taking the first jump edge of each second sampling signal as the sampling point;

s404: and determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message, wherein the clock synchronization protocol message carries the time stamp information. The possible implementation and beneficial effects of the embodiment of the present application refer to the above embodiment steps S101 to S105, and the repetition is not repeated, and those skilled in the art should know the repetition.

Referring to fig. 5, the present application provides a clock synchronization apparatus 500, which includes: the message and second pulse signal receiving module 501 is configured to: receiving a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information; a frequency division module 502, configured to: dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; a sampling module 503, configured to: sampling the second pulse signals by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; a sample value determining module 504, configured to: determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking a first jump edge of each first sampling signal as the sampling point; a clock synchronization module 505 for: and carrying out clock synchronization according to the time stamp information and the first sampling values.

Referring to fig. 6, the present application further provides a clock synchronization apparatus 600, which includes: a frequency division module 601, configured to: dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; a sampling module 602, configured to: sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals; a sampling value determining module 603, configured to: determining a plurality of second sampling values of the plurality of second sampling signals at the sampling points by taking the first jump edge of each second sampling signal as the sampling point; the message generating module 604 is configured to: and determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message, wherein the clock synchronization protocol message carries the time stamp information.

It should be noted that, in the embodiment of the present application, the division of the modules is merely schematic, and there may be another division manner in actual implementation, and each functional module in the examples of the present application may be integrated in one processing module, or each module may exist separately and physically, or two or more units may be integrated in one unit. The integrated modules can be realized in a form of hardware or a form of software functional modules.

The application also provides a clock synchronization system, which comprises: the second frequency division module is used for dividing the frequency of the second reference clock signal by utilizing the fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; the second sampling module is used for sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals; the second sampling value determining module is used for determining a plurality of second sampling values of the plurality of second sampling signals at sampling points by taking the first skip edge of each second sampling signal as the sampling point; the message generating module is used for determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message to the message and second pulse signal receiving module, wherein the clock synchronization protocol message carries the time stamp information; the message and second pulse signal receiving module is used for receiving the second pulse signal sent by the message generating module and the clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information; the second frequency division module is used for dividing the frequency of the first reference clock signal by utilizing the fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; the second sampling module is used for sampling the second pulse signals by utilizing the plurality of first sub-clock signals to obtain a plurality of first sampling signals; the second sampling value determining module is used for determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking the first skip edge of each first sampling signal as the sampling point; and the clock synchronization module is used for carrying out clock synchronization according to the time stamp information and the plurality of first sampling values.

The application also provides a chip, a processor and a memory, wherein the processor is connected with the memory, the memory stores an instruction program, and the processor is used for executing the following steps under the control of the instruction program: acquiring a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to acquire time stamp information; dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same; sampling the second pulse signals by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking a first jump edge of each first sampling signal as the sampling point; and carrying out clock synchronization according to the time stamp information and the first sampling values.

The application also provides a chip comprising: the processor is connected with the memory, the memory stores an instruction program, and the processor is used for executing the following steps under the control of the instruction program: dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same; sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals; determining a plurality of second sampling values of the plurality of second sampling signals at the sampling points by taking the first jump edge of each second sampling signal as the sampling point; and determining the time stamp information according to the plurality of second sampling values and the local time, and generating a clock synchronization protocol message, wherein the clock synchronization protocol message carries the time stamp information.

Based on the above embodiments, the present application further provides a computer program, which when run on a computer, causes the computer to execute the clock synchronization method provided in the above embodiments.

Based on the above embodiments, the present application further provides a computer-readable storage medium having stored therein a computer program which, when executed by a computer, causes the computer to execute the clock synchronization method provided in the above embodiments.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

A clock synchronization method applied to a slave synchronization device, the method comprising:

receiving a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information;

dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same;

sampling the second pulse signals by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals;

determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking a first jump edge of each first sampling signal as the sampling point;

and carrying out clock synchronization according to the time stamp information and the first sampling values.
The method of claim 1, wherein sampling the second pulse signal with the plurality of first sub-clock signals comprises:

sampling the second pulse signal for N times by adopting the plurality of first sub-clock signals, and determining N groups of sampling results; wherein, N is a positive integer; each set of the sampling results includes the plurality of first sampling signals.
The method according to claim 1 or 2, wherein dividing the first reference clock signal by the fractional-n phase-locked loop circuit to obtain a plurality of first sub-clock signals comprises:

four frequency division is carried out on the first reference clock signal by utilizing a fractional frequency division phase-locked loop circuit to obtain four first sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees.
A method according to claim 3, wherein the fractional-n phase-locked loop circuit comprises: an inverter, a first frequency divider and a second frequency divider;

the inverter is used for: generating a signal in phase opposition to a first reference clock signal based on the first reference clock signal;

the first frequency divider is used for: dividing the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively 0 DEG and 180 DEG;

the second frequency divider is used for: the signal with the opposite phase to the first reference clock signal is divided by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90 degrees and 270 degrees respectively.
The method according to any of claims 1-4, wherein the first jump edge is a rising edge that jumps from low to high and/or a falling edge that jumps from high to low.
The method of any of claims 1-5, wherein sampling the second pulse signal with the plurality of first sub-clock signals comprises:

the second pulse signal is sampled by using a second jump edge of the plurality of first sub-clock signals, wherein the second jump edge is a rising edge which jumps from a low level to a high level and/or a falling edge which jumps from the high level to the low level.
The method of any of claims 1-6, wherein after the deriving the plurality of first sub-clock signals, the method further comprises:

generating a first multi-phase clock signal according to the plurality of first sub-clock signals, and sampling the second pulse signal by using the first multi-phase clock signal.
The method of any of claims 1-7, wherein the clock synchronizing based on the time stamp information and the first plurality of sample values comprises:

and when the sampling value with the set size appears in the first sampling values for the first time, determining the current time according to the pulse period of the second pulse signal and the time stamp information.
The method according to any of claims 1-8, wherein the clock synchronization protocol message specifies a sampling error of no more than ± 0.5ns.
The method according to any of claims 1-9, wherein the clock frequency of the first reference clock signal is not higher than 500MHz.
A clock synchronization method applied to a master synchronization device, the method comprising:

dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same;

sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

determining a plurality of second sampling values of the plurality of second sampling signals at the sampling points by taking the first jump edge of each second sampling signal as the sampling point;

and determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message, wherein the clock synchronization protocol message carries the time stamp information.
The method of claim 11, wherein sampling the second pulse signal with the plurality of second sub-clock signals comprises:

Sampling the second pulse signal for N times by adopting the plurality of second sub-clock signals, and determining N groups of sampling results; wherein, N is a positive integer; each set of the sampling results includes the plurality of second sampling signals.
The method of claim 11 or 12, wherein dividing the second reference clock signal by the fractional-n phase-locked loop circuit to obtain a plurality of second sub-clock signals comprises:

four frequency division is carried out on the second reference clock signal by utilizing a fractional frequency division phase-locked loop circuit to obtain four second sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees.
The method of claim 13, wherein the fractional-n phase-locked loop circuit comprises: an inverter, a first frequency divider and a second frequency divider;

the inverter is used for: generating a signal in phase opposition to a second reference clock signal based on the second reference clock signal;

the first frequency divider is used for: dividing the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively 0 DEG and 180 DEG;

The second frequency divider is used for: and dividing the signal with the phase opposite to that of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90 degrees and 270 degrees respectively.
The method according to any of claims 11-14, wherein the first jump edge is a rising edge that jumps from low to high and/or a falling edge that jumps from high to low.
The method of any of claims 11-15, wherein sampling the second pulse signal with the first plurality of sub-clock signals comprises:

the second pulse signal is sampled by using a second jump edge of the plurality of first sub-clock signals, wherein the second jump edge is a rising edge which jumps from a low level to a high level and/or a falling edge which jumps from the high level to the low level.
The method of any of claims 11-16, wherein after the deriving the plurality of first sub-clock signals, the method further comprises:

generating a second multi-phase clock signal according to the plurality of second sub-clock signals, and sampling the second pulse signal by using the second multi-phase clock signal.
The method according to any of claims 11-17, wherein said determining timestamp information from said plurality of second sample values and a local time comprises:

and when the sampling value with the set size appears in the second sampling values for the first time, determining the time stamp information according to the pulse period of the second pulse signal and the local time.
The method according to any of claims 11-18, wherein the clock synchronization protocol message specifies a sampling error of not more than ±0.5ns.
The method according to any of claims 11-19, wherein the clock frequency of the first reference clock signal is not higher than 500MHz.
A clock synchronization device, the device comprising:

the message and second pulse signal receiving module is used for: receiving a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information;

the frequency division module is used for: dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same;

a sampling module for: sampling the second pulse signals by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals;

A sampling value determining module, configured to: determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking a first jump edge of each first sampling signal as the sampling point;

a clock synchronization module for: and carrying out clock synchronization according to the time stamp information and the first sampling values.
The apparatus of claim 21, wherein the apparatus comprises:

the sampling module is specifically configured to: sampling the second pulse signal for N times by adopting the plurality of first sub-clock signals, and determining N groups of sampling results; wherein, N is a positive integer; each set of the sampling results includes the plurality of first sampling signals.
The apparatus according to claim 21 or 22, wherein the frequency dividing module is specifically configured to:

four frequency division is carried out on the first reference clock signal by utilizing a fractional frequency division phase-locked loop circuit to obtain four first sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees.
The apparatus of claim 23, wherein the fractional-n phase-locked loop circuit comprises: an inverter, a first frequency divider and a second frequency divider;

The inverter is used for: generating a signal in phase opposition to a first reference clock signal based on the first reference clock signal;

the first frequency divider is used for: dividing the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively 0 DEG and 180 DEG;

the second frequency divider is used for: the signal with the opposite phase to the first reference clock signal is divided by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90 degrees and 270 degrees respectively.
The apparatus according to any of claims 21-24, wherein the first jump edge is a rising edge that jumps from low to high and/or a falling edge that jumps from high to low.
The apparatus according to any of the claims 21-25, wherein the sampling module is specifically configured to:

the second pulse signal is sampled by using a second jump edge of the plurality of first sub-clock signals, wherein the second jump edge is a rising edge which jumps from a low level to a high level and/or a falling edge which jumps from the high level to the low level.
The apparatus of any one of claims 21-26, wherein the clock synchronization apparatus further comprises: and the signal synthesis module is used for generating a first multi-phase clock signal according to the plurality of first sub-clock signals and sampling the second pulse signal by using the first multi-phase clock signal.
The apparatus according to any of the claims 21-27, wherein the clock synchronization module is specifically configured to:

and when the sampling value with the set size appears in the first sampling values for the first time, determining the current time according to the pulse period of the second pulse signal and the time stamp information.
A clock synchronization device, the device comprising:

the frequency division module is used for: dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same;

a sampling module for: sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

a sampling value determining module, configured to: determining a plurality of second sampling values of the plurality of second sampling signals at the sampling points by taking the first jump edge of each second sampling signal as the sampling point;

The message generation module is used for: and determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message, wherein the clock synchronization protocol message carries the time stamp information.
The apparatus of claim 29, wherein the sampling module is specifically configured to: sampling the second pulse signal for N times by adopting the plurality of second sub-clock signals, and determining N groups of sampling results; wherein, N is a positive integer; each set of the sampling results includes the plurality of second sampling signals.
The apparatus according to claim 29 or 30, wherein the frequency dividing module is specifically configured to:

four frequency division is carried out on the second reference clock signal by utilizing a fractional frequency division phase-locked loop circuit to obtain four second sub-clock signals; the phase difference of two adjacent first sub-clock signals after frequency division is 90 degrees.
The apparatus of claim 31, wherein the fractional-n phase-locked loop circuit comprises: an inverter, a first frequency divider and a second frequency divider;

the inverter is used for: generating a signal in phase opposition to a second reference clock signal based on the second reference clock signal;

The first frequency divider is used for: dividing the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively 0 DEG and 180 DEG;

the second frequency divider is used for: and dividing the signal with the phase opposite to that of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 90 degrees and 270 degrees respectively.
The apparatus according to any of claims 29-32, wherein the first jump edge is a rising edge that jumps from low to high and/or a falling edge that jumps from high to low.
The apparatus according to any one of claims 29-33, wherein the sampling module is specifically configured to:

the second pulse signal is sampled by using a second jump edge of the plurality of first sub-clock signals, wherein the second jump edge is a rising edge which jumps from a low level to a high level and/or a falling edge which jumps from the high level to the low level.
The apparatus of any one of claims 29-34, wherein the clock synchronizing device further comprises: and the signal synthesis module is used for generating a second multi-phase clock signal according to the plurality of second sub-clock signals and sampling the second pulse signal by using the second multi-phase clock signal.
The apparatus according to any one of claims 29-35, wherein the message generation module is specifically configured to:

and when the sampling value with the set size appears in the second sampling values for the first time, determining the time stamp information according to the pulse period of the second pulse signal and the local time.
A chip, comprising: the processor is connected with the memory, the memory stores an instruction program, and the processor is used for executing the following steps under the control of the instruction program:

acquiring a second pulse signal and a clock synchronization protocol message, and analyzing the clock synchronization protocol message to acquire time stamp information;

dividing the first reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same;

sampling the second pulse signals by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals;

determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking a first jump edge of each first sampling signal as the sampling point;

And carrying out clock synchronization according to the time stamp information and the first sampling values.
A chip, comprising: the processor is connected with the memory, the memory stores an instruction program, and the processor is used for executing the following steps under the control of the instruction program:

dividing the frequency of the second reference clock signal by using a fractional frequency phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same;

sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

determining a plurality of second sampling values of the plurality of second sampling signals at the sampling points by taking the first jump edge of each second sampling signal as the sampling point;

and determining the time stamp information according to the plurality of second sampling values and the local time, and generating a clock synchronization protocol message, wherein the clock synchronization protocol message carries the time stamp information.
A clock synchronization system, the clock synchronization system comprising:

the second frequency division module is used for dividing the frequency of the second reference clock signal by utilizing the fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein the period of each second sub-clock signal is the same;

The second sampling module is used for sampling the second pulse signals by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

the second sampling value determining module is used for determining a plurality of second sampling values of the plurality of second sampling signals at sampling points by taking the first skip edge of each second sampling signal as the sampling point;

the message generating module is used for determining time stamp information according to the plurality of second sampling values and the local time, and sending a clock synchronization protocol message to the message and second pulse signal receiving module, wherein the clock synchronization protocol message carries the time stamp information;

the message and second pulse signal receiving module is used for receiving the second pulse signal sent by the message generating module and the clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain time stamp information;

the first frequency division module is used for dividing the frequency of the first reference clock signal by utilizing the fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein the period of each first sub-clock signal is the same;

the first sampling module is used for sampling the second pulse signals by utilizing the plurality of first sub-clock signals to obtain a plurality of first sampling signals;

The first sampling value determining module is used for determining a plurality of first sampling values of the plurality of first sampling signals at sampling points by taking a first skip edge of each first sampling signal as the sampling point;

and the clock synchronization module is used for carrying out clock synchronization according to the time stamp information and the plurality of first sampling values.