WO2023004576A1 - Procédé, appareil et système de synchronisation d'horloge, et puce - Google Patents

Procédé, appareil et système de synchronisation d'horloge, et puce Download PDF

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Publication number
WO2023004576A1
WO2023004576A1 PCT/CN2021/108624 CN2021108624W WO2023004576A1 WO 2023004576 A1 WO2023004576 A1 WO 2023004576A1 CN 2021108624 W CN2021108624 W CN 2021108624W WO 2023004576 A1 WO2023004576 A1 WO 2023004576A1
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sampling
clock
sub
signal
signals
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PCT/CN2021/108624
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English (en)
Chinese (zh)
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章成旻
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华为技术有限公司
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Priority to PCT/CN2021/108624 priority Critical patent/WO2023004576A1/fr
Priority to CN202180100996.1A priority patent/CN117716644A/zh
Publication of WO2023004576A1 publication Critical patent/WO2023004576A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Definitions

  • the present application relates to the technical field of distributed networks, in particular to a clock synchronization method, device, system and chip.
  • the clock synchronization system can accurately synchronize the real-time clocks of each node in the distributed network communication to adopt the clock synchronization system of the standard for a precision clock synchronization protocol for networked measurement and control systems (IEEE 1588)
  • each node of the distributed network is equipped with a clock module and a processing module, wherein the processing module is used to process related protocols of IEEE 1588 messages and collect time stamps, and convert the time stamps to It is sent to the clock module, and the clock module is used to calculate the clock information based on the time stamp sent by the processing module, and then adjust the local real-time clock to realize the clock synchronization of each node.
  • the clock module periodically sends time stamp information and pulse per second (PPS) information to the processing module, so that the real-time clock of the processing module is synchronized with the clock module.
  • PPS pulse per second
  • the IEEE 1588 synchronization system has very high requirements for sampling accuracy.
  • the sampling accuracy required is at the nanosecond level.
  • the sampling accuracy of second pulse information is an important factor affecting the accuracy of the entire IEEE 1588 synchronization system.
  • the sampling accuracy of the second pulse information is completely dependent on the clock frequency of the sampling clock, that is, the sampling accuracy of the second pulse information can only be improved by increasing the clock frequency of the sampling clock.
  • a sampling clock with a clock frequency of 1 GHz is required to make the sampling accuracy of the second pulse information reach 1 ns.
  • the present application provides a clock synchronization method, device, system and chip, which can ensure higher precision sampling when the clock frequency of the sampling clock is low.
  • the present application provides a clock synchronization method, including: receiving a second pulse signal and a clock synchronization protocol message, analyzing the clock synchronization protocol message to obtain timestamp information;
  • the clock signal is frequency-divided to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;
  • the second pulse signal is sampled by using a plurality of first sub-clock signals to obtain a plurality of first sampling signals ; Taking the first jump edge of each first sampling signal as the sampling point, determine multiple first sampling values of the multiple first sampling signals at the sampling point; perform clock synchronization according to the timestamp information and the multiple first sampling values .
  • a clock synchronization method provided in the embodiment of the present application uses a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain N first sub-clock signals clk1 ⁇ clkN; using the above-mentioned first sub-clock signal
  • the second pulse signal is sampled to obtain first sampling signals Q1-QN.
  • the jump edge position of the second pulse signal so that the current time can be determined more accurately.
  • the present application uses N first sub-clock signals , the sampling precision can be reduced to 1/N clock period of the first reference clock signal, and the sampling precision can be increased to N times of the original.
  • using multiple first sub-clock signals to sample the second pulse signal includes: using multiple first sub-clock signals to sample the second pulse signal N times, and determining N sets of sampling results; wherein, N is a positive integer; each group of sampling results includes multiple first sampling signals.
  • the phases of multiple first sub-clock signals obtained by frequency division of the first reference clock signal may drift or be inaccurate.
  • the sampling average can be determined by the total number of sampling results N and multiple sets of sampling results to avoid the problem that the sampling accuracy of the second pulse information is affected by the drift or inaccuracy of multiple first sub-clock signals obtained after frequency division.
  • using a fractional frequency-division phase-locked loop circuit to divide the first reference clock signal to obtain a plurality of first sub-clock signals includes: using a fractional frequency-division phase-locked loop circuit to divide the first reference clock signal The frequency of the signal is divided by four to obtain four first sub-clock signals; wherein, after the frequency division, the phase difference between two adjacent first sub-clock signals is 90°.
  • the fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider and a second frequency divider; the inverter is used to: generate and A signal with the opposite phase of the first reference clock signal; the first frequency divider is configured to divide the frequency of the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting point of the two first sub-clock signals is The initial phases are respectively 0° and 180°; the second frequency divider is used to divide the frequency of the signal opposite to the phase of the first reference clock signal by two to obtain two first sub-clock signals, wherein the two first The starting phases of the sub clock signals are 90° and 270° respectively.
  • the inverter in the fractional frequency-division phase-locked loop After the first reference clock signal is input to the inverter in the fractional frequency-division phase-locked loop, its 0° and 180° phase clock signals are obtained, and the 0° and 180° phase clock signals are respectively subjected to the first frequency division
  • the second frequency divider and the second frequency divider obtain the first sub-clock signals with initial phases of 0°, 90°, 180° and 270° respectively.
  • the structure of the fractional frequency division phase-locked loop circuit of the present application is not limited thereto.
  • the inverter in the fractional frequency division phase-locked loop circuit can also be a phase separation circuit, and the phase separation circuit can also generate A signal that is in phase opposite to the first reference clock signal.
  • the first jump edge is a rising edge transitioning from a low level to a high level and/or a falling edge transitioning from a high level to a low level.
  • the second pulse signal is sampled by using a plurality of first sub-clock signals, including: sampling the second pulse signal by using the second jump edge of a plurality of first sub-clock signals, and the second jump edge is a transition from a low level to Rising edge high, and/or falling edge transition from high to low.
  • the method further includes: generating a first multi-phase clock signal according to the multiple first sub-clock signals, and using the first multi-phase clock signal to compare the second pulse signal Take a sample.
  • determining the time stamp information according to a plurality of second sampling values and the local time includes: when a sampling value of a set size appears for the first time among the plurality of second sampling values, according to the pulse period of the second pulse signal As well as the local time, determine the timestamp information.
  • the sampling error stipulated in the clock synchronization protocol message used will also be low.
  • the sampling error stipulated in the clock synchronization protocol message is not greater than ⁇ 0.5 ns.
  • the clock synchronization method provided by this application can also be completed by using a clock below 500MHz, which is relatively common in clock frequency and has relatively low requirements on clock manufacturing technology.
  • the clock frequency of the first reference clock signal is not higher than 500MHz.
  • the present application provides a clock synchronization method, which is applied to a master synchronization device, and uses a fractional frequency-division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain multiple second sub-clock signals; wherein, each The period of the second sub-clock signal is the same; Utilize a plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals; take the first jump edge of each second sampling signal as the sampling point, determine how many A plurality of second sampling values of a second sampling signal at the sampling point; determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, and the clock synchronization protocol message carries time stamp information.
  • the technical effect of the corresponding solution in the second aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail.
  • using multiple second sub-clock signals to sample the second pulse signal includes: using multiple second sub-clock signals to sample the second pulse signal N times, and determining N sets of sampling results; wherein, N is a positive integer; each group of sampling results includes multiple second sampling signals.
  • using a fractional frequency-division phase-locked loop circuit to divide the second reference clock signal to obtain a plurality of second sub-clock signals includes: using a fractional frequency-division phase-locked loop circuit to divide the second reference clock signal The frequency of the signal is divided by four to obtain four second sub-clock signals; wherein, after the frequency division, the phase difference between two adjacent first sub-clock signals is 90°.
  • the fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider and a second frequency divider; the inverter is used to: generate and The signal with the opposite phase of the second reference clock signal; the first frequency divider is used to divide the frequency of the second reference clock signal by two to obtain two first sub-clock signals, wherein the starting point of the two first sub-clock signals The initial phases are respectively 0° and 180°; the second frequency divider is used to divide the frequency of the signal opposite to the phase of the second reference clock signal by two to obtain two first sub-clock signals, wherein the two first The starting phases of the sub clock signals are 90° and 270° respectively.
  • the first jump edge is a rising edge transitioning from a low level to a high level and/or a falling edge transitioning from a high level to a low level.
  • using multiple first sub-clock signals to sample the second pulse signal includes: using the second jump edges of the multiple first sub-clock signals to sample the second pulse signal, and the second jump edge is the rising edge from low to high, and/or the falling edge from high to low.
  • the method further includes: generating a second multi-phase clock signal according to the multiple second sub-clock signals, and using the second multi-phase clock signal to compare the second pulse signal Take a sample.
  • determining the time stamp information according to a plurality of second sampling values and the local time includes: when a sampling value of a set size appears for the first time among the plurality of second sampling values, according to the pulse period of the second pulse signal As well as the local time, determine the timestamp information.
  • the sampling error stipulated in the clock synchronization protocol message is not greater than ⁇ 0.5 ns.
  • the clock frequency of the first reference clock signal is not higher than 500 MHz.
  • the present application also provides a clock synchronization device, including a message and pulse-per-second signal receiving module, used to: receive the pulse-second signal and a clock synchronization protocol message, and analyze the clock synchronization protocol message to obtain time stamp information;
  • the frequency division module is used to: use the fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;
  • the sampling module It is used to: use a plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals;
  • the sampling value determination module is used to: take the first jump edge of each first sampling signal as a sampling point, A plurality of first sampling values of the plurality of first sampling signals at the sampling point are determined;
  • a clock synchronization module is configured to perform clock synchronization according to the time stamp information and the plurality of first sampling values.
  • the present application also provides a clock synchronization device, including a frequency division module, configured to: use a fractional frequency division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain multiple second sub-clock signals; Wherein, the period of each second sub-clock signal is the same; the sampling module is used to: use a plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals; the sampling value determination module is used to: Taking the first jump edge of each second sampling signal as the sampling point, determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point; the message generation module is used for: according to the plurality of second sampling values And the local time determines the time stamp information, sends the clock synchronization protocol message, and the clock synchronization protocol message carries the time stamp information.
  • the technical effect of the corresponding solution in the fourth aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in
  • the present application provides a chip, including: a processor and a memory, the processor is connected to the memory, and an instruction program is stored in the memory, and the processor, under the control of the instruction program, is used to perform the following steps: obtain the second pulse signal and a clock synchronization protocol message, analyzing the clock synchronization protocol message to obtain time stamp information; using a fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, each The period of a sub-clock signal is the same; Utilize a plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals; take the first jump edge of each first sampling signal as a sampling point to determine a plurality of A plurality of first sampling values of the first sampling signal at the sampling point; clock synchronization is performed according to the time stamp information and the plurality of first sampling values.
  • the technical effect of the corresponding solution in the fifth aspect can refer to the technical effect that can be obtained
  • the present application provides a chip, including: a processor and a memory, the processor is connected to the memory, and an instruction program is stored in the memory, and the processor is used to perform the following steps under the control of the instruction program: using fractional frequency division
  • the phase-locked loop circuit divides the frequency of the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same; the second pulse signal is sampled by using a plurality of second sub-clock signals , to obtain a plurality of second sampling signals; taking the first jump edge of each second sampling signal as a sampling point, determine a plurality of second sampling values of a plurality of second sampling signals at the sampling point; according to a plurality of second sampling The value and the local time determine the time stamp information, and generate a clock synchronization protocol message, and the clock synchronization protocol message carries the time stamp information.
  • the technical effect of the corresponding solution in the sixth aspect can refer to the technical effect that can be obtained by the corresponding solution
  • the present application provides a clock synchronization system.
  • the clock synchronization system includes: a second frequency division module, which is used to divide the frequency of the second reference clock signal by a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clocks.
  • the second sampling module is used to sample the second pulse signal by using a plurality of second sub-clock signals to obtain a plurality of second sampling signals;
  • the second sampling value The determination module is used to take the first jump edge of each second sampling signal as a sampling point to determine a plurality of second sampling values of a plurality of second sampling signals at the sampling point;
  • the second sampling value and the local time determine the time stamp information, and send a clock synchronization protocol message to the message and second pulse signal receiving module, and the clock synchronization protocol message carries time stamp information;
  • the message and second pulse signal receiving module is used to receive
  • the second pulse signal sent by the message generation module and the clock synchronization protocol message are parsed to obtain the time stamp information;
  • the first frequency division module is used to use the fractional frequency division phase-locked loop circuit to process the first reference clock signal frequency division to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;
  • the first sampling module is used
  • FIG. 1 is a first schematic flow diagram of a clock synchronization method
  • FIG. 2 is a timing diagram corresponding to a clock synchronization method
  • Fig. 3 is a structural schematic diagram of a fractional frequency division phase-locked loop circuit
  • FIG. 4 is a second schematic flow diagram of a clock synchronization method
  • Fig. 5 is a schematic diagram of a clock synchronization device
  • Fig. 6 is a schematic diagram of another clock synchronization device.
  • one of the multiple nodes acts as a master synchronization device (master), and the remaining nodes act as slave synchronization devices (slave).
  • the master synchronization device can synchronize the reference time to all slave synchronization devices.
  • the master synchronization device sends an IEEE 1588 protocol message, and the slave synchronization device can collect time stamp information according to the received protocol message.
  • the real-time clock is adjusted so that the clock module of the slave synchronization device is synchronized with the time of the master synchronization device.
  • the slave synchronization device sends the time stamp information and the pulse-per-second information to the processing module, and the slave synchronization device adjusts its own real-time clock according to the time stamp information and the pulse-per-second information, and finally realizes clock synchronization.
  • the sampling error specified in the clock synchronization protocol message used will be relatively low.
  • a sampling clock with a clock frequency of 1 GHz is required to sample the second pulse signal in order to achieve a sampling accuracy of 1 ns.
  • the cost of producing a 1GHz clock is too high, and the clock frequency is less than 500MHz, but the sampling accuracy of the clock at a lower cost is difficult to meet the requirements of the IEEE 1588 synchronization system. Accuracy requirements. In view of this, when the clock frequency of the sampling clock used is low, how to ensure a higher precision sampling requirement is an urgent problem to be solved by those skilled in the art.
  • Figure 1 is a flow chart of the clock synchronization method provided by the embodiment of the application
  • Figure 2 is a timing diagram corresponding to the clock synchronization method provided by the implementation of the application, in combination with Figure 1 and Figure 2, the clock synchronization method in the embodiment of the application is applied to When syncing from a device, you can include methods like:
  • S101 Receive a second pulse signal and a clock synchronization protocol message, and analyze the clock synchronization protocol message to obtain time stamp information.
  • the clock synchronization protocol message may include: a high-precision time synchronization protocol (precision time protocol, PTP) message, a generalized precision time protocol (generalized precision time protocol, 802.1AS) message, a sync synchronization message, and a follow_up following message , delay_req delay request message or delay_resp delay response message, etc.
  • the sampling error stipulated in the clock synchronization protocol message may not be greater than ⁇ 0.5ns.
  • a PTP type message is used as an example, but it does not constitute a limitation to this application.
  • any All clock synchronization protocols can be applied in this application, and are not limited here.
  • the second pulse signal can be generated by an external clock device, and can also be sent together with the master synchronization device.
  • the time stamp information master synchronization device is determined based on the current time, and the current time is not limited to universal time coordinated (UTC) time and global positioning system (global positioning system, GPS) time, etc., which are not specifically limited here.
  • UTC universal time coordinated
  • GPS global positioning system
  • S102 Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals. The period of each first sub-clock signal is the same.
  • the first reference clock signal may be generated by an internal clock
  • the internal clock may include: a crystal oscillator, a frequency multiplication circuit, a phase detector, a clock pulse circuit, an input digital-to-analog converter, a voltage-controlled oscillator, etc. .
  • the crystal oscillator can generate a clock signal with a reference frequency, and the reference frequency is related to the specific structure of the crystal oscillator; the frequency multiplication circuit is used to perform frequency multiplication processing on the reference frequency clock signal; The pulse circuit converts the phase detection signal into a clock pulse signal for the phase detection signal, and inputs the digital-analog converter to convert the clock pulse signal into an analog clock pulse signal, and the voltage-controlled oscillator outputs the first reference clock signal according to the analog clock pulse signal.
  • the above-mentioned processing process of the clock signal of the reference frequency is only an example, and the device connection relationship in the internal clock is not limited.
  • the purpose is to generate a clock signal of a specific frequency.
  • the specific generation method is not limited, and those skilled in the art should know .
  • the existing frequency division circuit can use a delay loop (time to digital converter, TDC) to divide the frequency of the first reference clock signal.
  • TDC time to digital converter
  • the timing time after frequency division will be completely determined by the timing chip (cell), but the timing chip (cell) jitter and high uncertainty, and is greatly affected by process voltage temperature (precess voltage temperature, PVT) conditions, so the reliability of frequency division using TDC is low, and a delay jitter of up to 1.68% will be generated, and due to The structure of its delay loop will lead to the accumulation of delay jitter, resulting in greater errors.
  • this application uses analog devices to form a fractional frequency division phase-locked loop circuit, which is not affected by process angle deviation and temperature.
  • a complex closed-loop structure is used to meet the requirements of high-speed clock scenarios, which has the advantages of low delay and high precision.
  • the first reference clock signal is divided by four using a fractional frequency-division phase-locked loop circuit to obtain four first sub-clock signals; wherein, after frequency division, adjacent The phase difference between the two first sub-clock signals is 90°.
  • a fractional frequency-division phase-locked loop circuit is used to divide the frequency of the first reference clock signal by four, thereby obtaining four first sub-clock signals: the first sub-clock signal clk1, the first sub-clock signal clk2, the first sub-clock The signal clk3 and the first sub-clock signal clk4; wherein, the phase difference between each adjacent clock signal is 90°.
  • phase difference between adjacent clock signals in the embodiment of the present application is 90° means, for example, the phase difference between the first sub-clock signal clk1 and the first sub-clock signal clk2 may have a certain deviation range Or, in other words, the phase difference between the first sub-clock signal clk1 and the first sub-clock signal clk2 is approximately 90°, and each first sub-clock needs to be kept in sync.
  • the clock frequency of the first reference clock signal is not higher than 500 MHz.
  • the number of generated first sub-clock signals may be related to the clock frequency of the first reference clock signal, for example, when the clock frequency of the first reference clock signal is 500MHz, fractional frequency division
  • the phase-locked loop circuit can divide the frequency of the first reference clock signal by four to obtain four first sub-clock signals, and when the clock frequency of the first reference clock signal is 250MHz, the fractional frequency-division phase-locked loop circuit can divide the first sub-clock signal A reference clock signal is divided by eight to obtain eight first sub-clock signals.
  • the first sub-clock signal can use the second jump edge to sample the second pulse signal.
  • the second jump edge can be a rising edge, that is, from a low level (0) Jumping to the transition edge of high level (1), of course, the second transition edge can also be a falling edge, that is, the transition edge from high level (1) to low level (0), in order
  • the second transition edge is taken as an example for illustration. Exemplarily, taking rising edge sampling as an example, after the second pulse signal is sampled by using the first sub-clock signal clk1, the first sampling signal Q1 can be obtained.
  • S104 Using the first jump edge of each first sampling signal as a sampling point, determine a plurality of first sampling values of the plurality of first sampling signals at the sampling point.
  • the sampling point refers to the first transition edge of the first sampling signal, wherein the first transition edge is the transition edge from the first value to the second value
  • the first transition edge can be a rising edge, that is, a transition edge that transitions from a low level (0) to a high level (1).
  • the first transition edge can also be a falling edge, that is, a transition from a high level to
  • the transition edge from the level (1) to the low level (0) is described in this application by taking the first transition edge as a rising edge as an example.
  • S105 Perform clock synchronization according to the time stamp information and multiple first sampling values.
  • the current time is determined according to the sampling value at which the updated time is first collected among the multiple first sampling values and the time stamp information, so as to realize clock synchronization.
  • each device may include a clock synchronization module and a processing module, and the above steps S101 to S105 may be performed in the processing module, that is, the clock synchronization module periodically receives time stamp information from the master synchronization device and second pulse information, and periodically send time stamp information and second pulse information to the processing module.
  • the processing module executes the above steps S101 to step S105, so that the master synchronization device and the slave synchronization Devices implement clock synchronization.
  • clock synchronization based on time stamp information and multiple first sampling values may be: when a sampling value of a set size appears for the first time in multiple first sampling values, according to the pulse of the second pulse signal Period and timestamp information to determine the current time.
  • the embodiment of the present application can obtain four first sub-clock signals clk1-clk4 by dividing the frequency of the first reference clock by four;
  • the sampling of the signal can obtain the first sampling signals Q1-Q4, and obtain a plurality of first sampling values based on the first transition edges of the first sampling signals Q1-Q4.
  • the pulse period of the second pulse signal is 1s
  • the time indicated by the time stamp information is 10:00:00.
  • the current time change is determined from the synchronization device is 10:00:01.
  • the sending time can be used as the compensation time, which is pre-added to the value carried by the time stamp. In the time, and then perform clock synchronization after compensating the sending time; and, because of the different ways of sending the clock synchronization protocol message, or the distance between the master synchronization device and the slave synchronization device, the corresponding sending time is also different.
  • the clock synchronization method uses a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain the first sub-clock signals clk1-clk4; wherein, each adjacent clock signal The phase difference of each is 90°, and the second pulse signal is sampled by using the above-mentioned first sub-clock signal to obtain the first sampling signals Q1-Q4.
  • the present application uses N first sub-clock signals , the sampling precision can be reduced to 1/N clock period of the first reference clock signal, and the sampling precision can be increased to N times of the original.
  • the synchronization method may further include: using a plurality of first sub-clock signals to sample the second pulse signal N times to determine N groups of sampling results; wherein, N is a positive integer; each group of sampling results includes a plurality of first sampling signals.
  • the above steps S103-S105 are executed N times, that is, after the second pulse signal is sampled N times by using a plurality of first sub-clock signals, if the phases of the plurality of first sub-clock signals do not drift, then Among the N groups of sampling results, each group of sampling results is basically the same. If the phases of multiple first sub-clock signals drift, the sampling average value can be determined by the total amount of sampling results N and multiple groups of sampling results, so as to avoid obtaining The drift or inaccuracy of multiple first sub-clock signals affects the sampling accuracy of the second pulse information.
  • the fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider and a second frequency divider; the inverter is used to: generate and A signal with the opposite phase of the first reference clock signal; the first frequency divider is configured to divide the frequency of the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting point of the two first sub-clock signals is The initial phases are respectively 0° and 180°; the second frequency divider is used to divide the frequency of the signal opposite to the phase of the first reference clock signal by two to obtain two first sub-clock signals, wherein the two first The starting phases of the sub clock signals are 90° and 270° respectively.
  • Fig. 3 is a structural schematic diagram of a fractional frequency division PLL circuit; referring to Fig. 3, the first reference clock signal is first input into the inverter in the fractional frequency division PLL to obtain its 0° and 180° phase clocks CLK0 and CLK1, CLK0 passes through the first frequency divider to obtain CLK00 and CLK01 with a frequency of 1/2 and a phase of 0° and 180°; CLK1 passes through the second frequency divider to obtain a frequency of 1/2 2. CLK10 and CLK11 with phases of 90° and 270°.
  • the structure of the fractional frequency division phase-locked loop circuit of the present application is not limited thereto.
  • the inverter in the fractional frequency division phase-locked loop circuit can also be a phase separation circuit, and the phase separation circuit can also be based on the first reference clock
  • the signal generates 0° and 180° phase clocks CLK0 and CLK1.
  • the delay error of the phase separation circuit is smaller, and its value is generally less than 3ps, which is more suitable for the high-precision clock synchronization protocol scenario of this application.
  • the method further includes:
  • a first multi-phase clock signal is generated according to the plurality of first sub-clock signals, and the second pulse signal is sampled by using the first multi-phase clock signal.
  • the fractional frequency-division phase-locked loop circuit may further include: an AND gate circuit for synthesizing a plurality of first sub-clock signals into a first multi-phase clock.
  • an AND gate circuit for synthesizing a plurality of first sub-clock signals into a first multi-phase clock.
  • CLK00, CLK01, CLK10, and CLK11 of the above embodiment are input to the AND gate circuit, the AND gate circuit can obtain a frequency half of the first reference clock signal, a duty cycle of 25%, and a starting phase of 0 °, 90°, 180° and 270° four-phase clock.
  • FIG. 4 is a flow chart of the clock synchronization method provided by the embodiment of the present application.
  • the clock synchronization method in the embodiment of the present application is applied to the master synchronization device, which may include:
  • S402 Use the multiple second sub-clock signals to sample the second pulse signal to obtain multiple second sampling signals
  • the present application provides a clock synchronization device 500, which device includes: message and second pulse signal receiving module 501, used for: receiving second pulse signal and clock synchronization protocol message, and analyzing the clock synchronization protocol
  • the time stamp information is obtained from the message;
  • the frequency division module 502 is configured to: use a fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, each first sub-clock The period of the signal is the same;
  • the sampling module 503 is configured to: use the plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals;
  • the sampling value determination module 504 is configured to: The first jump edge of the first sampling signal is a sampling point, and a plurality of first sampling values of the plurality of first sampling signals at the sampling point are determined;
  • the clock synchronization module 505 is configured to: according to the time stamp Clock synchronization is performed on the information and the plurality of first sampled
  • the present application also provides a clock synchronization device 600, which includes: a frequency division module 601, configured to: use a fractional frequency division phase-locked loop circuit to divide the second reference clock signal to obtain multiple The second sub-clock signal; wherein, the period of each second sub-clock signal is the same; the sampling module 602 is configured to: use the plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second Sampling signal; sampling value determination module 603, configured to: take the first jump edge of each second sampling signal as a sampling point, and determine multiple second sampling values of the multiple second sampling signals at the sampling point ; A message generating module 604, configured to: determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.
  • a frequency division module 601 configured to: use a fractional frequency division phase-locked loop circuit to divide the second reference clock signal to obtain multiple The second sub-clock signal; wherein, the period of each
  • each functional module can be integrated in In one processing module, each module may exist independently, or two or more units may be integrated into one unit.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • the present application also provides a clock synchronization system.
  • the clock synchronization system includes: a second frequency division module, which is used to divide the frequency of the second reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clocks signal; wherein, the period of each second sub-clock signal is the same; the second sampling module is used to use the plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals; Two sampling value determination modules, used to take the first jump edge of each second sampling signal as a sampling point to determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point; message generation A module, configured to determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message to the message and second pulse signal receiving module, the clock synchronization protocol message carrying the time Stamp information; message and second pulse signal receiving module, used to receive the second pulse signal and clock synchronization protocol message sent by the message generation module, and analyze
  • the present application also provides a chip, a processor and a memory, the processor is connected to the memory, an instruction program is stored in the memory, and the processor is used to perform the following steps under the control of the instruction program : Obtain a second pulse signal and a clock synchronization protocol message, analyze the clock synchronization protocol message to obtain time stamp information; use a fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain multiple first sub-clocks signal; wherein, the period of each first sub-clock signal is the same; the second pulse signal is sampled by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; The first jump edge is a sampling point, and determining a plurality of first sampling values of the plurality of first sampling signals at the sampling point; performing clock synchronization according to the time stamp information and the plurality of first sampling values.
  • the present application also provides a chip, including: a processor and a memory, the processor is connected to the memory, an instruction program is stored in the memory, and the processor is used to execute The following steps: use the fractional frequency division phase-locked loop circuit to divide the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same; using the plurality of second sub-clock signals The sub-clock signal samples the second pulse signal to obtain a plurality of second sampling signals; taking the first jump edge of each second sampling signal as a sampling point, and determining that the plurality of second sampling signals are at the sampling point multiple second sampled values at the same time; determine time stamp information according to the multiple second sampled values and local time, and generate a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.
  • an embodiment of the present application further provides a computer program, which causes the computer to execute the clock synchronization method provided in the above embodiments when the computer program is run on a computer.
  • the embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored in the computer-readable storage medium.
  • the computer program When the computer program is executed by a computer, the computer executes the clock synchronization provided by the above embodiments. method.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente demande concerne un procédé, un appareil et un système de synchronisation d'horloge, et une puce. Le procédé consiste à : recevoir des signaux d'impulsions par seconde et un message de protocole de synchronisation d'horloge, des informations d'horodatage pouvant être obtenues au moyen de l'analyse du protocole de synchronisation d'horloge; effectuer une division de fréquence sur un premier signal d'horloge de référence à l'aide d'un circuit de boucle à verrouillage de phase à division de fréquence fractionnaire, de manière à obtenir une pluralité de premiers sous-signaux d'horloge; échantillonner les signaux d'impulsions par seconde au moyen de la pluralité de premiers sous-signaux d'horloge, de manière à obtenir une pluralité de premiers signaux échantillonnés; prendre des premiers bords de saut des premiers signaux échantillonnés en tant que points d'échantillonnage, et déterminer une pluralité de premières valeurs d'échantillonnage de la pluralité de premiers signaux échantillonnés au niveau des points d'échantillonnage; et effectuer une synchronisation d'horloge en fonction des informations d'horodatage et de la pluralité de premières valeurs d'échantillonnage. Dans la présente demande, après qu'une division de fréquence est effectuée sur un premier signal d'horloge de référence à l'aide d'un circuit de boucle à verrouillage de phase à division de fréquence fractionnaire, des signaux d'impulsions par seconde peuvent être échantillonnés avec une plus grande précision en utilisant une pluralité de premiers sous-signaux d'horloge, de sorte que la précision d'échantillonnage peut être améliorée, ce qui permet d'améliorer encore la justesse de synchronisation d'horloge.
PCT/CN2021/108624 2021-07-27 2021-07-27 Procédé, appareil et système de synchronisation d'horloge, et puce WO2023004576A1 (fr)

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CN202180100996.1A CN117716644A (zh) 2021-07-27 2021-07-27 一种时钟同步方法、装置、系统及芯片

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US10608647B1 (en) * 2018-12-14 2020-03-31 Silicon Laboratories Inc. Delay adjustment using frequency estimation
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EP3806413A1 (fr) * 2019-10-07 2021-04-14 FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V. Procédé d'acquisition de réponses d'impulsion, par exemple pour systèmes à bande ultra large
CN112748758A (zh) * 2020-12-28 2021-05-04 深兰人工智能(深圳)有限公司 时钟源选择方法、装置、电子设备和存储介质

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10608647B1 (en) * 2018-12-14 2020-03-31 Silicon Laboratories Inc. Delay adjustment using frequency estimation
CN109765583A (zh) * 2019-03-04 2019-05-17 华通信安(北京)科技发展有限公司 一种基于gnss接收机秒脉冲的时钟同步方法
EP3806413A1 (fr) * 2019-10-07 2021-04-14 FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V. Procédé d'acquisition de réponses d'impulsion, par exemple pour systèmes à bande ultra large
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