JP2998716B2 - Frame synchronization control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization control circuit, and more particularly, to a frame synchronization control circuit used for establishing frame synchronization with a received frame in a receiving device such as a broadcasting device or a communication device. About.

[0002]

2. Description of the Related Art A frame synchronization control circuit establishes frame synchronization with a received frame by matching the frequency of a data clock of a transceiver tube and matching the data frames. As disclosed in Japanese Unexamined Patent Publication No. Hei 6-152392, control for frame synchronization is performed only within a specific period within a frame.

Hereinafter, a conventional frame synchronization control circuit will be described. FIG. 8 is a block diagram showing an example of the electrical configuration of a conventional frame synchronization control circuit, and FIG. 9 is a timing chart for explaining the operation of the conventional frame synchronization control circuit. As shown in FIG. 8, a conventional frame synchronization control circuit includes a frame detection circuit 1, an oscillator 2, a frequency division ratio control unit 3, a variable frequency divider 4, a first PLL (Phase
Locked Loop) circuit 5 and a second PLL circuit 6.

The frame detection circuit 1 generates a frame clock indicating the beginning of a data frame in the receiver, detects a frame synchronization signal included in the received signal, and generates a frame clock generated in the receiver. A signal that detects the degree of advance or delay with respect to the clock is generated. The frequency division ratio control unit 3 generates a frequency division control signal indicating the amount of change of the normal frequency division ratio in the variable frequency divider 4 and the time and control direction of the change in response to the signal from the frame detection circuit 1. I do. The variable frequency divider 4 calculates the frequency based on the frequency division control signal,
For example, the reference clock from the oscillator 2 composed of a crystal oscillator is frequency-divided at a variable frequency division ratio. The first PLL circuit 5 generates a system clock necessary for the operation of each unit in the receiver in phase with the frequency-divided clock. Second PLL
The circuit 6 generates a data clock required for processing received data in phase synchronization with the system clock.

Next, the operation of the conventional frame synchronization control circuit will be described with reference to FIG. The frame detection circuit 1 counts the system clock to generate a frame clock, and based on the frame clock, advances the frame synchronization signal of the received signal.
Detect the degree of delay. Then, in the frequency division ratio control unit 3, the amount of change of the normal frequency division ratio in the variable frequency divider 4 and the time and control direction to be changed are determined by the signals indicating the degree of advance and delay from the frame detection circuit 1. Control. The variable frequency divider 4 divides the frequency of the reference clock generated by the oscillator 2 at a variable frequency division ratio under the control of the frequency division ratio control unit 3. The first PLL circuit 5 generates a system clock in phase with the frequency-divided clock, and the second PLL circuit 6 generates a system clock.
A data clock is generated in phase synchronization with the system clock from.

In this case, the control of the variable frequency divider 4 by the frequency division ratio controller 3 is performed at the timing shown in FIG. That is, the frequency division ratio control unit 3 includes the frame detection circuit 1
Immediately after the frame clock FC (generated at every frame period T2) shown in FIG. 9A in response to the signal from FIG. 9A, the frequency is divided for a certain control time T1 as shown in FIG. 9B. A frequency division control signal SD indicating the amount of change in the ratio and the time to be changed is generated, the frequency division ratio of the variable frequency divider 4 is changed, and the frequency-divided clock whose frequency has changed is output from the variable frequency divider 4. appear.

For example, when the frame clock generated in the receiver is behind the frame synchronization signal detected from the received signal, the frequency division ratio of the variable frequency divider 4 is set smaller than usual. The frequency of the frequency-divided clock generated by the variable frequency divider 4 is increased, and thus the frequency of the system clock generated by the PLL circuit 5 is increased. As a result, in the receiver, the period of the frame clock generated based on the system clock becomes shorter than usual,
The delay of the frame clock with respect to the frame synchronization signal detected from the received signal can be reduced.
Such control is normally performed only in the first period of a frame in which control data is transmitted so as not to affect the A / D conversion operation for data reception. When the control is not completed in the above, it is performed over a plurality of frames. Such control is continued until the data clock of the receiver matches the data clock of the transmitter and the data frame between the transmitter and the receiver matches.

As described above, in the conventional frame synchronization control circuit, the frequency division ratio of the variable frequency divider 4 is controlled by utilizing the fact that the cycle of the frame clock changes when the frequency of the system clock changes. The period of the frame clock in the receiver is controlled to establish the frequency synchronization of the data clock between the transmitter and the receiver, and the frame synchronization. In this case, the control of the frequency of the system clock is performed as described above. It was performed only during a specific period.

[0009]

However, the conventional frame synchronization control circuit has the following problems. First, as the frequency of the system clock used increases, the time required to establish frame synchronization increases. That is, the conventional frame synchronization control circuit controls the frequency of the system clock inside the receiver to control the frequency division ratio of the variable frequency divider 4 when establishing synchronization of the data frame between the transmitter and the receiver. The operation is continuously performed during the control time T1 in the frame. However, when the frequency of the system clock is changed by changing the dividing ratio of the variable frequency divider, if the frequency is changed too much, the operation is performed by the system clock. Therefore, the frequency difference that can be adjusted by one control cannot be increased so much. Therefore, when the frequency of the system clock increases, a plurality of frames are required to perform required control, and it is inevitable that the time required until frame synchronization is established becomes long.

As a second problem, as the frequency of the data clock used increases, the accuracy of a clock generator to be provided in a portable or mobile transceiver must be increased. That is, in the case of mobile communication, the clock recovery cannot be performed based on the received data because the received data is not temporally stable.
Therefore, it is necessary to adjust the frequency of the data clock provided inside the receiver in accordance with the data clock on the transmitter side, but as the frequency of the data clock increases, the frequency difference of the adjustable data clock decreases. Therefore, it is necessary to increase the precision of the clock generator used in the receiver.

The present invention has been made in view of the above-mentioned circumstances, and in a frame synchronization control circuit, a frequency change amount for frame synchronization can be increased.
Accordingly, it is possible to provide a frame synchronization control circuit which can shorten the time required for establishing frame synchronization and does not need to increase the accuracy of a clock generator to be provided even in mobile communication. It is an object.

[0012]

According to a first aspect of the present invention, there is provided a frame synchronization control circuit of a receiver for synchronizing a data frame between a transmitter and a receiver. Variable frequency dividing means for variably dividing the clock, PLL means for generating a data clock in phase with the divided clock, and generating a frame clock by counting a reference clock. By controlling the frequency division by the variable frequency dividing means in a plurality of times within one or a plurality of frames in accordance with the detection result of the deviation from the detected frame synchronization signal, the PLL
And a control means for synchronizing the data clock generated by the means with the data clock of the received signal.

According to a second aspect of the present invention, there is provided the frame synchronization control circuit according to the first aspect of the present invention, wherein the control means controls the control amount indicating a frequency difference between the frame clock and a frame synchronization signal. Accordingly, a decoder for outputting a count value of a reference clock for performing N (N is a positive integer) control of the variable frequency dividing means within one frame period, and the count value is set, and a decoder for setting the count value is provided. A counter for counting the set value by a reference clock from the time of occurrence and generating a control position pulse for causing the variable frequency dividing means to perform the N-time control at equal intervals within one frame period from the beginning of the frame; Latching a control direction indicating a direction of deviation between the frame clock and a frame synchronization signal in accordance with the frame clock, and It is characterized by comprising a holding means for outputting a control direction control signal indicating increase or decrease of the frequency division ratio in.

According to a third aspect of the present invention, there is provided the frame synchronization control circuit according to the first aspect of the present invention, wherein the control means controls the control amount indicating a frequency difference between the frame clock and a frame synchronization signal. Accordingly, a decoder for outputting a count value of a reference clock for performing N (N is a positive integer) control of the variable frequency dividing means within one frame period, and the count value is set. A counter control section that distributes and outputs the signal at an arbitrary interval, and counts an output value of the counter control section by a reference clock from the time of generation of the frame clock, and the variable frequency dividing means within one frame period from the beginning of the frame. A counter for generating a control position pulse for causing said N-times control to be performed at specified intervals, and a shift between said frame clock and a frame synchronization signal. Holding means for latching a control direction indicating a direction in accordance with the frame clock and outputting a control direction control signal indicating an increase or decrease of a frequency division ratio in the variable frequency dividing means. .

According to a fourth aspect of the present invention, there is provided the frame synchronization control circuit according to the first aspect of the present invention, wherein the control means controls the control amount indicating a frequency difference between the frame clock and a frame synchronization signal. Accordingly, a decoder for outputting a count value of a reference clock for performing N (N is a positive integer) control over the variable frequency dividing means for one frame period or more, and a decoder for setting the count value, A counter which counts the set value by a reference clock from the time of occurrence and generates a control position pulse for causing the variable frequency dividing means to perform the N-times control at equal intervals over one or more frame periods from the beginning of a frame; Latching a control direction indicating a direction of deviation between the frame clock and the frame synchronization signal in accordance with the frame clock. Te, is characterized by comprising a holding means for outputting a control direction control signal indicating increase or decrease of the frequency division ratio in the variable frequency divider means.

Further, the invention described in claim 5 is the first invention.
5. The frame synchronization control circuit according to claim 2, 3 or 4, wherein a time interval between adjacent controls in a plurality of frequency division controls for the variable frequency division means is necessary for stable operation of the PLL means. It is characterized in that it is determined to be longer than a certain time.

The invention according to claim 6 is based on claim 1,
6. The frame synchronization control circuit according to claim 2, 3, 4 or 5, wherein a duration of each control in a plurality of frequency division controls for the variable frequency division means is a control time during which the PLL means is unlocked. It is characterized in that it is determined as follows.

[0018]

According to the configuration of the present invention, in order to synchronize the data clock generated by the receiving device with the data clock of the received signal, the control for increasing or decreasing the frequency division ratio of the variable frequency divider for dividing the reference clock of the oscillator is performed. In performing the control, the required correction amount for the frame synchronization compensation is controlled a plurality of times within a frame at a fixed time interval from the beginning of the frame so that the lock of the PLL circuit for generating the data clock is not lost. Since the control is performed in a distributed manner, the control amount of the frame synchronization compensation can be increased, and the time of the frame synchronization compensation can be shortened.

In another configuration of the present invention, in order to synchronize the data clock generated by the receiving device with the data clock of the received signal, the frequency division ratio of the variable frequency divider that divides the reference clock of the oscillator is set. When performing the control to increase or decrease, control of a required correction amount for frame synchronization compensation is performed within an arbitrary time from the beginning of the frame within one frame so that the lock of the PLL circuit for data clock generation is not released. Since control is performed a plurality of times at intervals, the amount of control for frame synchronization compensation can be increased, and the time required for frame synchronization compensation can be reduced.

According to still another configuration of the present invention, in order to synchronize a data clock generated by a receiving device with a data clock of a received signal, a frequency dividing ratio of a variable frequency divider for dividing a reference clock of an oscillator is used. When performing control to increase or decrease the amount of correction, control of the correction amount required for frame synchronization compensation
In order to prevent the lock of the PLL circuit for generating the data clock from being unlocked, the control is performed in a distributed manner a plurality of times at a fixed time interval from the beginning of the frame over a period of one frame period or more. The amount can be increased, and the time for frame synchronization compensation can be reduced.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. First Embodiment First, a first embodiment of the present invention will be described. The first embodiment is applied to the case where the control of the variable frequency divider is performed at equal intervals. FIG. 1 is a block diagram showing an electrical configuration of a frame synchronization control circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram showing an electrical configuration of a variable frequency divider control unit in the circuit. FIG. 3 is a timing chart for explaining the control operation in the embodiment. As shown in FIG. 1, the frame synchronization control circuit of this example includes a frame detection circuit 1, an oscillator 2, a variable frequency divider control unit 7, and a data clock variable frequency divider (hereinafter referred to as a variable frequency divider). ) 8 and a PLL circuit 9.

The frame detection circuit 1 counts a reference clock by a built-in frame counter (not shown) to generate a frame clock, and uses a comparator or the like (not shown) to receive the generated frame clock and receive the frame clock. The amount of deviation of frame synchronization is compared with a frame synchronization signal detected from the signal (hereinafter, referred to as a control amount).
And the direction of deviation (hereinafter referred to as the control direction) are detected and output. The oscillator 2 includes a crystal oscillator or the like, and generates a fixed frequency reference clock. Variable frequency divider controller 7
Controls the frequency division in the variable frequency divider 8 based on the control amount and the control direction signal from the frame detection circuit 1.

The variable frequency divider 8 performs an operation of generating a divided clock by dividing the frequency of the reference clock from the oscillator 2 under the control of the variable frequency divider controller 7. PLL circuit 9
Is synchronized in phase with the frequency-divided clock from the variable frequency divider 8,
Generates a data clock required for processing received data.
Further, from a data clock generated by the PLL circuit 9, a frame pulse indicating the head of the data frame is generated in a subsequent circuit (not shown) so as to achieve frame synchronization with the data frame on the transmission side. .

As shown in FIG. 2, the variable frequency divider control section 7 of this example is roughly composed of a decoder 11, a counter 12, and a flip-flop 13. The decoder 11 calculates the number of times the variable frequency divider 8 needs to be controlled for frame synchronization in accordance with the control amount signal input from the frame detection circuit 1 and sets the number of times of control in the counter 12 as an initial value. . The counter 12 starts counting from the frame clock input by the reference clock from the oscillator 2, outputs the control position pulse a set number of times from the beginning of the frame, and finishes counting the set initial value. Then, when the counter value becomes 0, the operation ends. The flip-flop 13 latches a control direction signal from the frame detection circuit 1 according to a frame clock from the frame detection circuit 1 and outputs a control direction control signal.

Next, the operation of the frame synchronization control circuit of this embodiment will be described with reference to FIGS. The frame detection circuit 1 generates a frame clock from the reference clock, compares the generated frame clock with a frame synchronization signal in the received signal, and thereby controls a control amount for compensating for a frame synchronization shift and a control direction. And outputs it to the variable frequency divider control unit 7. In the variable frequency divider control unit 7, the decoder 11
The counter 12 counts N (N
Is a positive integer), and outputs a set value calculated in advance to the counter 12 so as to count.

The counter 12 counts the set value from the decoder 11 by the reference clock supplied from the oscillator 2 immediately after the generation of the frame clock.
A control position pulse (indicating the timing at which the variable frequency divider 8 adjusts the frequency division ratio) is output to the variable frequency divider 8 N times at regular intervals from the beginning of the frame. The counter 12
After outputting the control position pulse N times, the operation is stopped until the next frame clock is input. Further, the flip-flop 13 latches a signal in the control direction from the frame detection circuit 1 in accordance with the frame clock from the frame detection circuit 1, and responds to a change in the control direction for increasing or decreasing the frequency division ratio. For example, it outputs control direction control signals having different positive and negative polarities.

Here, the timing of the control operation in the frame synchronization control circuit of this example will be described. The variable frequency divider 8 uses the frame clock FC shown in FIG. 3A as a reference timing T0 and, as shown in FIG. 3B, from the beginning of the frame at every control interval T3, the control position pulses SD1 and SD2. ,..., SDN, an operation of increasing or decreasing the frequency division ratio in the direction specified by the control direction control signal for the control period T4 is performed during the frame period T2. At this time, the control interval T3 is PL
Assuming that the time required for the operation of the L circuit 9 to stabilize is T _PLL , T 3 ≧ T _PLL is determined. The control period T4 is determined so that T4 ≦ T _LOCK , where T _LOCK is a control period (control amount) during which the PLL circuit 9 is unlocked.

As described above, according to the configuration of this example, in the frame synchronization control circuit, the control of the frame synchronization compensation is performed a plurality of times within one frame at equal intervals from the beginning of the frame. The control amount of the frame synchronization compensation can be increased while preventing the lock from being released, and the time required until the completion of the frame synchronization compensation can be shortened. Therefore, even when the frequency of the system clock to be used is high, it is possible to prevent the time required for establishing frame synchronization from becoming excessive.

In this example, since the control of the frame synchronization compensation is performed at equal intervals, the configuration of the variable frequency divider control unit 7 is simplified. Furthermore, since the control of the frame synchronization compensation is completed within one frame, the control can be simplified by performing the control from the beginning of the frame.

Second Embodiment Next, a second embodiment of the present invention will be described. FIG.
FIG. 5 is a block diagram showing an electric configuration of a variable frequency divider control unit constituting a frame synchronization control circuit according to a second embodiment of the present invention. FIG. 5 is a diagram for explaining a control operation in the embodiment. It is a timing chart. The configuration of the second embodiment is significantly different from the configuration of the above-described first embodiment (FIG. 2) in that the configuration (FIG. 4) is applicable when the control interval of the variable frequency divider is not constant. is there. Therefore,
The only major difference from the first embodiment is the configuration of the variable frequency divider control unit.

That is, the variable frequency divider controller 7A of this example
Is a decoder 11 and a counter 12 as shown in FIG.
A, flip-flop 13 and counter control unit 14
This is different from the variable frequency divider controller of the first embodiment in that a counter controller 14 is additionally inserted between the decoder 11 and the counter 12A. The counter control unit 14 controls the counter 1 at any preset variable interval in accordance with a control amount signal from the decoder 11.
A control signal for operating 2A is output. The counter 12A counts the reference clock from the oscillator 2 in response to the control signal from the counter control unit 14, and sets the control position pulse at the interval specified by the control signal from the counter control unit 14 for a set number of times. Is output to the variable frequency divider 8 and the counting of the set initial value is terminated. When the counter value becomes 0, the operation is terminated. Since the configurations of the decoder 11 and the flip-flop 13 are substantially the same as those of the first embodiment (FIG. 2), detailed description will be omitted.

Next, the operation of the frame synchronization control circuit of this embodiment will be described with reference to FIGS. 1, 4 and 5.
The frame detection circuit 1 generates a frame clock from the reference clock, compares the generated frame clock with a frame synchronization signal in the received signal, and thereby controls a control amount for compensating for a frame synchronization shift and a control direction. And outputs it to the variable frequency divider controller 7A. In the variable frequency divider control unit 7A, the decoder 11 controls the counter 1 according to the control amount input from the frame detection circuit 1.
A set value calculated in advance is output to the counter 12A so that 2A counts N (N is a positive integer).

The counter 12A counts the set value from the decoder 11 by the reference clock supplied from the oscillator 2 immediately after the input of the frame clock, so that the variable frequency divider 8 adjusts the frequency division ratio. Are output to the variable frequency divider 8 at specified intervals from the beginning of the frame N times. After outputting the control position pulse N times, the counter 12A stops its operation until the next frame clock is input. Further, the flip-flop 13 latches a signal in the control direction from the frame detection circuit 1 in accordance with the frame clock from the frame detection circuit 1, and responds to a change in the control direction for increasing or decreasing the frequency division ratio. For example, it outputs control direction control signals having different positive and negative polarities.

Here, the timing of the control operation in the frame synchronization control circuit of this example will be described. Variable frequency divider 8, as the reference timing T0 to the frame clock FC shown in FIG. 5 (a), as shown in FIG. (B), the control interval T3 _1, T3 _{2, ...,} each T3 _N, control position By the pulses SD1, SD2,..., SDN, in the direction designated by the control direction control signal, for a control time T4,
The operation of increasing or decreasing the frequency division ratio is performed during one frame period T2. At this time, the control interval T3 _1, T3 _2,
, T3 _N are T3 ₁ , T3 ₂ ,... _, T3 _N , where T _PLL is the time required for the operation of the PLL circuit 9 to stabilize.
It is determined so that ≧ T _PLL . Also, the control time T4
, When the lock is disengaged control period of the PLL circuit 5 (control quantity) and T _{LO CK,} it is determined to be T4 ≦ T _LOCK.

As described above, according to the configuration of this example, in the frame synchronization control circuit, the control of the frame synchronization compensation is performed a plurality of times within one frame at an arbitrary time interval from the beginning of the frame, so that the PLL is controlled. The control amount of the frame synchronization compensation can be increased while preventing the circuit from being unlocked, and the time required for the frame synchronization compensation can be shortened. Therefore, even when the frequency of the system clock to be used is high, it is possible to prevent the time required for establishing frame synchronization from becoming excessive.

In this example, since the control of the frame synchronization compensation is performed at an arbitrary specified interval from the beginning of the frame, for example, when the control cannot be completed within one frame, the control interval of the portion near the end is shortened. Thus, it is possible to perform control so that control can be completed within one frame. Further, since the control of the frame synchronization compensation is completed within one frame, the control can be simplified by performing the control from the beginning of the frame.

Third Embodiment Next, a third embodiment of the present invention will be described. FIG.
FIG. 7 is a block diagram showing an electric configuration of a variable frequency divider control unit constituting a frame synchronization control circuit according to a third embodiment of the present invention. FIG. 7 is a diagram for explaining a control operation in the third embodiment. It is a timing chart. The configuration of the third embodiment is significantly different from the configuration of the above-described first embodiment (FIG. 2), in that the configuration (FIG. 6) is applicable when the control of the frame synchronization compensation is not completed within one frame period. That is the point. Therefore, the difference from the first embodiment described above is only the configuration of the variable frequency divider control unit, as in the case of the second embodiment.

That is, the variable frequency divider controller 7B of this example
Is a decoder 11 and a counter 12 as shown in FIG.
B and the flip-flop 13 are substantially the same as those of the first embodiment described above.
The second embodiment is different from the variable frequency divider control unit of the first embodiment in that the counting is started from an arbitrary time instead of starting the counting from the input of the frame clock. The counter 12B counts the reference clock from the oscillator 2 and outputs a control position pulse to the variable frequency divider 8 at a set number of times and at equal intervals from the arbitrarily set time from the set time. When the counting of the set initial value is completed and the counter value becomes 0, the operation is completed.

Next, the operation of the frame synchronization control circuit of this embodiment will be described with reference to FIGS. 1, 6 and 7.
The frame detection circuit 1 generates a frame clock from the reference clock, compares the generated frame clock with a frame synchronization signal in the received signal, and thereby controls a control amount for compensating for a frame synchronization shift and a control direction. And outputs it to the variable frequency divider controller 7B. In the variable frequency divider control unit 7B, the decoder 11 controls the counter 1 according to the control amount input from the frame detection circuit 1.
A set value calculated in advance is output to the counter 12B so that 2B counts N (N is a positive integer).

The counter 12B starts the decoder 11 by the reference clock supplied from the oscillator 2 from the set time.
The control position pulse is output to the variable frequency divider 8 at equal intervals from an arbitrary set timing by counting N times from the set value to the set value. At this time, if the output of the control position pulse is not completed within one frame period, the control position pulse is output continuously in the next frame. After outputting the control position pulse N times, the counter 12B stops its operation until the next frame clock is input. Further, the flip-flop 13 latches a signal in the control direction from the frame detection circuit 1 in accordance with the frame clock from the frame detection circuit 1, and responds to a change in the control direction for increasing or decreasing the frequency division ratio. For example, it outputs control direction control signals having different positive and negative polarities.

Here, the timing of the control operation in the frame synchronization control circuit of this example will be described. The variable frequency divider 8 controls the control position pulse SD1 from an arbitrary position at every control interval T3, as shown in FIG. 7B, regardless of the reference timing T0 of the frame clock FC shown in FIG. 7A. , SD2,..., SDN in the direction specified by the control direction control signal for a control time T4,
The operation of increasing or decreasing the frequency division ratio is performed for a period of one frame period T2 or more. At this time, the control interval T3 (T3
× N ≧ T2) is determined so that T3 ≧ T _PLL , where T _PLL is the time required for the operation of the PLL circuit 5 to stabilize. Further, assuming that the control period (control amount) in which the lock of the PLL circuit 5 is released is T _LOCK , the control time T 4 is as follows.
It is determined that T4 ≦ T _{LO CK} .

As described above, according to the configuration of this embodiment, the frame synchronization control circuit performs the control of the frame synchronization compensation plural times at equal intervals over one frame period or more. , The control amount of the frame synchronization compensation can be increased, and the time required for the frame synchronization compensation can be shortened. Therefore, even when the frequency of the system clock to be used is high, it is possible to prevent the time required for establishing frame synchronization from becoming excessive. Further, in this example, since the control of the frame synchronization compensation is performed at equal intervals over one or more frames and independently of the head of the frame, the configurations of the variable frequency divider control unit 7B and the counter 12B can be simplified. it can.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there may be design changes within the scope of the present invention. Even this is included in the present invention. For example, all or a part of the frame synchronization control circuit of this example may have a hardware configuration or a software configuration. Part of the frame synchronization control circuit of this example (for example, the variable frequency divider control units 7, 7A, 7B) includes a CPU (Central Processing Unit), a memory having a work area, a memory storing a program, With a configuration including a unit and the like, it is also possible to cause a required operation to be performed by software processing.

[0044]

As described above, according to the frame synchronization control circuit of the present invention, the reference clock of the oscillator is set to match the frequency of the data clock generated by the receiving device and the data clock of the received signal. When performing control to increase or decrease the frequency division ratio of the variable frequency divider to be frequency-divided, control of a required correction amount is performed within one frame or one frame so that the PLL circuit for data clock generation is not locked.
Since the control is performed in a distributed manner over the frame period, the control amount of the frame synchronization compensation can be increased, and the time of the frame synchronization compensation can be shortened.

In particular, in a mobile communication receiver, since the received data is not temporally stable, it is not possible to reproduce the clock based on the data. It is necessary to adjust according to the data clock of the receiver, but as the frequency of the data clock increases, the frequency difference between the adjustable data clocks decreases, so that the clock generator inside the receiver has higher accuracy. However, if the present invention is applied, the adjustment range of the frequency difference of the data clock can be widened, so that the clock generator in the receiver does not require high accuracy, and therefore, It is possible to provide an inexpensive receiver for portable or mobile use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a frame synchronization control circuit according to a first (second, third) embodiment of the present invention;

FIG. 2 is a block diagram showing an electrical configuration of a variable frequency divider control unit in the circuit.

FIG. 3 is a timing chart for explaining a control operation in the embodiment.

FIG. 4 is a block diagram showing an electrical configuration of a variable frequency divider control unit included in a frame synchronization control circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining a control operation in the embodiment.

FIG. 6 is a block diagram showing an electrical configuration of a variable frequency divider control unit included in a frame synchronization control circuit according to a third embodiment of the present invention.

FIG. 7 is a timing chart for explaining a control operation in the embodiment.

FIG. 8 is a block diagram illustrating an example of an electrical configuration of a conventional frame synchronization control circuit.

FIG. 9 is a timing chart illustrating the operation of a conventional frame synchronization control circuit.

[Description of Signs] 7, 7A, 7B Variable frequency divider control section (control means) 8 Variable frequency divider for data clock (variable frequency divider) 9 PLL circuit (PLL means) 11 Decoder 12, 12A, 12B Counter 13 Flip flop (holding means) 14 Counter control unit

Claims (6)

(57) [Claims] 1. A frame synchronization control circuit of a receiver for synchronizing a data frame between a transceiver and a variable frequency dividing means for variably dividing a reference clock, and generating a data clock in phase synchronization with the divided clock. PLL to do
Means, while counting a reference clock to generate a frame clock, and dispersing the frame clock multiple times within one or a plurality of frames according to a detection result of a shift between the frame clock and a frame synchronization signal detected from a received signal. A frame synchronization control circuit comprising: control means for synchronizing a data clock generated by the PLL means with a data clock of a received signal by controlling the frequency division by the variable frequency dividing means. 2. The control means controls the variable frequency dividing means for N (N is a positive integer) times within one frame period according to a control amount indicating a frequency difference between the frame clock and a frame synchronization signal. A decoder for outputting a count value of a reference clock to be performed, and the count value being set, the set value being counted by the reference clock from the time of generation of the frame clock, and the variable frequency dividing means starting from the beginning of the frame. A counter for generating a control position pulse for causing the N-time control to be performed at equal intervals within one frame period, and a control direction indicating a direction of deviation between the frame clock and a frame synchronization signal in accordance with the frame clock. Latch means for outputting a control direction control signal indicating increase or decrease of the frequency division ratio in the variable frequency dividing means. 2. The frame synchronization control circuit according to claim 1, wherein 3. The control means performs N (N is a positive integer) control of the variable frequency dividing means within one frame period according to a control amount indicating a frequency difference between the frame clock and a frame synchronization signal. A decoder for outputting a count value of a reference clock to be performed, a counter control unit for setting the count value, distributing the set value at an arbitrary interval, and outputting the set value, and a reference clock from the time of generation of the frame clock. A counter that counts an output value of the counter control unit and generates a control position pulse for causing the variable frequency dividing unit to perform the N-time control at a specified interval within one frame period from the beginning of a frame; A control direction indicating a direction of deviation between the frame clock and the frame synchronization signal is latched according to the frame clock,
2. The frame synchronization control circuit according to claim 1, further comprising a holding unit that outputs a control direction control signal indicating an increase or decrease of a frequency division ratio in said variable frequency dividing unit. 4. The control means controls N (N is a positive integer) times the variable frequency dividing means for one frame period or more in accordance with a control amount indicating a frequency difference between the frame clock and a frame synchronization signal. A decoder for outputting a count value of a reference clock to be performed over a period of time, the count value being set, the set value being counted by the reference clock from the time of generation of the frame clock, and the variable frequency dividing means from the beginning of the frame. A counter for generating a control position pulse for causing the N-time control to be performed at equal intervals over one frame period, and a control direction indicating a direction of a shift between the frame clock and a frame synchronization signal according to the frame clock. Latch and hold for outputting a control direction control signal indicating increase or decrease of the dividing ratio in the variable dividing means 2. The frame synchronization control circuit according to claim 1, further comprising: 5. A time interval between adjacent controls in a plurality of frequency division controls for said variable frequency dividing means, wherein said time interval is equal to said PLL.
5. The frame synchronization control circuit according to claim 1, wherein the time is determined so as to be equal to or longer than a time necessary for stabilizing the operation of the means. 6. The continuation time of each control in a plurality of frequency division controls for the variable frequency division means is determined so as to be equal to or less than a control time for unlocking the PLL means. A frame synchronization control circuit according to 1, 2, 3, 4 or 5.