JP2678172B2 - Time data receiving device and time adjusting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time data receiving device and a time adjusting device.

[0002]

2. Description of the Related Art Conventionally, for example, a technique has been proposed in which time data is transmitted through a telephone line to correct the time in order to synchronize the clock time of a broadcasting station in each place with the reference time of a center device.

[0003]

In the above-mentioned conventional apparatus,
It is necessary to receive the time data transmitted in bit serial on the receiving side, correct the time at accurate timing, and synchronize the seconds. For this purpose, a clock signal for synchronizing seconds must be transmitted in addition to the time data, so that there are disadvantages that the circuit configuration therefor becomes complicated and that countermeasures against clock signal noise are required.

[0004] The present invention aims to provide a time data receiving apparatus and a time adjustment device can be synchronized transmission of the clock signal for synchronization is not required, and the time of the transmission side and the terminal side very precisely I am trying.

[0005]

According to the present invention, time data
From the transmitting device, the rear end indicating the end of transmission of the time data is first
The above time data transmitted in synchronization with the clock signal of
Received by the receiving unit and the time data transmitter.
Detecting means for detecting the delay time of the time data
At the rear end that indicates the end of transmission of the time data and at the time of the delay
A synchronization signal generating means for generating a synchronization signal according to
A reference signal circuit for generating a second clock signal;
Clock circuit that measures time based on the clock signal of 2
And the sync signal from the sync signal generating means
The second clock signal of the reference signal circuit is set to the time of day.
Synchronizing with the first clock signal of the data transmitter
At the same time, the time measured by the clock circuit is converted into the time data.
Time data including a time correction means for correcting based on
Configure a receiver.

Further, it is transmitted from the time data transmitter.
The time data is received by the time data receiving device and
Correct the time on the time data receiving device side based on the data
In the time adjustment device, the time data transmission device
Is a first reference signal circuit that outputs a first clock signal.
And time based on this first clock signal
The first clock circuit and the time data of this first clock circuit
The time data output circuit to output and this time data output circuit
The end of the transmission indicating the end of time data transmission from the road
Output in synchronization with the first clock signal from the signal circuit
The time data receiving device, comprising:
Receives the time data from the time data transmitter
When the data is sent from the receiving unit and the time data sending device
Time delay data detection means and the time
The end of the transmission of the data and the delay time
Synchronization signal generating means for generating a synchronization signal by the second clock
And a second reference signal circuit for generating a clock signal
A clock circuit that measures the time based on the clock signal
The second clock signal from the second reference signal circuit is
Synchronized with the first clock signal in the data transmitter
And the time measured by the second clock circuit is set to the above time.
Time correction means for correcting the time based on the time data
Configure a time adjustment device.

The above time data receiving device and time correction
The device solves the above problems.

[0008]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the system configuration of the entire time adjustment device. In FIG. 1, reference numeral 1 denotes a reference clock unit for measuring a reference time, reference numeral 2 denotes a system controller such as a personal computer, and reference numerals 3a to 3a denote data transmission units for transmitting reference time data. . 4 ... 4 are a data receiving unit 4a and a clock unit 4b, respectively.
And a time data receiving device.

FIG. 2 shows the internal structure of the time data transmission device 3. Reference clock unit 1 includes an oscillation circuit (not shown.) Synchronized with the clock signal of 1MHz and 1Hz is supplied from a first reference signal circuit 5 for outputting a second signal and a communication clock signal, the reference signal circuit a first clock circuit 6 for measuring time on the basis of the second signal from the 5, a time display unit 7 for displaying the measured time of the clock circuit 6, the time data output circuit for outputting the measured time data of the clock circuit 6 8
It is composed of The data transmission unit 3a includes a time data input circuit 9 that receives the time data from the time data output circuit 8, a communication control circuit 10 that controls communication of the time data received by the time data input circuit 9, and a time data communication. Timing signal from the communication control circuit 10 and the timing circuit 11 for generating the timing signal of
A serial communication circuit 12 for performing serial-to-parallel conversion based on a timing signal from the device, and a loopback circuit 1 for transmitting / receiving time data and forming a loopback path.
3, a modem circuit 14 for controlling a data transmission / reception operation with respect to a telephone line, and an interface circuit 15 for connecting to the system controller 2.

FIG. 3 shows the internal structure of the time data receiving device 4. In the figure, 16 is a second reference signal circuit for generating clock signals of various frequencies necessary for each part of the time data receiving device 4, and 17 is a second reference signal circuit for timing the time based on the 1-second signal from the reference signal circuit 16 . The reference numeral 2 denotes a clock circuit, and a reference numeral 18 denotes a time display section for displaying the time measured by the clock circuit 17, which constitutes a clock section 4b. Reference numeral 19 is a modem circuit for controlling a data transmission / reception operation with respect to a telephone line, 20 is a serial communication circuit for performing parallel-serial conversion of received data, and 21 is a data delay time between the time data transmitting device 3 and the time data receiving device 4. A time correction circuit for measuring and correcting the time, 22
Is a communication control circuit that controls the communication operation and time adjustment operation of the time data receiving device 4, and these constitute a data receiving unit 4a.

Next, the outline of the time adjustment operation will be described with reference to FIG. The time data transmitting device 3 and the time data receiving device 4 measure time independently. Activation of the time correction is performed according to a request from the time data receiving device 4 side. The time data receiving device 4 makes a call to the time data transmitting device 3, and when the line is connected, the time data receiving device 4 sends out a loop closing signal. When the time data transmitting device 3 receives the loop closing signal, it forms a loopback path with the time data receiving device 4. Subsequently, a predetermined signal for delay time measurement is transmitted from the time data receiving device 4, a time until this signal returns from the time data transmitting device 3 is measured, and the time is stored. Subsequently, a loop release signal is transmitted from the time data receiving device 4 to release the loopback path. After that, the time data receiving device 4 sends a time data request signal, and by receiving this time data request signal, the time data transmitting device 3 sends time data every one second. This time data is as shown in FIG.
The rear end indicating the end of the transmission of is synchronized with the clock signal having a cycle of 1 second. The time data receiving device 4 corrects the time based on the time data. When the time correction is completed, the time data receiving device 4 transmits an end signal, whereby the time data transmitting device 3 stops transmitting the time data, opens the line, and ends the time correction operation.

Next, the detailed configuration and operation of each unit will be described. First, an operation of synchronizing the one-second signal and the communication clock signal in the reference signal circuit 5 will be described. FIG. 5 shows the internal configuration of the reference signal circuit 5. The 1-MHz clock signal supplied to the reference signal circuit 5 is divided by 1/1250 by the frequency dividing circuit 23 to 800 Hz.
Clock signal. The 800 Hz clock signal is frequency-divided by 1/800 in the frequency dividing circuit 24 and is converted into a 1 Hz clock signal. On the other hand, based on the 1 Hz clock signal supplied to the reference signal circuit 5, a 1 Hz clock signal for synchronizing the operation of each part of the reference signal circuit 5 is output from the synchronization separation circuit 25. This clock signal is supplied to frequency dividing circuits 23 and 24, and the 1-Hz clock signal from frequency dividing circuit 24 is
Is synchronized with the 1 Hz clock signal supplied to. The signal detection circuit 26 detects whether or not the 1 MHz clock signal and the 1 Hz clock signal from the synchronization separation circuit 25 are being supplied.
By switching the switching circuit 27, the output circuit 28 always outputs 1
A clock signal of 1 Hz, that is, a 1 second signal is output. With the above configuration, countermeasures against interruption of the 1 Hz or 1 MHz clock signal are taken.

On the other hand, the communication clock signal is 30
0, 1200, 2400 BPS, etc.
Cannot be generated by dividing the frequency of the clock signal. Therefore, the oscillation frequency of the voltage controlled crystal oscillation circuit 29 (4915200 Hz in this example) is set to the frequency dividing circuits 30 and 31.
Is divided by 1/6144 into an 800 Hz clock signal, and the 800 Hz clock signal from the frequency dividing circuit 23 is compared in phase by the phase comparator 32 to synchronize the frequency with the 1 MHz clock signal. . further,
The frequency dividing circuits 30 and 31 are reset by the 1 Hz clock signal from the synchronization separating circuit 25 to synchronize with the 1 Hz clock signal supplied to the reference signal circuit 5.
The frequency division circuit 30 outputs a communication clock signal of 76.8 kHz, which is supplied to the timing circuit 11.

As described above, the 1-second signal and the communication clock signal are synchronized with each other and output from the reference signal circuit 5.

Next, the operation of synchronizing the rear end indicating the end of transmission of the time data from the time data output circuit 8 with the 1-second signal will be described. In order to synchronize the rear end indicating the end of transmission of the time data with the 1-second signal, it is necessary to correct the delay time at the time of parallel-serial conversion of the serial communication circuit 12 and shift the timing of sending the time data. The time data amount k1 is constant regardless of the communication speed. In addition, a delay due to the parallel-to-serial conversion of the time data occurs, but this delay amount k2 is also constant in principle regardless of the communication speed. Therefore, the shift amount N of the actual time data is k1 + k2. Now, the communication speed is 2400
Assuming that the BPS and the time data amount k1 are 90 bits and the delay amount k2 accompanying the parallel-serial conversion of the time data is 2 bits, N = k1 + k2 = 92 bits.

FIG. 6 shows the internal structure of the timing circuit 11. 76.8 kHz from reference signal circuit 5
Is divided by the frequency dividing circuit 33, is converted into a clock signal having a cycle suitable for the communication speed, that is, 2400 BPS, and is supplied to the serial communication circuit 12. The clock signal from the frequency dividing circuit 33 is supplied to the timer circuit 34.
And the number of clocks is counted.

FIG. 7 shows the timing of sending time data. By starting the transmission of the time data earlier by the amount of shift N from the rise of the 1-second clock, it is possible to synchronize the 1-second signal with the rear end indicating the end of the transmission of the time data. Now, since the communication speed is 2400 BPS,
Assuming that the count set number of the timer circuit 34 is n, n = 2
400−N = 2400−92 = 2308. This n
= 2308 is set in the timer circuit 34. The timer circuit 34 starts counting the number of clocks from the frequency dividing circuit 33 in response to the time counting start signal every second from the differentiating circuit 35, and supplies a time data transmission signal to the communication control circuit 10 when "2308" is counted. Then, transmission of time data is started.

As described above, the time data transmission is completed.
Synchronizing the trailing and second signal representative of.

Next, the measurement of the transmission delay time of the time data and the time correction operation in the time data receiving device will be described in detail.

FIG. 8 is an explanatory diagram for explaining the loopback path. In the figure, those having the same numbers as those in FIGS. 2 and 3 indicate the same ones. Reference numeral 36 denotes a telephone line through which data is transmitted and received. In this example, the transmission delay time of the time data is measured immediately before the loopback path, that is, the serial communication circuit 20 and the modem circuit 19.
Perform between By doing so, the time can be adjusted including the delay time in modem circuits 14 and 19.

The delay time measuring operation will be described with reference to FIG. 8. First, the time data receiving device 4 transmits a "loop closing signal" to the time data transmitting device 3. The time data transmitting device 3 switches the switch A of the loopback circuit 13 to the terminal a in accordance with the “loop closing signal”. As a result, a loopback path from the terminal c of the time data receiving device 4 to the terminal d of the time data receiving device 4 via the switch A is formed. Even when the loopback path is formed, the signal from the time data receiving device 4 can be received by the time data transmitting device 3 because the modem circuit 14 and the serial communication circuit 12 are connected. When the loopback path is formed, the time data receiving device 4 sends a measurement signal for measuring the delay time. The time adjustment circuit 21 measures the time from sending out the measurement signal to returning. When the measurement is completed and the "loop release signal" is transmitted from the time data receiving device 4, the time data transmitting device 3 switches the switch A to the terminal b.

As shown in FIG. 9, the delay time to be measured is the time from the rise of the measurement signal in the time adjustment circuit 21 to the time when this signal returns and the time adjustment circuit 21 detects the rise of this signal again. Is. As shown in FIG. 8, the places where the delay time occurs are: t1: parallel-serial conversion delay, t2: modem transmission delay, t3: forward line delay, t4: modem reception delay, t5: modem transmission delay, t
6: There is a return line delay, t7: modem reception delay, and t8: serial-parallel conversion delay. Assuming that the delay time measured by the time correction circuit 21 is Tx, Tx = t2 + t3
+ T4 + t5 + t6 + t7. However, if the delay time when the time data is actually sent from the time data transmitting circuit 3 to the time data receiving device 4 is Td, then Td =
It is t5 + t6 + t7 + t8. Here, t2, t4,
t5 and t7 are delay times in the modem circuit. If the same modem circuit is used at the same communication speed in the time data transmitting device 3 and the time data receiving device 4, t2 = t5,
It can be considered that t4 = t7. Further, if it is considered that the respective delay times of the forward path and the return path are substantially equal, Tx = 2 × (t5 + t6
+ T7), so that Td = (Tx / 2) + t8. That is, the actual delay time Td is “the sum of the delay time at the time of transmission / reception of the modem, the delay time of the communication line, and the delay time at the time of parallel-serial conversion”. t8 is a fixed number of bits n regardless of the communication speed F, and t8 = (1/1 /
F) × n = n / F. Therefore, Td = (Tx /
2) + (n / F). (Tx / 2) is a one-way communication delay time, and (n / F) is a unique time depending on the communication speed.

As described above, the delay time Td at the time data transmission can be obtained from the delay time Tx measured by the time adjustment circuit 21 and the specific time (n / F) depending on the communication speed F.

Next, the time correction operation of the time data receiving device 4 based on the delay time will be described. The shift time Ts is set by the time correction circuit 21 based on the delay time Td. As shown in FIG. 10C, the delay time Td is 1
If within seconds, the shift time Ts = (1−Td). This shift time Ts is set in the timer of the time correction circuit 21, and as shown in FIG. 10D, timing of the shift time Ts is started when the third second of the received time data is determined. When this time measurement is completed, a reset signal is output from the time correction circuit 21 to reset the reference signal circuit 16 as shown in FIG. 10E, and the communication control circuit 22 sets the time data received immediately before the reset to The time of the clock circuit 17 is corrected based on the time.

FIG. 10f shows the time adjustment timing when the clock circuit 17 is advanced, and g and h of FIG. 10 are the timing adjustment timing when the clock circuit 17 is delayed. Here, the reference signal circuit 1
The time of the clock circuit 17 is corrected to 7:00:03 based on the time data of 7:00:02 received immediately before the reset of Step 6.

By the above operation, it is not necessary to send the clock signal for second synchronization, and the time of the time data receiving device 4 is corrected to the correct time synchronized with the time of the time data transmitting device 3.

[0028]

According to the present invention, the transmission of time data is completed.
Is the first clock on the time data transmitter side.
When receiving time data synchronized with the signal and communicating time data
The trailing edge that indicates the end of the above time data by detecting the delay time of
And a second clock on the receiver side based on the delay time
For synchronizing the signal to the first clock signal,
The first and second clocks are sent without sending a clock signal.
Signal, that is, both the time data transmitter and receiver
Enables phase synchronization of device clock signals
Along with, the time of both devices should be set very accurately.
Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a time adjustment device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a time data transmitting device 3.

FIG. 3 is a block diagram showing a configuration of a time data receiving device 4;

FIG. 4 is an explanatory diagram for explaining a time correction operation;

FIG. 5 is a block diagram showing an internal configuration of a first reference signal circuit 5 .

FIG. 6 is a block diagram showing an internal configuration of a timing circuit 11;

FIG. 7 is an explanatory diagram for explaining transmission timing of time data.

FIG. 8 is an explanatory diagram for explaining a loopback path.

FIG. 9 is an explanatory diagram for explaining a delay time measurement timing;

FIG. 10 is a timing chart for explaining a time correction operation.

[Explanation of symbols]

3 time data transmitter 3a data transmitter 4 time data receiver 4a data receiver 5 first reference signal circuit 6 first clock circuit 8 time data output circuit 16 second reference signal circuit 17 second clock circuit 21 Time adjustment circuit 22 Communication control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-191301 (JP, A) JP-A-60-71981 (JP, A) JP-A-60-214291 (JP, A)

Claims (2)

(57) [Claims] 1. A time data transmission device transmits time data.
The rear end that indicates the end of transmission is transmitted in synchronization with the first clock signal.
A receiving unit that receives the time data transmitted , and the time data transmitted from the time data transmission device
Detecting means for detecting the delay time of, and the rear end indicating the end of transmission of the time data and the delay time.
And a reference signal circuit that generates a second clock signal, and a clock that measures time based on the second clock signal.
A circuit and the synchronizing signal from the synchronizing signal generating means
The second clock signal of the reference signal circuit is changed to the time data.
When synchronized with the first clock signal of the transmitter
In addition, the clocked time of the above clock circuit is based on the above time data.
And a time adjusting means for adjusting the time.
Time data receiving device. 2. The time transmitted from the time data transmission device
Data is received by the time data receiving device, and the time data
Correct the time on the time data receiving device side based on
In the time adjustment device, the time data transmission device outputs a first clock signal
To the first reference signal circuit and the first clock signal
A first clock circuit that measures time based on the
Time data output circuit that outputs the time data of the clock circuit
And the end of transmission of the time data from this time data output circuit.
The trailing end indicating the end of the first signal from the reference signal circuit.
And a synchronizing means for outputting in synchronization with the clock signal, the time data receiving device is the time data transmitting device.
From the receiver that receives the time data described above and the time data described above.
Detects the delay time of the time data transmitted from the transmitter
Detection means and a rear end indicating the end of transmission of the time data
And a synchronization for generating a synchronization signal according to the above delay time
A signal generating means and a second clock signal generating a second clock signal .
Based on the reference signal circuit and this second clock signal
From the clock circuit that keeps time and the second reference signal circuit
The second clock signal of the above in the data transmitter
The second clock is synchronized with the first clock signal.
Correct the clock time of the clock circuit based on the above time data.
Time adjusting means for adjusting time
Correction device.