TWM628940U - Master device and slave device - Google Patents

Abstract

The disclosure provides a master device and a slave device. The master device performs: in a first period of an i-th second, sending a synchronization signal frame to the slave device, wherein the synchronization signal frame includes a synchronization header, a pulse per second (1PPS) signal, a first time of date (ToD) information, and a first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a transmission time point at which a first reference 1PPS signal is transmitted in a second period of the i-th second; during the second period of the i-th second, receiving the first reference 1PPS signal from the slave device; determining a second phase compensation information sent to the slave device in a first period of an (i+1)-th second according to a receiving time point when the first reference 1PPS signal is received.

Description

Master device and slave device

The present invention relates to a synchronization mechanism between devices, and more particularly, to a master device and a slave device.

Please refer to FIG. 1A , which is a schematic diagram of a conventional synchronization mechanism. In FIG. 1A , the master device can be connected to the slave device through three signal transmission lines, and the master device can transmit frequency information (such as 10MHz) and phase information (such as one-second pulse) through these signal transmission lines. (a pulse per second, 1PPS) signal) and time of date (Time of date, ToD) information to the slave device, so that the slave device can synchronize accordingly.

However, since the method of FIG. 1A needs to use three signal transmission lines, the wiring is inconvenient.

Please refer to FIG. 1B , which is a schematic diagram of another conventional synchronization mechanism. In FIG. 1B , the master device can be connected to the slave device through a single signal transmission line, and the synchronization signal (such as an embedded PPS (ePPS) signal) can be converted by pulse width modulation (PWM) sent to the slave device for Now such as the Inter-Range Instrumentation Group-B (Inter-Range Instrumentation Group B, IRIG-B) technology.

Please refer to FIG. 1C , which is a schematic diagram of a conventional PWM. In this embodiment, the bit "0" can be adjusted to a pulse wave with a duty cycle of 25% based on the concept of PWM, for example, and the bit "1" can be adjusted to, for example, based on the concept of PWM. The duty cycle is 75% pulse. In FIG. 1C , the signal “1011” can be modulated into the pulse wave sequence shown, for example, according to the above principles, but it is not limited to this.

It can be seen from FIG. 1B that although the difficulty of wiring is reduced, since the master device transmits signals to the slave device in one direction, the slave device cannot know the delay error caused by the line length or other factors.

In view of this, the present invention provides a master device and a slave device, which can be used to solve the above technical problems.

The utility model provides a main control device, which includes a processing circuit and a compensation estimation circuit. The processing circuit is configured to: in the first period of the ith second, send a synchronization signal frame to a slave device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) ) signal, the first time of day information, and the first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a sending time for sending a first reference 1PPS signal during the second period of the i-th second point. The compensation estimation circuit is coupled to the processing circuit and is configured to: receive the first reference 1PPS signal from the slave device during the second period of the ith second; according to receiving the first reference 1PPS A reception time point of the signal determines a second phase compensation information sent to the slave device during the first period of the i+1th second.

The present invention provides a slave device, which includes a receiver and a processing circuit. The receiver is configured to receive a synchronization signal frame from a master device during a first period of the ith second, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (a pulse per second, 1PPS) signal, first day time information and first phase compensation information. The processing circuit is coupled to the receiver, and is configured to: correct a sending time point of sending a first reference 1PPS signal in the second period of the ith second according to the first phase compensation information; The first reference 1PPS signal is sent to the master device at the sending time point of the second period of seconds.

200: Sync System

210: Master control device

211: Compensation Estimation Circuit

212: Processing Circuits

213: Day Time Circuit

220: Servant Device

221: Receiver

222: Processing circuit

411: Sync header

412: First 1PPS signal

413: First day time information

413a: First Ingredient

413b: Second ingredient

414: First phase compensation information

511: Oscillator

512: Phase Locked Loop

513: Bidirectional transmission controller

611: Oscillator

612: Phase Locked Loop

613: Decoder

614: Day Time Circuit

615: Bidirectional Transmission Controller

F1, F2: Sync signal box

RS: first reference 1PPS signal

SC1: system clock signal

ET: External Day Time

T1: The first period

T2: The second period

T3: The third period

GT: Preset protection time

PT: Preset time point

EC: External clock signal

EP: External 1PPS signal

LC1: local clock signal

ST: system day time

FS: signal frequency

S311~S313, S321~S323: Steps

FIG. 1A is a schematic diagram of a conventional synchronization mechanism.

FIG. 1B is a schematic diagram of another conventional synchronization mechanism.

FIG. 1C is a schematic diagram of a conventional PWM.

FIG. 2 is a schematic diagram of a synchronization system according to an embodiment of the present invention.

FIG. 3 is a flowchart of a synchronization calibration method according to an embodiment of the present invention.

4 is a schematic diagram illustrating the first period and the second period of the i-th second according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the main control device shown in FIG. 2 .

FIG. 6 is a schematic diagram of the slave device shown in FIG. 2 .

Please refer to FIG. 2 , which is a schematic diagram of a synchronization system according to an embodiment of the present invention. In FIG. 2, the synchronization system 200 includes a master device 210 and a slave device 220, wherein the master device 210 and the slave device 220 can be connected through a bidirectional transmission interface (eg, a synchronous serial bus). That is, in some embodiments, the master device 210 can not only send information required for synchronization to the slave device 220, but also receive feedback information from the slave device 220, and the master device 210 and the slave device 220 are Synchronized corrections can be made in this mechanism of two-way communication.

In one embodiment, the main control device 210 includes a compensation estimation circuit 211 and a processing circuit 212 , wherein the processing circuit 212 is coupled to the compensation estimation circuit 211 . In some embodiments, the main control device 210 may further include a time-of-day circuit 213 coupled to the processing circuit 212, but it is not limited thereto. In addition, the slave device 220 includes a receiver 221 and a processing circuit 222 coupled to each other.

In the embodiment of the present invention, the master device 210 and the slave device 220 can cooperate to implement the synchronization calibration method of the present invention, the details of which are described below.

Please refer to FIG. 3 , which is a flowchart of a synchronization calibration method according to an embodiment of the present invention. The method of this embodiment can be executed by the master device 210 and the slave device 220 in FIG. 2 . The details of each step in FIG. 3 will be described below with the elements shown in FIG. 2 .

In the embodiment of the present invention, the operation principles performed by the master device 210 and the slave device 220 in the time interval of each second are roughly the same/similar, so the operation performed in the ith second is used as an example below. description, but not limited to.

First, in step S311 , in the first period of the ith second, the processing circuit 212 of the master device 210 sends the synchronization signal frame F1 to the slave device 220 . Correspondingly, in step S321 , in the first period of the ith second, the receiver 221 of the slave device 220 receives the synchronization signal frame F1 from the master device 210 .

In the embodiment of the present invention, the ith second can be at least divided into a first period and a second period, wherein the first period is, for example, a period during which the master device 210 can send a signal to the slave device 220, and the second period is, for example, It is the period during which the master device 210 listens to the signal sent by the slave device 220, but it is not limited to this.

Please refer to FIG. 4 , which is a schematic diagram of the first period and the second period of the ith second according to an embodiment of the present invention. As shown in FIG. 4 , the synchronization signal frame F1 sent by the master device 210 in the first period T1 of the ith second may include, for example, a synchronization header 411 , a first 1PPS signal 412 , a first time of day information 413 and The first phase compensation information 414 . In other embodiments, the designer can also adjust the order of the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 in the synchronization signal frame F1 according to requirements, but it is not limited thereto.

In one embodiment, the processing circuit 212 may, after obtaining the contents of the synchronization header 411 , the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 , synchronize the synchronization header according to the aforementioned PWM mechanism. The header 411 , the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 are encoded into corresponding PWM signals and sent, but not limited thereto.

In one embodiment, the content of the sync header 411 can be designed as a specific combination of bytes, so that the slave device 220 can detect the specific combination of bytes, It is determined that the synchronization signal frame F1 has been received, and the subsequent first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 are extracted and the subsequent operations are performed. In different embodiments, the length and content of the sync header 411 can be determined according to the designer's requirements. For example, it is assumed that the length of the sync header 411 is 7 bits, and its content is, for example, "1011000". In this case, after the slave device 220 detects the specific bit combination of “1011000”, the slave device 220 can correspond to the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 respectively The first 1PPS signal 412 , the first time-of-day information 413 and the first phase compensation information 414 are obtained by presetting the signal length.

For example, assuming that the default signal lengths of the first 1PPS signal 412 , the first time of day information 413 and the first phase compensation information 414 are 1 bit, 80 bits and 32 bits respectively, the slave device 220 detects After reaching the sync header 411 whose content is “1011000”, the slave device 220 may be configured to: determine the second bit of the sync header 411 as the first 1PPS signal 412 ; The element is determined as the first time of day information 413; and the 32 bits after the first time of day information 413 are determined as the first phase compensation information 414, but not limited thereto.

In one embodiment, the main control device 210 can determine the first time of day information 413 in the synchronization signal frame F1 through the time of day circuit 213 . In one embodiment, the time-of-day circuit 213 may determine the first component 413a of the first time-of-day information 413 after obtaining the external time-of-day ET corresponding to the ith second. In one embodiment, the external time of day ET is, for example, an epoch time, which can be obtained by the time of day circuit 213 from the Internet or other similar external sources and used as the first time of day The first component 413a of the information 413. In the embodiment of the present invention, when the default signal length of the first time of day information 413 is assumed to be 80 bits, the first component 413a may occupy the first 48 bits of the first time of day information 413, for example, but But not limited to this.

In one embodiment, the time of day circuit 213 may estimate the second component 413b of the first time of day information 413 based on the system clock signal SC1. In one embodiment, the system clock signal SC1 may include a plurality of pulses, and the periods of these pulses may be determined according to the frequency of the system clock signal SC1, for example. For example, assuming that the frequency of the system clock signal SC1 is 125MHz, the period of these pulses is, for example, 8ns (ie, 1/125M). That is, a pulse occurs every 8ns.

In this case, in response to the time-of-day circuit 213 detecting one of the pulse waves of the system clock signal SC1, the time-of-day circuit 213 may increment the first count value. That is, when the frequency of the system clock signal SC1 is 125 MHz, the time-of-day circuit 213 increments the first count value every 8 ns. In one embodiment, the time-of-day circuit 213 may use the first count value as the second component 413b of the first time-of-day information 413 . In the embodiment of the present invention, when the default signal length of the first time of day information 413 is assumed to be 80 bits and the first component 413a occupies the first 48 bits of the first time of day information 413, the second component For example, 413b may occupy the last 32 bits of the first day time information 413, but it is not limited thereto.

In short, the first component 413a of the first time of day information 413 can be determined by the time of day circuit 213 based on the external time of day ET (which has an accuracy of only seconds), while the second component 413b of the first time of day information 413 (whose accuracy can be up to ns) can be calculated by the time-of-day circuit 413 by itself, but it is not limited to this.

In one embodiment, the first phase compensation information 414 is used to request the slave device 220 to modify the transmission time point of the first reference 1PPS signal RS in the second period T2 of the ith second.

Roughly speaking, the slave device 220 is configured to transmit the first reference 1PPS signal RS at a preset time point during the second period of every second. In one embodiment, the first reference 1PPS signal RS is, for example, 1, and other bits in the second period are, for example, 0. In other words, if the length of the second period is set to be N bits, only one of the N bits is 1, and the other bits are all 0, but not limited to this.

In one embodiment, if the master device 210 and the slave device 220 are perfectly synchronized, the master device 210 will receive a message from the slave device 220 at a preset time point in the second period of every second. The first reference 1PPS signal RS.

However, since the synchronization between the master device 210 and the slave device 220 is generally not perfect, the master device 210 may not receive the first reference 1PPS signal from the slave device 220 at the preset time point of the second period. For example, the main control device 210 may receive the first reference 1PPS signal RS before/after a preset time point in the second period of the i-1th second. That is, there may be a certain time difference between the reception time point when the main control device 210 receives the first reference 1PPS signal RS in the second period of the i-1th second and the preset time point. In this case, the compensation estimation circuit 211 of the main control device 210 can generate the corresponding first phase compensation information 414 based on the specific time difference, so as to convert the first phase compensation information 414 through the synchronization signal frame F1 in the first period T1 of the ith second. The phase compensation information 414 is notified to the slave device 220 .

According to the content of the first phase compensation information 414, the slave device 220 can The first reference 1PPS signal RS is sent in advance/delay in the second period T2, so as to try to allow the master control device 210 to receive the first reference 1PPS signal RS at a preset time point of the second period T2.

In one embodiment, the compensation estimation circuit 211 may obtain a preset time point in the second period of the i-1th second. In one embodiment, the compensation estimation circuit 211 can obtain the synchronization signal frame of the i-1th second, and add a preset guard time after the end time of the synchronization signal frame as the second period of the i-1th second. preset time point in . In different embodiments, the above-mentioned preset protection time can be determined according to the needs of the designer.

In one embodiment, assuming that the length of the second period is set to be N bits, the predetermined guard time may be set to, for example, N/2 bits, but not limited to this. For example, assuming that N is 240, the compensation estimation circuit 211 can add a preset guard time of 120 (ie 240/2) bits as the i-th after the synchronization signal frame of the i-1 second. - A preset time point in the second period of 1 second, but may not be limited thereto. In other words, if the master device 210 and the slave device 220 are perfectly synchronized, in the second period of the i-1th second, only the 120th bit should be 1 (ie, the first reference 1PPS signal RS) , all other bits are 0. However, if the master device 210 and the slave device 220 are not perfectly synchronized, the position where the first reference 1PPS signal RS appears will not be located at the 120th bit in the second period.

Therefore, the compensation estimation circuit 211 can obtain the specific time difference between the reception time point when the first reference 1PPS signal RS is received in the second period of the i-1th second and the above-mentioned preset time point, and determine the specific time difference based on the above-mentioned specific time difference. A phase compensation information 414 .

In one embodiment, in response to determining that the receiving time point is ahead of the predetermined time point by a specific time difference, the compensation estimation circuit 211 may set the first phase compensation information 414 to be used to request the slave device 220 to perform the second phase compensation in the ith second. In the period T2, the first reference 1PPS signal RS is sent after a certain time difference. For example, it is assumed that the position where the first reference 1PPS signal RS appears is the 118th bit of the second period, which means that the first reference 1PPS signal RS is received by the master device 210 in advance of 2 bits (ie, a specific time difference). . Therefore, the compensation estimation circuit 211 can set the first phase compensation information 414 to be used to request the slave device 220 to send the first reference 1PPS signal RS with a delay of 2 bits in the second period T2 of the ith second.

On the other hand, in response to determining that the receiving time point is behind the preset time point by a specific time difference, the compensation estimation circuit 211 may set the first phase compensation information 414 to be used to request the slave device 220 to perform the second period T2 of the ith second The first reference 1PPS signal RS is sent in advance by a specific time difference. For example, it is assumed that the position where the first reference 1PPS signal RS appears is the 123rd bit of the second period, which means that the first reference 1PPS signal RS is received by the master device 210 after being delayed by 3 bits (ie, a specific time difference). arrive. Therefore, the compensation estimation circuit 211 can set the first phase compensation information 414 to be used to request the slave device 220 to send the first reference 1PPS signal RS by 3 bits in advance in the second period T2 of the ith second.

In one embodiment, assuming that the default signal length of the first phase compensation information 414 is 32 bits, the most significant bit (MSB) of the first phase compensation information 414 can be used, for example, to indicate that the slave device 220 should send in advance/late. The first reference 1PPS signal RS, and the remaining 31 bits can be used to represent the above-mentioned specific time difference. For example, when the first When the MSB of a phase compensation information 414 is 1, the first phase compensation information 414 can be used, for example, to request the slave device 220 to send the first reference 1PPS signal RS after a specific time difference. In addition, when the MSB of the first phase compensation information 414 is 0, the first phase compensation information 414 may be used, for example, to request the slave device 220 to send the first reference 1PPS signal RS in advance by a specific time difference, but not limited thereto.

Based on this, in step S322, the processing circuit 222 of the slave device 220 corrects the sending time point of sending the first reference 1PPS signal RS in the second period T2 of the ith second according to the first phase compensation information 414.

In one embodiment, the processing circuit 222 of the slave device 220 obtains a preset time point at which the first reference 1PPS signal RS is transmitted in the second period T2 of the ith second. In one embodiment, the processing circuit 222 of the slave device 220 may add the preset guard time GT as the preset time point PT after the end time of the synchronization signal frame F1, but it is not limited thereto.

Then, in response to determining that the first phase compensation information 414 indicates that the first reference 1PPS signal RS is sent after a specific time difference, the processing circuit 222 can delay the preset time point PT by a specific time difference as the sending time point PT'. For example, when the MSB of the first phase compensation information 414 is 1, the processing circuit 222 can delay the predetermined time point PT according to the specific time difference indicated by the remaining 31 bits of the first phase compensation information 414 .

On the other hand, in response to determining that the first phase compensation information 414 indicates that the first reference 1PPS signal RS is sent in advance by a specific time difference, the processor 222 may advance the preset time point GT by a specific time difference as the transmission time point PT'. For example, when the MSB of the first phase compensation information 414 is 0, the processing circuit 222 may compensate according to the first phase The specific time difference indicated by the remaining 31 bits of the information 414 is advanced by a predetermined time point PT.

After that, in step S323, the processing circuit 222 of the slave device 220 sends the first reference 1PPS signal RS to the master device 210 at the sending time point PT' of the second period T2 of the ith second. Correspondingly, in step S312, the compensation estimation circuit 211 of the master device 210 receives the first reference 1PPS signal RS from the slave device 220 in the second period T2 of the ith second.

Then, in step S313, the compensation estimation circuit 211 determines the second phase compensation information to be sent to the slave device 220 in the first period of the i+1th second according to the reception time point of the first reference 1PPS signal RS.

In one embodiment, the manner in which the compensation estimation circuit 211 determines the second phase compensation information is similar to the manner in which the first phase compensation information 414 is determined. For example, the compensation estimation circuit 211 obtains the preset time point PT in the second period T2 of the ith second. For example, the compensation estimation circuit 211 may add the preset guard time GT as the preset time point PT in the second period T2 of the ith second after the end time of the synchronization signal frame F1, but it is not limited thereto. Afterwards, the compensation estimation circuit 211 can obtain the specific time difference between the receiving time point and the predetermined time point PT, and determine the second phase compensation information based on the specific time difference.

In one embodiment, in response to determining that the receiving time point is ahead of the preset time point PT by a certain time difference, the compensation estimation circuit 211 may set the second phase compensation information to be used to request the slave device 220 to perform the i+1th second. The first reference 1PPS signal RS is sent after a certain time difference in the second period of . On the other hand, in response to determining that the receiving time point is behind the preset time point PT by a certain time difference, the compensation estimation circuit 211 may The second phase compensation information is set for requesting the slave device 220 to send the first reference 1PPS signal RS in advance by a specific time difference in the second period of the i+1th second. For details of the above means, reference may be made to the descriptions of the previous embodiments, which will not be repeated here.

After that, the master device 210 can accordingly generate a synchronization signal frame F2 corresponding to the i+1th second, and then control the slave device 220 to modify the transmission of the first reference 1PPS signal in the second period of the i+1th second The transmission time point of the RS, but not limited to this.

As can be seen from the above, the embodiment of the present invention enables the master device 210 and the slave device 220 to communicate bidirectionally under the condition that only a single signal transmission line (eg, a synchronous serial bus) is connected. Further, the master control device 210 can correspondingly determine the phase compensation information to be provided to the slave device 220 in the next second according to the feedback of the first reference 1PPS signal RS by the slave device 220 in the previous second. In this way, the slave device 220 can correct the time point of sending the first reference 1PPS signal according to the phase compensation information, thereby enabling the master device 210 and the slave device 220 to achieve a better synchronization effect with each other.

Please refer to FIG. 5 , which is a schematic diagram of the main control device shown in FIG. 2 . In FIG. 5 , in addition to the compensation estimation circuit 211 , the processing circuit 212 and the time-of-day circuit 213 , the main control device 210 may further include an oscillator 511 , a phase-locked loop 512 and a bidirectional transmission controller 513 .

In one embodiment, the oscillator 511 is, for example, an oven controlled crystal oscillator (OCXO) or other precisely controllable clock signal generators, and can be used to provide the local clock signal LC1.

In one embodiment, the phase lock loop 512 is coupled to the oscillator 511 , the compensation estimation circuit 211 , the processing circuit 212 and the time of day circuit 213 , and can be implemented as a digital phase lock loop (DPLL). In one embodiment, the phase-locked loop 512 can receive the external clock signal EC, the external 1PPS signal EP and the local clock signal LC1 from the oscillator 511 , and can generate the system clock signal SC1 and the first 1PPS signal 412 accordingly.

In one embodiment, the time-of-day circuit 213 may obtain the system clock signal SC1 and the first 1PPS signal 412 from the phase-locked loop 512, and determine the second component 413b of the time-of-day information 413 according to the previous teaching.

In one embodiment, the compensation estimation circuit 211 may determine the first phase compensation information 414 according to the first reference 1PPS signal RS received during the second period of the i-1th second, and calculate the first phase compensation information 414 Provided to the preprocessing circuit 212 .

In one embodiment, the processing circuit 212 can obtain the system clock signal SC1 and the time-of-day information 413 from the time-of-day circuit 213 , the first 1PPS signal 412 from the phase-locked loop 512 , and the first signal from the compensation estimation circuit 211 . After the phase compensation information 414, the above information is encoded into the synchronization signal frame F1 through a mechanism such as PWM.

In one embodiment, the bidirectional transmission controller 513 can be connected to, for example, the slave device 220 , and can be used to control the bidirectional transmission between the master device 210 and the slave device 220 . For example, in the first period T1 of the ith second, the bidirectional transmission controller 513 can switch the synchronous serial bus between the master device 210 and the slave device 220 to a low impedance state (commonly known as low-impedance state). Z state), thereby allowing the processing circuit 212 to The generated synchronization signal frame F1 is sent to the slave device 220 .

In addition, in the second period T2 of the ith second, the bidirectional transmission controller 513 can, for example, switch the synchronous serial bus between the master device 210 and the slave device 220 to a high-impedance state (ie, the so-called high-Z state). ), so that the compensation estimation circuit 211 can listen to the first reference 1PPS signal RS from the slave device 220 . After that, the compensation estimation circuit 211 can generate the second phase compensation information according to the first reference 1PPS signal RS received in the second period T2, so that the processing circuit 212 can generate the synchronization signal corresponding to the i+1th second accordingly. frame. For related details, reference may be made to the descriptions in the previous embodiments, which will not be repeated here.

Please refer to FIG. 6 , which is a schematic diagram of the slave device shown in FIG. 2 . In FIG. 6 , in addition to the receiver 221 and the processing circuit 222 , the slave device 220 also includes an oscillator 611 and a bidirectional transmission controller 615 .

In one embodiment, the bidirectional transmission controller 615 may be configured to receive the corresponding synchronization signal frame from the master device 210 during a first period of each second, and to process the first reference 1PPS provided by the circuit 222 during the second period. The signal RS is sent to the master device 210 .

In one embodiment, the receiver 211 may include a phase locked loop 612 , a decoder 613 and a time of day circuit 614 . In one embodiment, in the first period T1 of the ith second, the decoder 613 may decode the synchronization signal frame F1 to obtain the synchronization signal frame F1 after obtaining the synchronization signal frame F1 from the master device 210 from the bidirectional transmission controller 615, for example. A 1PPS signal 412, time-of-day information 413, first phase compensation information 414, and a signal frequency FS corresponding to the synchronization signal frame F1.

In one embodiment, the decoder 613 may estimate the signal frequency FS of the synchronization signal frame F1 based on the time difference between the bits in the synchronization signal frame F1. For example, assuming that the time difference between the bits of the synchronization signal frame F1 is 8ns, the decoder 613 can estimate that the signal frequency FS of the synchronization signal frame F1 is 125MHz (ie 1/8ns), but it is not limited thereto.

In one embodiment, the oscillator 611 is, for example, an OCXO or other precisely controllable clock signal generators, and can be used to provide the local clock signal LC2.

In one embodiment, the phase-locked loop 612 is coupled to the oscillator 611 and the decoder 613, and can generate the system clock signals SC1 and SC1 based on the local clock signal LC2 and the signal frequency FS from the decoder 613 and the first 1PPS signal 412. The first reference 1PPS signal RS.

In one embodiment, the time-of-day circuit 614 is coupled to the decoder 613 and the phase-locked loop 612 , and can receive the time-of-day information 413 and the first phase compensation information 414 from the decoder 613 , and receive the system clock from the phase-locked loop 612 The signal SC1 and the first reference 1PPS signal RS.

In one embodiment, the time-of-day circuit 614 can use the first component 413a of the time-of-day information 413 as the first time component of the system time-of-day ST (the precision of which is seconds), and then based on the system clock signal SC1 and the time-of-day information 413 The second component 413b estimates the second time component of the system time of day ST (with an accuracy of ns).

For example, as mentioned above, the second component 413b is the first count value obtained by the time-of-day circuit 213, and its value (represented by K) represents the number of 8ns previously counted by the time-of-day circuit 213 . Therefore, the time of day circuit 614 can correspondingly The second time component of the system day time ST is obtained by counting K 8ns. After that, the time of day circuit 614 can combine (eg add) the first time component and the second time component to obtain the system day time ST, but it is not limited thereto.

In one embodiment, the time-of-day circuit 614 can correct the transmission time point of the first reference 1PPS signal RS based on the first phase compensation information 414 . For example, when the MSB of the first phase compensation information 414 is 1, the time-of-day circuit 614 can obtain the preset time point at which the first reference 1PPS signal RS is transmitted in the second period T2 and use the first phase compensation information 414 After the specific time difference indicated by the remaining 31 bits, the preset time point is delayed by the specific time difference to correct the sending time point of the first reference 1PPS signal RS. In addition, when the MSB of the first phase compensation information 414 is 0, the time-of-day circuit 614 can obtain the preset time point at which the first reference 1PPS signal RS is transmitted in the second period T2 and the remaining time from the first phase compensation information 414 After the specific time difference indicated by the 31 bits, the preset time point is advanced by the specific time difference to correct the transmission time point of the first reference 1PPS signal RS.

Afterwards, the processing circuit 222 may send the first reference 1PPS signal to the main control device 210 according to the corrected sending time point of the first reference 1PPS signal RS provided by the time-of-day circuit 614 .

Correspondingly, the main control device 210 can then adaptively adjust the second phase compensation information in the synchronization signal frame corresponding to the i+1th second according to the situation of receiving the first reference 1PPS signal RS in the second period T2. content, and its details will not be repeated here.

In one embodiment, after the slave device 220 obtains the first 1PPS signal 412 , the signal frequency FS and the system day time ST, the slave device 220 can perform synchronization accordingly operation in an attempt to synchronize with the master device 210, but not limited thereto.

In some embodiments, the ith second may further include the third period T3 shown in FIG. 4 , and the third period T3 is located between the second period T2 of the ith second and the synchronization signal of the ith+1th second During the first period of the frame F2, neither the master device 210 nor the slave device 220 may transmit/receive in the third period T3, but it is not limited thereto. In addition, in one embodiment, the master device 210 may only transmit the frequency signal (eg, 50% of the duty cycle) to the slave device 220 in the third period T3, so that the slave device 220 can maintain the relationship with the master device 210 accordingly. frequency synchronization.

In addition, in some embodiments, although the master device 210 does not send a signal to the slave device 220 in the second period T2, the phase-locked loop 612 of the slave device 220 can enter the holdovcr mode, so that the second period T2 The synchronization with the master device 210 is maintained in T2.

To sum up, the embodiment of the present invention enables the master device and the slave device to communicate bidirectionally under the condition that the master device and the slave device are only connected through a single synchronous serial bus. For example, the master device can accordingly determine the phase compensation information to be provided to the slave device in the next second according to the situation of the first reference 1PPS signal RS fed back by the slave device in the previous second. In this way, the slave device can correct the time point of sending the first reference 1PPS signal according to the phase compensation information, so that the master device and the slave device can achieve better synchronization effect with each other.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of this new model shall be determined by the scope of the appended patent application.

200: Sync System

210: Master control device

211: Compensation Estimation Circuit

212: Processing Circuits

213: Day Time Circuit

220: Servant Device

221: Receiver

222: Processing circuit

F1: Sync signal box

RS: first reference 1PPS signal

SC1: system clock signal

ET: External Day Time

Claims (11)

A main control device, comprising: a processing circuit configured to: During the first period of the ith second, a synchronization signal frame is sent to a slave device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) signal, a first time-of-day information and first phase compensation information, wherein the first phase compensation information is used to request the slave device to correct a sending time point of sending a first reference 1PPS signal during the second period of the i-th second; a compensation estimation circuit coupled to the processing circuit and configured to: receiving the first reference 1PPS signal from the slave device during the second period of the ith second; A second phase compensation information sent to the slave device in the first period of the i+1th second is determined according to a reception time point of the first reference 1PPS signal. The master device of claim 1, wherein the compensation estimation circuit is configured to: obtaining a preset time point in the second period of the i-th second; obtaining a specific time difference between the receiving time point and the preset time point; The second phase compensation information is determined based on the specific time difference. The master device of claim 2, wherein the compensation estimation circuit is configured to: In response to determining that the receiving time point is ahead of the preset time point by the specific time difference, the second phase compensation information is set to be used to request the slave device to delay the specific time during the second period of the i+1th second The time difference sends the first reference 1PPS signal; In response to determining that the receiving time point is behind the preset time point by the specific time difference, the second phase compensation information is set to be used to request the slave device to advance the second period in the i+1th second The first reference 1PPS signal is transmitted at a specific time difference. The master device of claim 2, wherein the compensation estimation circuit is configured to: A preset protection time is added after the end time of the synchronization signal frame as the preset time point in the second period of the ith second. The main control device of claim 1, further comprising a time of day circuit coupled to the processing circuit, wherein the time of day circuit is configured to: obtaining an external time of day corresponding to the ith second, and determining a first component of the first time of day information accordingly; A second component of the first time of day information is estimated based on a system clock signal. The master device of claim 5, wherein the external time of day includes an epoch time, and the time of day circuit is configured to use the epoch time as the first component of the first time of day information. The master device of claim 5, wherein the system clock signal includes a plurality of pulses, and the time of day circuit is configured to: In response to detecting one of the pulse waves of the system clock signal, a first count value is incremented, and the first count value is used as the second component of the first time of day information. The master control device of claim 1, wherein the synchronization signal sequentially includes the synchronization header, the first 1PPS signal, the first time of day information, and the first phase compensation information. A slave device, comprising: a receiver configured to: During the first period of the ith second, a synchronization signal frame is received from a master control device, wherein the synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) signal, a first pulse per second (1PPS) signal, and a Time of day information and first phase compensation information; a processing circuit coupled to the receiver and configured to: correcting a sending time point of sending a first reference 1PPS signal in the second period of the ith second according to the first phase compensation information; The first reference 1PPS signal is sent to the master device at the sending time point of the second period of the ith second. The slave device of claim 9, wherein the processing circuit is configured to: obtaining a preset time point at which the first reference 1PPS signal is sent in the second period of the ith second; In response to determining that the first phase compensation information indicates that the first reference 1PPS signal is sent after a specific time difference, the predetermined time point is delayed by the specific time difference as the sending time point; In response to determining that the first phase compensation information indicates that the first reference 1PPS signal is sent ahead of the specific time difference, the predetermined time point is advanced by the specific time difference as the sending time point. The slave device of claim 10, wherein the processing circuit is configured to: A preset protection time is added as the preset time point after the end time of the synchronization signal frame.

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