CN117155507A - Clock synchronization system and method - Google Patents

Abstract

The invention discloses a clock synchronization system and a method, wherein the system comprises the following steps: the equipment to be synchronized comprises: a processor, a clock signal generator, and a counter; the clock signal generator is used for generating a clock signal; the counter is used for sending the corresponding counting time to the processor; when the processor determines the main equipment of the equipment, the processor sends the first counting time to each slave equipment every synchronous period so that each slave equipment obtains the second counting time; when the processor determines that the equipment is the slave equipment, clock deviation among the equipment is obtained through calculation according to the first counting time, the second counting time and the data transmission time delay, and the clock signal generator of the slave equipment is adjusted through the deviation value, so that the frequency of the clock signal of the slave equipment can be consistent with that of the master equipment, the clock synchronization problem among the equipment can be solved without adopting equipment of the same model, and the system has better expandability.

Description

Clock synchronization system and method

Technical Field

The present invention relates to the field of clock synchronization technologies, and in particular, to a clock synchronization system and method.

Background

In the prior art, a data transmission system or a clock synchronization system usually adopts a crystal oscillator with the same type, a device with the same type and a CPU with the same type to process data, such as encoding audio data and decoding the audio data, so as to avoid clock errors among decoding devices as much as possible.

Disclosure of Invention

The embodiment of the invention provides a clock synchronization system and a clock synchronization method, which can effectively solve the problem of poor system expandability caused by too much limitation on equipment materials, namely, only equipment with the same model can be searched each time by searching a plurality of equipment with the same model in the prior art.

An embodiment of the present invention provides a clock synchronization system, including: a plurality of devices to be synchronized; for each device to be synchronized, comprising: a processor, a clock signal generator, and a counter;

the clock signal generator is used for generating a clock signal and sending the clock signal to the processor;

the counter is used for counting the pulse number of the clock signal according to a preset counting period and sending corresponding counting time to the processor;

the processor is used for judging whether the equipment to be synchronized is a master equipment or a slave equipment according to the IP address of the equipment to be synchronized and the IP addresses of the rest equipment to be synchronized;

if the equipment to be synchronized is judged to be the master equipment, when each synchronization period arrives, acquiring a first counting time of a counter of the equipment to be synchronized, and simultaneously transmitting a data packet containing the first counting time to the slave equipment;

if the equipment to be synchronized is judged to be the slave equipment, after the data packet is received, acquiring a second counting time of a counter of the equipment to be synchronized; according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, clock deviation of a counter between the master device and the slave device is calculated, and according to the clock deviation, the frequency of a clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of a clock signal corresponding to a processor of the master device when the first counting time is acquired.

Preferably, the processor is configured to determine, according to an IP address of a device to be synchronized where the processor is located and IP addresses of other devices to be synchronized, whether the device to be synchronized is a master device or a slave device, where the processor is located, including:

and the processor is used for comparing the value of the target IP address adopted by the equipment to be synchronized with the values of the IP addresses adopted by other equipment to be synchronized, taking the equipment to be synchronized where the processor is positioned as a master equipment when the value of the target IP address is judged to be minimum, and taking the equipment to be synchronized where the processor is positioned as a slave equipment when the value corresponding to the target IP address is judged not to be minimum.

Preferably, the processor, before calculating the clock skew of the counter between the master device and the slave device, is further configured to:

sending a first message to a master device so that the master device returns a second message containing the receiving time of the first message to the slave device;

and calculating to obtain the data transmission time delay between the master device and the slave device according to the sending time of the first message and the receiving time of the first message.

Preferably, the calculating to obtain the clock deviation of the counter between the master device and the slave device according to the first count time, the second count time and the data transmission delay between the master device and the slave device includes:

the clock deviation of the counter between the master device and the slave device is calculated according to the following formula:

Offset＝(T2-T1)-[(T2-T1)+(T4-T3)]/2；

wherein, offset is clock Offset, T1 is first count time, T2 is second count time, T3 is transmission time of first message time, and T4 is reception time of first message.

Preferably, the clock signal generator is a multi-channel clock signal generator;

the multi-channel clock signal generator includes: an oscillator, a phase-locked loop, and a number of frequency dividers;

according to the clock deviation, the frequency of the clock signal generator of the equipment to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of the clock signal corresponding to the processor of the master equipment when the processor acquires the first counting time, and the method comprises the following steps:

when the clock deviation is judged to be positive, the phase-locked loop is adjusted to increase the frequency value of the phase-locked loop and the frequency value of each frequency divider until the adjusted frequency is consistent with the frequency of a clock signal corresponding to the processor of the main equipment when the first counting time is acquired;

and when the clock deviation is judged to be negative, the phase-locked loop is adjusted so as to reduce the frequency value of the phase-locked loop and the frequency value of each frequency divider until the adjusted frequency is consistent with the frequency of a clock signal corresponding to the processor of the main equipment when the first counting time is acquired.

Preferably, the method further comprises: a crystal oscillator;

the crystal oscillator is connected with an oscillator in the multichannel clock signal generator.

Preferably, the device to be synchronized is an audio processing device;

the audio processing apparatus further includes: a digital signal encoder and a network chip;

the digital signal encoder is used for acquiring audio data or decoding the audio data sent by other audio processing equipment;

the network chip is used for transmitting the audio data acquired by the audio processing equipment to the other audio processing equipment through a preset network protocol, or receiving the audio data sent by the other audio processing equipment through the preset network protocol.

Based on the system embodiment, the invention correspondingly provides a method item embodiment.

The embodiment of the invention provides a clock synchronization method which is applied to a processor in the clock synchronization system;

the clock synchronization method comprises the following steps:

when judging that the equipment to be synchronized is the master equipment according to the IP address of the equipment to be synchronized, acquiring a first counting time of a counter of the equipment to be synchronized when each synchronization period arrives, and simultaneously transmitting a data packet containing the first counting time to the slave equipment;

when judging that the equipment to be synchronized is slave according to the IP address of the equipment to be synchronized, acquiring a second counting time of a counter of the equipment to be synchronized when receiving the data packet sent by the master equipment; according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, clock deviation of a counter between the master device and the slave device is calculated, and according to the clock deviation, the frequency of a clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of a clock signal corresponding to a processor of the master device when the first counting time is acquired.

The invention has the following beneficial effects:

the embodiment of the invention provides a clock synchronization system and a method, wherein the system comprises the following components: a plurality of devices to be synchronized; for each device to be synchronized, comprising: a processor, a clock signal generator, and a counter; the clock signal generator is used for generating a clock signal and sending the clock signal to the processor; the counter is used for counting the pulse number of the clock signal according to a preset counting period and sending the corresponding counting time to the processor. Compared with the prior art, the method and the device have the advantages that firstly, a main device and a plurality of slave devices are determined according to the IP addresses adopted by the devices to be synchronized during communication through the processor of the devices; after determining the master device, a processor in the master device can perform clock calibration once every preset time period, namely, when each synchronization period arrives, a first counting time corresponding to a counter in the master device is acquired, meanwhile, a data packet containing the first counting time is sent to each slave device, so that each slave device records a current second counting time when the data packet is obtained, because the time of the counter is obtained according to the frequency corresponding to a clock signal entering the counter and the accumulated times, different counter times can correspond to different signal frequencies, namely, the expected counter time can be obtained by adjusting the signal frequency, namely, the clock deviation of the counter between the slave device and the master device is calculated and obtained according to the first counting time, the second counting time and the data transmission time delay between the master device, and the clock signal generator of the slave device is adjusted through the deviation value, so that the clock signal frequency of the slave device can be consistent with the clock signal of the master device when the counting time of the slave device is consistent with the counting time of the master device, the clock signal of the slave device is kept consistent with the clock signal of the master device, the clock signal of the slave device is confirmed to be adjusted, and the data between the slave device and each slave device can be prevented from being adjusted, and the data transmission time between the master device and the master device is not required to be synchronously obtained, and the clock signal of the slave device is not needed, and the master device is required to be synchronously adjusted, and the data is not needed to be simultaneously, and the data is required to be synchronously adjusted.

Drawings

Fig. 1 is a schematic structural diagram of an audio processing device when the device to be synchronized is an audio processing device according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a multi-channel clock signal generator according to an embodiment of the invention.

Fig. 3 is a schematic diagram of data transmission between a master device and a slave device according to an embodiment of the present invention.

Fig. 4 is a flowchart of a clock synchronization method according to an embodiment of the invention.

The reference numerals in fig. 1 are: CPU master-slave device processor-1, multichannel clock signal generator-2, digital signal encoder-3, crystal oscillator-4, IIC control line-5 network chip clock-6, clock signal-7, I2S_MCLK-8, I2S_SCLK-9, I2S_LRCLK-10, network chip-11.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

An embodiment of the present invention provides a clock synchronization system, including: a plurality of devices to be synchronized;

for each device to be synchronized, comprising: a processor, a clock signal generator, and a counter;

the clock signal generator is used for generating a clock signal and sending the clock signal to the processor;

the counter is used for counting the pulse number of the clock signal according to a preset counting period and sending corresponding counting time to the processor;

the processor is used for judging whether the equipment to be synchronized is a master equipment or a slave equipment according to the IP address of the equipment to be synchronized and the IP addresses of the rest equipment to be synchronized;

if the equipment to be synchronized is judged to be the master equipment, when each synchronization period arrives, acquiring a first counting time of a counter of the equipment to be synchronized, and simultaneously transmitting a data packet containing the first counting time to the slave equipment;

if the equipment to be synchronized is judged to be the slave equipment, after the data packet is received, acquiring a second counting time of a counter of the equipment to be synchronized; according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, clock deviation of a counter between the master device and the slave device is calculated, and according to the clock deviation, the frequency of a clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of a clock signal corresponding to a processor of the master device when the first counting time is acquired.

In the embodiment of the invention, the clock synchronization system comprises a plurality of devices to be synchronized, only one device is used as a master device in the plurality of devices to be synchronized, and the frequencies of clock signals of other slave devices are always the same according to the frequencies of the master device, namely the master clock device provides a synchronization clock source for the system, and the slave clock device uses the master clock device as the clock source to perform clock synchronization, so that the clock synchronization among the devices to be synchronized can be realized, the data processing effect of the devices when the devices process data can be improved, and the performance of the devices can be improved.

Fig. 1 is a schematic structural diagram of an audio processing device corresponding to a device to be synchronized according to an embodiment of the present invention.

In a preferred embodiment, the present invention provides an audio data processing system based on clock synchronization for collecting or decoding audio data, the audio data processing system comprising a plurality of audio processing devices, i.e. each audio processing device may be a device to be synchronized, each audio processing device being for collecting or decoding audio data, wherein only one audio processing device is the master device.

In a preferred embodiment, the audio processing device comprises a CPU master-slave device processor-1, a multi-channel clock signal generator-2, a digital signal encoder-3, a crystal oscillator-4, an IIC control line-5 and a network chip clock-6; wherein the CPU master-slave device processor is also connected with the multichannel clock signal generator through a counter (not shown in the figure); the multi-channel clock signal generator generates a clock signal-7 for providing a CPU master-slave device processor and a digital signal encoder with clock signals for the acquisition and decoding of audio signals.

The multichannel clock signal generator also generates clock signals of I2S_MCLK, I2S_SCLK and I2S_LRCLK, which are respectively a master clock, a bit clock and a left clock and a right clock of I2S, and provides the same I2S clock for the digital signal encoder and the CPU master-slave device processor, thereby ensuring clock synchronism in data transmission engineering.

The digital signal encoder is used for acquiring audio data or decoding the audio data sent by other audio processing equipment; the digital signal encoder and the CPU master-slave device processor share the master clock, the bit clock and the left-right clock of the I2S.

The output port of the multichannel clock signal generator is respectively connected with the processor, the digital signal encoder and the network chip, and the input port of the multichannel clock signal generator is also connected with the processor; the processor is also connected with the digital signal encoder and the network chip respectively. Wherein the CPU master-slave device processor is connected with the multi-channel clock signal generator through an IIC control line,

the network chip is used for transmitting the audio data acquired by the audio processing equipment to the other audio processing equipment through a preset network protocol, or receiving the audio data sent by the other audio processing equipment through the preset network protocol. The CPU drives the network chip to realize network communication, the Ethernet MAC inside the CPU supports IEEE1588, and the clock calibration between the master device and the slave device can be realized through PTPV1 or PTPV2 protocol when the master device and the slave device are in network communication.

The structure of the multi-channel clock signal generator is shown in fig. 2, and the multi-channel clock signal generator is used for generating a clock signal and transmitting the clock signal to the processor; wherein the multi-channel clock signal generator comprises: an oscillator, a fractional frequency pll, and a number of fractional frequency dividers; different clock frequencies can be generated by adjusting the parameters of the fractional-n phase-locked loop and the fractional-n frequency divider, and clock signals for acquisition and decoding of audio signals are provided for the CPU master-slave device processor and the digital signal encoder.

The crystal oscillator is connected with an oscillator in the multichannel clock signal generator and provides clock frequency for the multichannel clock signal generator.

The counter is used for counting the pulse number of the clock signal according to a preset counting period and sending corresponding counting time to the processor; when the frequency of the clock signal of the master device is set to be 50MHz, the cycle count of the counter is set to be 20ns; when the CPU master-slave processor is triggered by an external interrupt to acquire the 50MHz clock signal generated by the multi-channel clock signal generator, the accumulated count is used as a clock reference, for example, accumulated 1000 times, that is, the count time is 1000×20=20us.

The CPU master-slave device processor is a processor chip of the master-slave device, sets the frequency value of a decimal frequency division phase-locked loop (PLL) of the clock signal generator through I2C communication, sets decimal frequency dividers of the output ends of all clock frequencies, and outputs different clock frequencies to provide clock signals for the network chip and the digital signal encoder. Furthermore, the digital signal encoder is driven by the I2C and the I2S, so that the audio data acquisition and decoding are realized. And the CPU master-slave device processor is connected with the network chip to drive the network chip to realize network communication.

It can be understood that all devices adopt the model diagram shown in fig. 1, and each master device and each slave device perform network communication according to the PTPV1 or PTPV2 protocol, when in communication, the 32-bit IP address value between the devices is the smallest as the master clock device, and the other devices are the slave clock devices, and each time the synchronization period of the master clock device arrives at 250ms, clock calibration is performed, so that each slave device can obtain the clock Offset between the slave clock device and the master clock device.

Specifically, as shown in fig. 3, the steps of the method for implementing clock synchronization between the master device and the slave device are as follows:

step 1: firstly, all equipment CPU processors drive a multi-channel clock signal generator to output different clock signals through IIC, and clock signals are provided for a network chip and a digital signal encoder; when the CPU processor externally interrupts the IO pin, the CPU processor is triggered to enter a clock calibration period through external interruption, and the accumulated count and time corresponding to the counter are used as time references;

step 2: network communication is carried out between the master device and the slave device, and according to the PTPV1 or PTPV2 protocol, the processing of each device judges that the device to be synchronized is the master device or the slave device according to the IP address of the device to be synchronized and the IP addresses of the rest devices to be synchronized;

specifically, comparing the value of the target IP address adopted by the device to be synchronized with the values of the IP addresses adopted by other devices to be synchronized, when the value of the target IP address is determined to be minimum, taking the device to be synchronized where the processor is located as the master device, and when the value corresponding to the target IP address is determined to be not minimum, taking the device to be synchronized where the processor is located as the slave device. It can be understood that the device with the minimum 32-bit IP address value is used as the master clock device, and the other devices are slave clock devices;

step 3: when each synchronization period arrives, a processor serving as a master clock device acquires a first counting time of a counter of the device to be synchronized, and simultaneously sends a data packet containing the first counting time to a slave device; in a preferred embodiment, the synchronization period is 250ms, i.e. the master clock device performs a clock calibration every 250ms, so that the slave clock device calculates the clock Offset of both;

and S4, after the clock offset is acquired from the CPU in the clock equipment, driving the multi-channel clock signal generator through the IIC, and adjusting the value of the fractional-N phase-locked loop (PLL) through the register address. Illustratively, all clock frequencies share a fractional PLL, e.g., 900MHz.

If the Offset is greater than 0, which means that the 50MHz clock frequency generated by the multi-channel clock signal generator is higher than the clock frequency of the master clock device, the slave clock device needs to reduce the frequency value of the fractional PLL of the multi-channel clock signal generator, because the PLL is 900MHz, the PLL clock needs to be set to 900000000- (900/45 x Offset);

if the Offset is less than 0, it means that the 50MHz clock frequency generated by the multi-channel clock signal generator is lower than the clock frequency of the master clock device, and the slave clock device needs to increase the frequency value of the fractional PLL of the multi-channel clock signal generator. For example, the PLL is 900MHz, and the PLL clock is set to 900000000+ (900/45 x offset);

the slave clock equipment keeps the synchronization between the 50MHz frequency of the slave clock equipment and the 50MHz frequency of the master clock equipment by continuously fine-adjusting the frequency value of the fractional-division phase-locked loop PLL of the multi-channel clock signal generator, and the IIS of the CPU and the clock frequency of the digital signal encoder are generated by the fractional-division phase-locked loop PLL of the multi-channel clock signal generator through the frequency divider, so that the clock synchronization during encoding and decoding of audio data is ensured, and the problem of sound interruption or sound delay during audio decoding of all the slave equipment is solved.

In a preferred embodiment, if the CPU processor in the device determines that the device is the master device, when each synchronization period arrives, the CPU processor in the device obtains a first count time of a counter of the device, and sends a data packet containing the first count time to the slave device;

if the equipment is judged to be the slave equipment, after the data packet is received, acquiring a second counting time of a counter of the equipment, and simultaneously sending a first message to the master equipment so that the master equipment returns a second message containing the receiving time of the first message to the slave equipment;

after the data transmission time delay between the master device and the slave device is calculated according to the sending time of the first message and the receiving time of the first message, the clock deviation of the counter between the master device and the slave device is calculated according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, and according to the clock deviation, the frequency of the clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of the clock signal corresponding to the processor of the master device when the first counting time is acquired.

The calculating to obtain the clock deviation of the counter between the master device and the slave device according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device comprises the following steps:

the clock deviation of the counter between the master device and the slave device is calculated according to the following formula:

Offset＝(T2-T1)-[(T2-T1)+(T4-T3)]/2；

wherein, offset is clock Offset, T1 is first count time, T2 is second count time, T3 is transmission time of first message time, and T4 is reception time of first message.

Specifically, as shown in fig. 3, the acquisition of the master-slave clock error Offset by the PTP protocol between devices includes the following steps:

step 1: the master clock device sends a frame of PTPV1 or PTPV2 data as "Sync Message" to the multicast address "224.0.1.129" in a multicast form every 250ms, and immediately after recording the counter time T1, sends "show_up Message T1".

Step 2: and the slave clock equipment records the counter time T2 according to the received PTP data packet Sync Message.

Step 3: the slave clock sends a delay_req message to the master clock, the sending time T3 is recorded, the receiving time T4 at the moment is recorded after the master clock receives the message delay_resp carrying the T4 is sent to the slave clock by the master clock.

Thus, the slave clock device obtains all times of T1, T2, T3 and T4, calculates round trip time difference, and then takes the average value of [ (T2-T1) + (T4-T3) ]/2, and the clock deviation of the slave clock relative to the master clock is: offset= (T2-T1) - [ (T2-T1) + (T4-T3) ]/2.

T2 is the current count time of the slave clock device itself obtained by the slave clock device, T1 is the current count time of the master clock device itself obtained by the master clock device, T2-T1 is the clock deviation between the slave clock device and the master clock device, and the clock deviation comprises the network transmission time round trip time, so the round trip time difference of the network transmission is subtracted, and therefore, the clock deviation of the slave clock relative to the master clock is as follows: offset= (T2-T1) - [ (T2-T1) + (T4-T3) ]/2.

In the system of the invention, network communication is carried out among a plurality of devices, one of the devices is used as a master clock device, the other devices are all slave clock devices, the logic processing algorithm is utilized, 50MHz clock signals are used as clock references, clock errors of the slave clock devices and the master clock devices are obtained among the devices through a PTP protocol, and each slave clock device adjusts the frequency value of a decimal frequency division phase-locked loop (PLL) of a multichannel clock signal generator in real time, so that the 50MHz frequency of the slave clock device is synchronous with the 50MHz frequency of the master clock device. Because the IIS of the CPU and the clock frequency of the digital signal encoder are both generated by the fractional frequency phase-locked loop PLL of the multi-channel clock signal generator through the frequency divider, the clock synchronization during encoding and decoding of the audio data is ensured.

The invention achieves the aim of clock synchronization by acquiring the clock error between the master device and the slave device and continuously fine-adjusting the voltage-controlled crystal oscillator, and the scheme can theoretically ensure the consistency of clock signals of the digital signal encoder after the frequency division of the CPU. The invention takes the acquired count value captured by 50MHz clock as the hardware timestamp of PTP, can well ensure the clock synchronization between the master device and the slave device, and has the maximum error precision of 20ns. The 50MH signal is used as a feedback point, and the frequency value of a fractional frequency division phase-locked loop (PLL) of the multichannel clock signal generator is finely adjusted, so that the clock synchronization of the digital signal encoder and the I2S of the CPU processor is ensured. The network audio transmission system applied by the synchronous clock described above was found to be a clock error of +/-1 us. High quality, high sampling rate audio transmission can be satisfied.

The invention realizes the clock synchronization among the devices to be synchronized, not only can fundamentally solve the influence of clock frequency errors of crystal oscillators among different devices (decoding devices) on the devices, but also can solve the influence of CPU frequency division coefficients of different devices on the devices. The model of each device is not required to be the same, only one device is ensured to be used as a master clock device in the network audio transmission system, the other devices are all slave clock devices, the slave clock devices follow the clock frequency of the master clock device, clock synchronization can be realized only by adjusting the signal generator chip of the slave clock device in real time, and the processing speed of the device materials and the CPU is not excessively required. The invention can fundamentally solve the influence of clock frequency errors of crystal oscillators among different devices on the devices, and can also solve the influence of CPU frequency division coefficients of different devices on the devices.

As shown in fig. 4, on the basis of the above-mentioned various embodiments of the clock synchronization system, the present invention correspondingly provides method item embodiments;

an embodiment of the present invention provides a clock synchronization method, which is applied to a processor in the clock synchronization system, including:

when judging that the equipment to be synchronized is the master equipment according to the IP address of the equipment to be synchronized, acquiring a first counting time of a counter of the equipment to be synchronized when each synchronization period arrives, and simultaneously transmitting a data packet containing the first counting time to the slave equipment;

when judging that the equipment to be synchronized is slave according to the IP address of the equipment to be synchronized, acquiring a second counting time of a counter of the equipment to be synchronized when receiving the data packet sent by the master equipment; according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, clock deviation of a counter between the master device and the slave device is calculated, and according to the clock deviation, the frequency of a clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of a clock signal corresponding to a processor of the master device when the first counting time is acquired.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (8)

1. A clock synchronization system, comprising: a plurality of devices to be synchronized; for each device to be synchronized, comprising: a processor, a clock signal generator, and a counter;

the clock signal generator is used for generating a clock signal and sending the clock signal to the processor;

the counter is used for counting the pulse number of the clock signal according to a preset counting period and sending corresponding counting time to the processor;

the processor is used for judging whether the equipment to be synchronized is a master equipment or a slave equipment according to the IP address of the equipment to be synchronized and the IP addresses of the rest equipment to be synchronized;

if the equipment to be synchronized is judged to be the master equipment, when each synchronization period arrives, acquiring a first counting time of a counter of the equipment to be synchronized, and simultaneously transmitting a data packet containing the first counting time to the slave equipment;

if the equipment to be synchronized is judged to be the slave equipment, after the data packet is received, acquiring a second counting time of a counter of the equipment to be synchronized; according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, clock deviation of a counter between the master device and the slave device is calculated, and according to the clock deviation, the frequency of a clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of a clock signal corresponding to a processor of the master device when the first counting time is acquired.

2. The clock synchronization system of claim 1, wherein the processor is configured to determine, according to an IP address of a device to be synchronized and IP addresses of other devices to be synchronized, whether the device to be synchronized is a master device or a slave device, the processor includes:

and the processor is used for comparing the value of the target IP address adopted by the equipment to be synchronized with the values of the IP addresses adopted by other equipment to be synchronized, taking the equipment to be synchronized where the processor is positioned as a master equipment when the value of the target IP address is judged to be minimum, and taking the equipment to be synchronized where the processor is positioned as a slave equipment when the value corresponding to the target IP address is judged not to be minimum.

3. A clock synchronization system as defined in claim 1, wherein the processor, prior to calculating the clock bias of the counter between the master and slave devices, is further configured to:

sending a first message to a master device so that the master device returns a second message containing the receiving time of the first message to the slave device;

and calculating to obtain the data transmission time delay between the master device and the slave device according to the sending time of the first message and the receiving time of the first message.

4. A clock synchronization system according to claim 3, wherein the calculating the clock bias of the counter between the master device and the slave device according to the first count time, the second count time, and the data transmission delay between the master device and the slave device comprises:

the clock deviation of the counter between the master device and the slave device is calculated according to the following formula:

Offset＝(T2-T1)-[(T2-T1)+(T4-T3)]/2；

wherein, offset is clock Offset, T1 is first count time, T2 is second count time, T3 is transmission time of first message time, and T4 is reception time of first message.

5. A clock synchronization system as defined in claim 1, wherein the clock signal generator is a multi-channel clock signal generator;

the multi-channel clock signal generator includes: an oscillator, a phase-locked loop, and a number of frequency dividers;

according to the clock deviation, the frequency of the clock signal generator of the equipment to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of the clock signal corresponding to the processor of the master equipment when the processor acquires the first counting time, and the method comprises the following steps:

when the clock deviation is judged to be positive, the phase-locked loop is adjusted to increase the frequency value of the phase-locked loop and the frequency value of each frequency divider until the adjusted frequency is consistent with the frequency of a clock signal corresponding to the processor of the main equipment when the first counting time is acquired;

and when the clock deviation is judged to be negative, the phase-locked loop is adjusted so as to reduce the frequency value of the phase-locked loop and the frequency value of each frequency divider until the adjusted frequency is consistent with the frequency of a clock signal corresponding to the processor of the main equipment when the first counting time is acquired.

6. A clock synchronization system as recited in claim 5, further comprising: a crystal oscillator;

the crystal oscillator is connected with an oscillator in the multichannel clock signal generator.

7. A clock synchronization system as defined in claim 1, wherein the device to be synchronized is an audio processing device;

the audio processing apparatus further includes: a digital signal encoder and a network chip;

the digital signal encoder is used for acquiring audio data or decoding the audio data sent by other audio processing equipment;

the network chip is used for transmitting the audio data acquired by the audio processing equipment to the other audio processing equipment through a preset network protocol, or receiving the audio data sent by the other audio processing equipment through the preset network protocol.

8. A clock synchronization method, characterized by being applied to a processor in a clock synchronization system as claimed in any one of claims 1-7;

the clock synchronization method comprises the following steps:

when judging that the equipment to be synchronized is the master equipment according to the IP address of the equipment to be synchronized, acquiring a first counting time of a counter of the equipment to be synchronized when each synchronization period arrives, and simultaneously transmitting a data packet containing the first counting time to the slave equipment;

when judging that the equipment to be synchronized is slave according to the IP address of the equipment to be synchronized, acquiring a second counting time of a counter of the equipment to be synchronized when receiving the data packet sent by the master equipment; according to the first counting time, the second counting time and the data transmission time delay between the master device and the slave device, clock deviation of a counter between the master device and the slave device is calculated, and according to the clock deviation, the frequency of a clock signal generator of the device to be synchronized is adjusted, so that the adjusted frequency is consistent with the frequency of a clock signal corresponding to a processor of the master device when the first counting time is acquired.