RU1777245C - Error detector for digital data transmission channel - Google Patents

Abstract

The invention can be used in apparatus for statistical studies of discrete communication channels and information storage devices. The aim of the invention is to increase the reliability of error detection. The device for detecting errors contains a shift register 1, block 2 of adders 4 modulo two, the first majority element 3, adder 5 modulo two, the second majority element 4, element 6 OR NOT, element 8 OR, counter 7 pulses, decoder 10, Element 9 I. The introduction of the second majority element, the OR-NOT, AND, OR, counter and decoder elements allows you to register clock synchronization failures in the channel under study, as well as block the error detection output for the duration of the synchronization failure device during which An incorrect error stream is generated. In this case, the response threshold of the first majority element is selected to be larger than I / 2, and the second - less than I / 2, where I is the number of inputs of the majority element. Thereby, the overall reliability of error detection will be improved. 2 ill., 3 tablets &

Description

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The invention relates to techniques for telecommunication and magnetic recording and can be used in apparatus for statistical studies of discrete communication channels and information storage media.

A device is known for detecting and recording a discrete communication channel error stream comprising an error detection unit, a shift register, a 5 block of keys, an OR circuit, an intermediate memory unit, a control unit, and a register 1.

The error detection unit of this device does not allow the detection of a clock synchronization failure in the communication channel, which reduces the reliability of error detection.

Of the known devices, the closest to the proposed one is a device for detecting and recording errors of a discrete transmission channel and accumulating errors, comprising an error detection unit, a shift register, AND elements, counters, an intermediate memory unit, an OR element, a pulse shaper, a register torus and control unit 2.

However, this device does not have sufficient reliability of error detection due to the fact that it does not allow registering clock synchronization failures in the channel under study, which appear in the insertion or dropout of characters in the information stream.

The aim of the invention is to increase the reliability of error detection.

This goal is achieved in that a block of adders modulo two, the first and second majority elements, an OR-NOT element are introduced into the device for detecting errors of a discrete information transmission channel containing a shift register, an OR element, an AND element, and a pulse counter. modulo two adder and decoder, the output of which is connected to the first inputs of AND element and OR element and is the first output of the device. The first output of the shift register is connected to the first inputs of the first and second majority elements and the adder modulo two, the output of which is connected to the second input of the element And, the output of which is the second output of the device. The information input of the shift register is the information input of the device, the clock input of the shift register is combined with the second input of the OR element and is the clock input of the device. The second outputs of the shift register are connected to the corresponding inputs of the adders modulo two blocks, the outputs of which are connected respectively to the second inputs of the first and second majority elements, the output of the second majority element is connected to the first input of the element AND L AND NOT, the output of the first majority element is connected to the second inputs the adder modulo two and the element AND AND NOT, whose output is connected to the reset input of the pulse counter, the counting input and outputs of which are connected respectively to the output of the OR element and the inputs ifrator.

The introduction of a block of adders modulo two, the first and second majority elements, an OR-NOT element, an adder modulo two and a decoder allows you to register clock synchronization failures in the channel under study and, in addition, block the error detection output while the synchronization failure device is processing, in the course of which there is an incorrect formation of the error stream. In this way, the reliability of error detection is improved.

The threshold of operation of the first majority element is selected more than I / 2, and the second is less than I / 2, where I is the number of inputs of the majority element.

In FIG. 1 shows a block diagram of a device;

in FIG. 2 is an example implementation of a device.

The device for detecting errors contains a shift register 1, block 2 adders modulo two, first and second majority elements 3, 4, adder 5 modulo two, element 6 OR NOT, pulse counter 7, element 8 OR, element 9 AND, decoder 10.

The output of the decoder 10 is connected to the first inputs of the OR element 8 and the And element 9 and is the first output of the device. The first output of the shift register 1 is connected to the first inputs of the first 3 and second 4 majority elements and an adder 5 modulo two, the output of which is connected to the second input of the 9th element. The output of which is the second output of the device. The information input of the shift register 1 is the information input of the device, the clock input of the shift register 1 is combined with the second input of the OR element 8 and is the clock input of the device. The second outputs of the shift register 1 are connected to the corresponding inputs of the adder block 2 modulo two, the outputs of which are connected respectively to the second inputs of the first and second majority elements 3, 4. The output of the second majority element 4 is connected to the first input of the element 6 OR NOT, and the output of the first majority

element 3 - to the second inputs of the adder 5 modulo two and the element 6 OR NAND, the output of which is connected to the reset input of the counter 7. pulses, the counting input and the outputs of which are connected respectively to the output of element 8 OR and the inputs of the decoder 10.

The device operates as follows. As a test signal for evaluating the noise immunity of a discrete information transmission channel, a pseudorandom sequence of pulses arriving at the information input of the device is used. The test sequence is accompanied by a clock frequency supplied to the clock input of the device. Due to interference in the channel, errors are introduced into the pseudo-random sequence, which lead to the replacement of the binary symbols of the sequence with their inverse value. In addition, due to errors in the clock sequence, clock synchronization failures occur, which are expressed in inserts or lost characters in the pseudo-random sequence when it is received. The sequence of pseudorandom characters is fed to the information input of the shift register 1 and shifted along it synchronously with the clock frequency supplied to the clock input of the register 1. The length of the shift register 1 is equal to the length of the pseudorandom sequence and is n 2k-1 cells, where to 3.4 .. .. The state of this register is analyzed at each moment of time that comes after the next clock pulse, by block 2 adders modulo two, the number of adders by

p -1 module two which is equal to - - and which are connected to the corresponding outputs of register 1.

If there are no errors in the sequence of pseudo-random symbols on each cycle, all adders modulo two blocks 2 will take values equal to the value of the symbol in the last bit of shift register 1. Thus, it is possible to express one of the characters in register 1, precisely in its last bit, through the characters of the other bits of register 1.

The thresholds of the majority elements 3 and 4 are set as follows:

T is the threshold value of the second majority element 4 satisfies the inequality T I / 2;

H is the threshold value of the first majority element 3 satisfies the expression H I-T.

If the number of units at the inputs of the majority elements 3 and 4 is greater than or equal to H, then one is set at the output of the majority element 3, and at the output

majority element 4 is set to zero.

If the number of units at the inputs of the majority elements 3 and 4 does not exceed the threshold level T, then at the output of the majority:

0 of the tare element 3 will be set to zero, and at the output of the majority element 4 - one.

If the number of units at the inputs of the majority elements 3 and 4 lies in the interval from T + 1 to H - 1, then the paths are set at the outputs of the majority elements 3 and 4, and a unit is established at the output of element 6.

Thus, if among any n successive characters of the pseudo-random sequence located in the shift register 1 there are no more than T erroneous, then it is possible to correctly determine the value of the character in the output bit of register 1.

5 If the number of erroneous characters lies in the range from T + 1 to H - 1, which will occur if the structure of the pseudo-random sequence is violated in the event of clock synchronization failure, then unit 0 will be established at the output of element 6, and thereby, the fact of clock synchronization failure will be recorded .

An adder 5 modulo two calculates erroneous symbols. Signals from the majority element 3 and the last digit of register 1 are received at its inputs. If an erroneous character is received from register 1, then it does not coincide with the signal value from the majority element 3 and

At the output of adder 5 modulo two, one is set.

Since, in the event of a clock synchronization failure in register 1, the structure of the pseudo-random sequence 5 is violated, the formation of the error stream at the output of the adder 5 modulo two will occur incorrectly until the synchronization failure passes through register 1. At this time, the output of the adder 5 by

0 to module two, it is blocked by the signal from decoder 10 on element 9 I. The signal at the output of decoder 10 is generated as follows. When a unit appears at the output of element 6, OR NOT (in

5, the moment of fixing the synchronization failure), the counter 7 is reset to zero at the input of the reset. In this case, a zero code is set at the input of the decoder 10, to which the decoder 10 processes zero at the output. This zero signal opens element 8 OR. which passes the clock frequency from the clock input of the device to the counting input of the counter 7. The counter counts until the number n (in binary form) is established at its output. At the same time, at the output of the decoder 10, a unit is established by which the 8-ILI element is closed. After that, the state of the counter 7 and the decoder 10 remain unchanged until the next positive pulse arrives from the output of the 6 OR-NOT element. Thus, when synchronization fails, the output of the decoder 10 produces a negative pulse, the duration of which is sufficient to block the second output of the device while the synchronization failure register 1 passes through.

As counter 7, you can use a binary counter, for example type 155 HE7.

The decoder 10 is a set of logic elements that implements the following dependence: at the output of the decoder 10 there is one if there is a number n at the output of the counter 7, and zero in all other cases.

Majority gates 3 and 4 can be implemented in any way, for example, using adders modulo two.

It should be noted that during operation of the device, the number of units at the inputs of the majority elements, equal to the values from T + 1 to H -1, occurs not only when synchronization fails, but also in a situation where there are more than T errors on the length n. In order to reduce the likelihood of making an incorrect decision in such a case, it is necessary to choose n large enough, while it is possible to assign T large values.

For example, for a binary channel without memory, with the probability of error per Po symbol and threshold T p / 4,

where x is the integer part of x

for different probability P (n) that more than T erroneous characters are shown on the length n will be

p (n) S + CnPo (1 -Ro)

, n - 1

1) p 15, T 3, P (15) 0.125. 2) p 63, T 15, P (63) 0.24-U; 17 Thus, in comparison with the prototype, in the proposed device due to the introduction of a block of adders modulo two, an OR-NOT element, an adder modulo two. of the decoder, the first and second majority elements, it is possible to detect clock synchronization failures. Information about this is generated at the first output of the device. If there is a synchronization failure, due to a violation of the structure of the pseudo-random sequence in the shift register 1, the device will incorrectly generate an error stream during the time that the synchronization failure passes through the register 1. At this time, the second

the device output (error sequence output) is blocked by the sync failure signal. Thus, the overall reliability of error detection is improved. The proposed device for detecting errors of a discrete information transmission channel can be implemented on commercially available series elements 564, 133, 533, 1533.

As an example, we consider the construction and operation of the device for the case of K 3, therefore, item 7. We find the polynomial-generating sequences and the verification system from the literature.

The generating polynomial of the considered pseudo-random sequence will have the following form

(x7-1) / (x4 + x2 + xf + 1) x3 + x + 1 and the verification system

Eo Eo

a0 ai @ a5 a0 a2 © az a

where © is the summation operation modulo two.

In accordance with the generating polynomial, the sequence of characters generated by it is written as follows

... 111X110011101001110 ... D-

n 7

The block diagram of the device will look like

shown in FIG. 2. Number of inputs

majority elements 3 and 4 is equal to 4. We set the thresholds of elements 3 and 4 as follows

way:

T 1, then H 1-T 4-T 3.

In the absence of errors and synchronization failures, the device operates as follows. Suppose that at the initial moment of time in register 1 there is a segment of a pseudo-random sequence marked on its image with a curly bracket. The subsequent states of register 1 arising1 when moving along it a pseudo-random sequence correspond to. This state of the remaining elements of the yt family is given in Table. 1

Assume that a bit containing an error is in the cell ae of register 1. The operation of the device in this case is explained by the states of its elements shown in Table 2.

Consider a situation related to a clock synchronization failure. We will use the notation and initial conditions given in Table. 1. Suppose that the clock synchronization failed due to the loss of the clock pulse number 1. Moreover, the pseudo-random sequence bit corresponding to this pulse is not written to the register. The operation of the device in this case is explained by the states of its elements shown in the table. 3.

Thus, when the clock synchronization fails, information about this appears at the output of the decoder 10 in the form of a negative pulse. The same pulse blocks the passage to the output of the And 9 element of a false pulse from the output of the adder 5 modulo two, which was formed on the seventh clock cycle.

Claims (1)

The claims A device for detecting errors of a discrete information transmission channel containing a shift register, an OR element, an And element, and a pulse counter, characterized in that, in order to increase the reliability of error detection, a block of (p-1) / 2 adders modulo two (where n is the length of the pseudo-random sequence), the first and second majority elements, an OR-NOT element, an adder modulo two and a decoder whose output is connected to the first inputs of the AND element and the OR element and is the first output of the device, first exit reg the shift unit is connected to the first inputs of the first and second majority elements and an adder modulo two, the output of which is connected to the second input of the element And, the output of which is the second output of the device, the information input of the shift register is the information input of the device, the clock input of the shift register is combined with the second input of the OR element and is the clock input of the device, the second outputs of the shift register are connected to the corresponding inputs of the adders modulo two blocks, the outputs of which are connected respectively - to the second inputs of the first and second majority elements, the output of the second majority element is connected to the first input of the OR-NOT element, the output of the first majority element is connected to the second inputs of the adder modulo two and the OR-NOT element, the output of which is connected to the reset input of the pulse counter, the counting input and the outputs of which are connected respectively to the output of the OR element and the inputs of the decoder. Table 4. flit.2