JPH02206228A - Signal transmitter-receiver - Google Patents

Abstract

PURPOSE:To detect the bit error of a normal transmission line with a parity bit by sending the parity bit from a transmission side equipment together with parallel data, applying parity check at a reception side equipment and controlling a latched timing. CONSTITUTION:N-bit parallel data are inputted to the parallel input terminals P1-Pn of the transmission side equipment 101 and also inputted to a parity generating circuit 1. The parity generating circuit 1 identifies an n-bit level and generates the parity bit (data 11). A parallel output in (n+1)-bit from the latch circuit 6 is inputted to a parity check circuit 7, where the parity is checked. A counter 8 counts clocks inputted to a clock terminal C and outputs a pulse at every (n+1)-bit when the signal of parity error is not inputted to a set terminal S and outputs a pulse at every n-bit or (n+2)-bit when no error signal is inputted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal transmitting/receiving device that transmits data of n bits in one time slot, and in particular to a digital line switching device that digitizes analog information such as video and exchanges digital signals. It belongs to the technical field of

[Prior Art] FIG. 7 is a diagram showing an example of the configuration of a conventional signal transmitting/receiving device.

In the transmitting unit @ 101, n-bit data corresponding to one time slot is input to the shift register 3 in parallel. The frame generation circuit 31 generates a preset frame signal using a clock. The frame signal is input to the parallel input terminal Po of the shift register 3. The counter 2 counts the clocks, generates a pulse every n+1 bit period, and outputs it to the select terminal S of the shift register 3. In shift register 3, counter 2
When the output pulse is sent to the select terminal S and the clock rises or falls, n-bit parallel data and 1-bit frame signal 1 are latched. Furthermore, when the output pulse of the counter 2 is not being sent, the latched data is shifted every time the clock rises, rises or falls, and the shifted serial data is sent to the receiving side device 102. do.

In the receiving side device 102, the received serial data is processed by the delay adjustment circuit 4 for a time τ so that the phase matches the receiving side clock.
only to be delayed. The delayed serial data is input to the serial input terminal of the shift register 5. The shift register 5 shifts the input data at each rising or falling edge of the clock, and outputs the shifted (n+1) bit parallel output to the latch circuit 6. The latch circuit 6 latches the (n+1) bits of parallel data input every pulse period sent from the frame detection circuit 32, outputs n bits as parallel data, and sends 1 bit to the frame detection circuit source. . The frame detection circuit source identifies the data sent from the latch circuit 6, detects the frame signal, and sends it to the clock terminal C of the latch circuit 6 every n+1 bits so that it can be output as normal n-bit parallel data. Send out a pulse.

Through the above operations, l) n-bit parallel data can be transmitted and received;

[Problem to be solved by the invention]

The conventional example described above can transmit and receive signals of n bits per time slot, but it is impossible to detect errors in data during transmission. It is necessary to provide bits, which increases the transmission bit rate and has the disadvantage that a separate MB detection circuit is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal transmitting/receiving device having a simple circuit configuration, which can eliminate the conventional drawbacks, and can detect bit errors in a normal transmission path using parity bits, and can also specify a time slot delimiter. shall be.

[Means to solve the problem]

In order to achieve the above object, the signal transmitting and receiving device of the present invention has the following features:
A first invention provides a signal transmitting/receiving device comprising a transmitting device that converts n-bit parallel data into serial data and transmits the same, and a receiving device that converts the serial data transmitted from the transmitting device into parallel data. The transmitting device receives n-bit parallel data, and
A harness generation circuit that identifies the n bits of data and generates parity, and a harness generation circuit that separately counts input clocks and generates parity.
A first counter that generates a pulse every +1 bit cycle, n-bit parallel data, and the output of the logic generation circuit are input to the parallel input terminal, and the output of the first counter is input to the select terminal. The clock is input to the clock terminal, and n is input to the output of the first counter.
It outputs a pulse every +1 bits, and latches the n-bit parallel data and the output data of the parity generation circuit at the rising edge or falling edge of the clock, and outputs a pulse every n+1 bits to the output of the first counter. When a pulse is not output, shift the latched n+1 bit output data every time the clock rises or falls;
a first shift register that uses the shifted n+1-bit output data as output data of the transmitting device, and the receiving device separately inputs the data received from the transmitting device and the receiving device. means for adjusting the phase with the clock of the receiving side device, the received data whose phase is adjusted with the clock of the receiving side device is inputted to the input terminal, the clock inputted to the side is inputted to the clock terminal, and the rising edge of the clock Or a second shift register that outputs falling n+1 bits of data, and the n+1 bits of data output from the second shift register input 1+ to the parallel input terminal, and the pulse that is input to the clock terminal. The n+1 bit data output from the second shift register is latched at the rising edge of n+ or the falling edge of n+
a latch circuit that outputs 1-bit parallel data; a parity check circuit that inputs the n+1-bit parallel data of the latch circuit, performs a parity check, and outputs a parity error signal when a parity error is detected; and the parity error signal. is input to an input terminal, a separately input set signal is input to the set terminal, and when the set signal is in an on state, the set circuit outputs the parity error signal input to the input terminal, and the clock is connected to the clock terminal. The output of the set circuit is input to the set terminal, the clock input to the clock terminal is counted, and when the parity error signal sent from the set circuit does not indicate a parity error, the output of the n+1 bit is input to the set terminal. a second circuit which generates a pulse every period, and when the parity error signal indicates a parity error, generates a pulse every period of n bits or n+2 bits, and outputs the pulse to the clock terminal of the latch circuit; It is characterized by being equipped with a counter.

Further, the second invention provides a method for adjusting the clock from the data received from the transmitting side device as an alternative means for adjusting the phase of the data received from the transmitting side device and the clock of the receiving side device in the receiving side device of the first invention. This invention requires a means to extract the clock and use it as a clock for the receiving side device, and is characterized by obtaining the same effect as the first invention.

That is, in a signal transmitting/receiving apparatus that includes a transmitting device that converts n-bit parallel data into serial data and transmits the serial data, and a receiving device that converts the serial data transmitted from the transmitting device into parallel data, the transmitting device is input with n-bit parallel data, and
A parity generation circuit that identifies bit data and generates parity, and a separate input clock that counts the n+1
a tenth counter that generates a pulse every bit period;
n-bit parallel data and the output of the parity generation circuit are input to the parallel input terminal, the output of the first counter is input to the select terminal, the clock is input to the clock terminal, and the output of the first counter is input to the select terminal. At the output, n+1
It outputs a pulse for each bit, and latches the n-bit parallel data and the output data of the parity generation circuit at the rising or falling edge of the clock, and outputs the output of the first counter K n + 1 bits at a time. When a pulse is not output, the latched n+1 bits of output data are shifted every time a clock rises or falls, and the shifted n+1 bits of output data are set as the output data of the transmitting device. 1 shift register, and the receiving device includes means for extracting a clock from the data received from the transmitting device and using it as a clock for the receiving device, and a means for extracting a clock from the data received from the transmitting device, and a means for inputting the data received from the transmitting device. The clock of the receiving device is input to the clock terminal, and the received data is shifted at the rising or falling edge of the clock, and the n+l bits from the current received data to the n-bit shifted data are a second shift register that outputs data, and n+1 bit data output from the second shift register,
Latch the n+1 bits of data inputted to n+1 parallel input terminals and output from the second shift register at the rising edge or falling edge of the pulse inputted to the clock terminal, and output n+1 bits of parallel data. Input the latch circuit and the n+1 bit parallel data of the latch circuit, perform a parity check, and parity 2
A parity check circuit outputs a parity error signal when - is detected, the parity error signal is inputted to an input terminal, and a separately inputted set signal is inputted to the set terminal.

a set circuit that outputs the parity error signal input to the input terminal when the set signal is on; the clock input to the clock terminal; the output of the set circuit input to the set terminal; n+1 when the parity error signal sent from the set circuit does not indicate a parity error.
generating a pulse every bit period, and when the parity error signal indicates a parity error, generating a pulse every n bit or n+2 bit period;
The device is characterized by comprising a second counter that outputs the pulse to a clock terminal of the latch circuit.

[Effect]

In the present invention, the parity of the old parallel input data is removed at the transmitting side device, and the parity bit is also included.
When transmitting in bits and starting one communication, the receiving device performs a parity check, and each time a parity error is detected, it shifts one bit at a time, and if a parity error always occurs, extract n+1n+1 bits t and b. The data on the sending side can be received normally, and by prohibiting 1-bit shifts due to parity errors during communication, transmission can be performed using normal parity checks!
It becomes possible to detect Ia.

Examples will be described below based on the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. 1. The operation shown in FIG. 1 will be explained using FIG. 2.

The same reference numerals as in FIG. 7 indicate the same parts.

In the sending device 101, n-bit parallel data is input to the parallel input terminals P1 to P1 of the shift register 3, and is also input to the parity generation circuit l. The parity generation circuit 1 identifies the level of n bits and generates a parity bit (data 11). The parity bit is input to one parallel input terminal P0 of the shift register 3.

81! 1 is applicable when 1 time slot is 4 bits (n=4), and is assumed to be an even parity. For example, from time t1
During period t, the number of 1s (H level) in the input data is 3, so the parity bit (data 11) is 1. The clock is input to counter 2, and a pulse (H
level) and outputs the select terminal S of shift register 3.
Send K data ν.

The level of data U and the state of shift register 3 correspond to 1:1), and when the data sphere is at H level, input terminal P0
Latch n+1 bits of parallel input data to ~,
When it is at L level, the latched data is set to be shifted. Both change at the rising edge of the clock input to the clock terminal CK. Time 1. , 1. , 1.1. Since data n is at H level at time n + 1 (
=5) Latch bit parallel data. Since the data ν is at the L level at the other rising edges of the clock, the missed data is shifted bit by bit and sent out as serial data (data 13). The receiving side device receives data 13, delays the received data by time (data 14) in order to match the phase with the receiving side clock in the delay adjustment circuit 4, and inputs it to the input terminal of the shift register 50. Data 14 is shifted in the shift register 5 every time the clock rises.

The parallel output of n+1 (=5) bits is input to the latch circuit 6, and the output pulse of the counter 8 (
It is latched at the rising edge of data 15).

The n+l bit parallel output of the latch circuit 6 is input to the parity check circuit 7, which performs a parity check.
The parity check result is sent to the set circuit 9. In the set circuit 9, if the set terminal SK set signal is sent, the parity check result inputted to the input terminal is directly sent to the set terminal S of the counter 8 as an output (data 16). If the set terminal SK set signal is not sent, output of the parity check result is prohibited. Counter 8 counts the clock input to clock terminal C, and if no parity error signal is input to set terminal S, outputs a pulse every n+1 bits,
If a parity error signal is input to the set terminal S, a pulse is output every n bits or every n+2 bits.

In FIG. 2, 5-bit data input to the latch circuit 6 is latched at time t2, and a parity check circuit 7 performs a parity check on the latched 5-bit data. At time t8, the number of 1's is 3, which is not an even number, so the parity error signal becomes H level. FIG. 2 shows a case where a set signal is being sent, and the parity error signal is sent to the set terminal of the counter 8 as it is through the set circuit 9. In FIG. 2, the counter 8 has an output pulse period of 6 when the parity error signal is at H level.
Data 15 is set for each bit, and a pulse should normally be output at time t6, which is 5 bits later, but a pulse is output at time t7, which is 6 bits later. As a result of the parity check of the data latched at time t, the number of 1's becomes 4, and the sheverity error signal (data 16) goes to L level. Therefore, from this point on, the period of the output pulse of the counter 8 is 5 bits, and parallel transmission data can be normally received as parallel reception data. Even if the output pulse of data 15 is not at the regular time, a parity error may not occur depending on the data arrangement, but after a certain amount of time, the output pulse of data 15 will be set at the regular time, so there is no problem. . When parity errors no longer occur, transmission of the set signal is stopped, and changes in the latch time period due to parity errors are prohibited. By doing this, it is possible to detect code errors on the transmission path by parity checking during normal times.

FIG. 3 shows an embodiment of the set circuit 9, which can be easily configured by performing a logical product of the parity error signal input to the input terminal 1 and the set signal t input to the set terminal S (AND game) 21. .

4 and 5 show respective embodiments of the counter 8 to which a conventional ring counter K AND gate 22 or 24 is added. FIG. 4 shows n+2 evolution when a set signal is input. If an L level is input to the set terminal S, it functions as an n+1 counter, and each time a clock is input to the clock terminal C, an H level is input to the clock terminal C.
・Flip 70 tube DFFI to DFF (n+1)
When DFF(n+1) becomes H level, all the outputs from DFFI to DFFn go to L level, and as a result, all the inputs of the NOR gate become L level, so the NOR gate phantom output When the DFF becomes H level, the DFF IKH level is latched at the next clock. In this way, a pulse can be output from the output terminal Q every n+1 periods. If the set terminal SKH level is input, the output of the NOR game (NOR game) 23 will not go to the H level unless the D flip-flop DFF (n+i) also goes to the L level, and will be delayed by one clock, so it will function as an n+ binary counter, and the output terminal A pulse can be output every n+2 periods from Q.

In FIG. 5, n evolution is performed when a set signal is input. If L level is input to set terminal S, DF
The output of Fn is input to the NOR gate 5, and the set terminal S
If an H level is input to , the output of DFFn becomes NOR.
Since they are not input to the gate 6, they function as an n+1-ary counter and an n-ary counter by the same operation as shown in FIG. 4, and pulses are outputted from the output terminal Q every n+1 bit and every n bit, respectively.

In the embodiment shown in FIG. 1, the received data is delayed by the delay adjustment circuit 4 to match the phase with the received clock, but the clock side may also be delayed and adjusted, or the clock may be extracted from the received data and the receiving clock The same operation is possible even when used as a clock.

The operation of one circuit in FIG. 6 is easily understood from the above description of the embodiment in FIG. 1, so a detailed explanation will be omitted.
The structure of another embodiment of the present invention is shown in which a clock is extracted from data received from a transmitting side device and used as a receiving side clock. The same numbers as in Figure 1 indicate the same parts, 10
is the clock extraction circuit.

〔Effect of the invention〕

As explained above, the first and second inventions transmit parity bits together with parallel data from the transmitting device, perform a parity check on the receiving device, and check the parity bit by one bit each time a parity error is detected. By shifting the latch timing and recognizing the point where no parity error occurs as the time slot delimiter, from then on, even if a parity error occurs, the latch timing is not shifted, thereby creating a parity pit. This advantage is particularly noticeable when the signal transmitting/receiving apparatus of the present invention is applied to the technical field of digital space division line switching equipment that digitizes analog information such as video and exchanges digital signals.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an embodiment of the present invention, Fig. 2 is a rounded timing chart explaining Fig. 1, Fig. 3 is an embodiment of the set circuit in Fig. 1, and Figs. 4 and 5. FIG. 6 is a block diagram of another embodiment of the present invention, and FIG. 7 is a configuration example of a conventional transmitting/receiving device. 101... Sending side device 102... Receiving side device 1... Parity generation circuit 2.8... Counter 3.5... Shift register 4... Delay adjustment circuit 6... Latch circuit 7 ... Parity check circuit 9 ... Set circuit 10 ... Clock extraction circuit 31 ... Frame generation circuit Proverbs ... Frame detection circuit 21 , 22 , 24 ... AND circuit illusion, 25 ...
NOR circuit DFFI ~DFF(n+1)-D7 lip 70 tube 5
...NOT circuit 11.12, 13, 14, 15, 16...Data t1 to t7 ...Time Patent applicant Nippon Telegraph and Telephone Corporation agent Patent attorney Hisabu Tamamushi (1 other person)

Claims (2)

[Claims] (1) In a signal transmitting/receiving device comprising a transmitting device that converts n-bit parallel data into serial data and transmits the same, and a receiving device that converts the serial data transmitted from the transmitting device into parallel data, the transmitting device comprises: The side device receives n-bit parallel data, has a parity generation circuit that identifies the n-bit data and generates parity, and separately counts the input clock and generates a pulse every n+1 bit period. A first counter, n-bit parallel data, and the output of the parity generation circuit are input to the parallel input terminal, the output of the first counter is input to the select terminal, the clock is input to the clock terminal, and the A pulse of every (n+1) bits is outputted to the output of the first counter, and the n-bit parallel data and the output data of the parity generation circuit are latched at the rising or falling edge of the clock. When the pulse of every n+1 bit is not output to the output of the n+1 bit, the latched n+1
Shift the output data of bits, and the shifted n+1
a first shift register that uses bit output data as output data of the transmitting device, and the receiving device is configured to combine the data received from the transmitting device and a clock separately input to the receiving device. The received data whose phase is matched with the clock of the receiving device is inputted to an input terminal, the separately inputted clock is inputted to the clock terminal, and when the clock rises or falls, the received data Shift the received data and calculate n from the current received data to the data shifted by n bits.
A second shift register that outputs +1-bit data, and n+1-bit data output from the second shift register are input to n+1 parallel input terminals, and the rising edge or rising edge of the pulse input to the clock terminal is input to the n+1 parallel input terminals. A latch circuit that latches the n+1 bits of data output from the second shift register at the time of downlink and outputs the n+1 bits of parallel data; and a latch circuit that inputs the n+1 bits of parallel data of the latch circuit and performs a parity check. A parity check circuit outputs a parity error signal when an error is detected, the parity error signal is input to an input terminal, a separately input set signal is input to the set terminal, and when the set signal is in an on state, the parity check circuit is input to the input terminal. a set circuit that outputs the parity error signal that has been input, the clock is input to a clock terminal, the output of the set circuit is input to the set terminal, the clocks input to the clock terminal are counted, and the clocks are sent out from the set circuit. When the parity error signal detected does not indicate a parity error, a pulse is generated every n+1 bit period, and
and a second counter that generates a pulse every n bit or n+2 bit period when the parity error signal indicates a parity error, and outputs the pulse to the clock terminal of the latch circuit. A signal transmitting/receiving device characterized by: (2) In a signal transmitting/receiving device comprising a transmitting device that converts n-bit parallel data into serial data and transmits the same, and a receiving device that converts the serial data transmitted from the transmitting device into parallel data, the transmitting device comprises: The side device receives n-bit parallel data, has a parity generation circuit that identifies the n-bit data and generates parity, and separately counts the input clock and generates a pulse every n+1 bit period. A first counter, n-bit parallel data, and the output of the parity generation circuit are input to the parallel input terminal, the output of the first counter is input to the select terminal, the clock is input to the clock terminal, and the A pulse of every (n+1) bits is output to the output of the first counter, and the n-bit parallel data and the output data of the parity generation circuit are latched at the rising or falling edge of the clock. When a pulse of every n+1 bit is not outputted, the latched n+1 is output every time the clock rises or falls.
Shift the output data of bits, and the shifted n+1
a first shift register that uses bit output data as output data of the transmitting device, and the receiving device extracts a clock from the data received from the transmitting device and uses the clock of the receiving device. means for inputting data received from the transmitting device to an input terminal, and inputting a clock of the receiving device to a clock terminal;
a second shift register that shifts the received data at the rising or falling edge of a clock and outputs n+1 bits of data from the current received data to the n-bit shifted data; and from the second shift register. The n+1-bit data to be output is input to n+1 parallel input terminals, and the n+1-bit data output from the second shift register is latched at the rising or falling edge of the pulse input to the clock terminal. a latch circuit that outputs parallel data; a parity check circuit that inputs the n+1 bit parallel data of the latch circuit, performs a parity check, and outputs a parity error signal when a parity error is detected; and an input terminal for the parity error signal. A set circuit that inputs a separately input set signal to the set terminal and outputs the parity error signal input to the input terminal when the set signal is on. The output of the circuit is input to the set terminal, the clock input to the clock terminal is counted, and when the parity error signal sent from the set circuit does not indicate a parity error, a pulse is generated every n+1 bit period. Also, when the parity error signal indicates a parity error, n bits or n+
A signal transmitting/receiving device comprising: a second counter that generates a pulse every two bits and outputs the pulse to a clock terminal of the latch circuit.