JPS581387A - Sampling clock regenerating circuit - Google Patents

Abstract

PURPOSE:To obtain a sampling clock regenerating circuit which regenerates a clock signal synchronizing with a clock line signal, by outputting a gate signal on the basis of the clock line signal, and starting oscillating operation by the signal. CONSTITUTION:A gated oscillating circuit 95 opens an NAND gate 951 by a gate signal synchronizing with slice data to output the slice data, i.e. a pulse signal which synchronizes with a clock line signal. This pulse signal is supplied to a frequency divider 92 through inverters 954 and 955. A gate signal generating circuit 96, on the other hand, generates a gate signal on the basis of the slice data to start the oscillating operation of the gated oscillating circuit 95 by said gate signal. Therefore, a certain phase relation between the clock line signal and an oscillation output is born to eliminate the jitters between the data and a sampling clock.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sampling clock regeneration circuit, and more particularly, to a sampling clock regeneration circuit for regenerating a sampling clock for sampling data based on a clock run-in signal transmitted within a vertical synchronization period in television teletext broadcasting. This invention relates to a sampling clock regeneration circuit.

Text multiplex broadcasting is known as a digital transmission system for television receivers. As is well known, this teletext broadcasting system inserts digital signals representing data such as characters and graphics into an appropriate IH (H-horizontal scanning period) within the vertical blanking period of the FCF revision broadcasting signal. It is something that is transmitted.

FIG. 1 is an illustrative diagram showing an example of a television text multiplex signal. FIG. 1 shows the IH portion of the 20th H within the vertical blanking period in which character signals (data) are inserted in a television character multiplexing system. That is,
During this 20th period, a clock length in signal (CRI) starting from the color burst signal (CC) located in the pack porch of the horizontal synchronization signal (H8) at a certain time #lJ1 and consisting of repetitions of "1" and rOJ; The 8-bit framing code ffl't (FIC) following this CRI signal
Then, a data signal (DA) that continues from the next bit of this FiLC signal to the end of IH is inserted.

As mentioned above, the CILI signal is configured as a 16 or 18 bit signal consisting of repetitions of "1" and rOJ, and the data signal (
This serves as a time reference for creating sampling pulses for sampling DA). Further, the FILC signal is 1
This is an 8-bit code signal selected to provide a bit error line protection function, and serves as a time reference when the sampled data signal is parallel-converted 8 bits at a time. Since there are many possible code configurations for this FliLC signal, it is only necessary to adopt the one that is obvious. For example, N
)11100101 is adopted in the C55 method of 1,
Also, in the UK Teletext system, 11100100 is
In addition, in the French Ante-Aup system, 111001
11 have been adopted.

FIG. 182 is a schematic block diagram of a conventional text-multiple electric signal receiver. In the figure, a tuner or video detection circuit 2 is for reproducing video signals and television text multiplex signals. The video signal is applied to a cathode ray tube 5 via a video circuit 3 and a mixing circuit 4.

On the other hand, the television text multiplex signal is applied to a multiplex period sampling circuit 6. The multiplex period sampling circuit 6 is constituted by a gate circuit for character signal extraction, which extracts IH to several H minutes into which the character multiplex signal is inserted from the detection output of the video detection circuit.

The extracted character signal is applied to a data slicer circuit 7, where it is sliced 2 degrees at the 1 level of its amplitude and converted into a rectangular wave. This character signal converted into a rectangular wave is given to a serial/parallel conversion circuit 8 and a clock recovery circuit 9. The black body reproducing circuit 9 obtains a CRI signal from the character multiplex signal shown in FIG. 1 and reproduces a sampling clock. 'This sampling clock is given to the serial/parallel converter circuit 8. The serial/parallel conversion circuit 8 samples and extracts the data signal from the output signal of the data slicer circuit 7 using a sampling pulse.

The sequentially extracted data signals are converted into parallel signals 8 bits at a time by timing pulses and are applied to the main memory 11. Further, the clock reproduced by the clock reproduction circuit 9 is given to the address control circuit 10. The address control circuit IO specifies the address of the main memory 11 by incrementing the clock pulse.

Therefore, the main memory 11 stores the data output from the serial/parallel conversion circuit 8 at a predetermined address designated by the address control circuit 10. The data stored in the main memory 11 is subjected to predetermined processing in a signal processing circuit 12 and then provided to the mixing circuit 4. The mixing circuit 4 mixes the character signal with the normal video signal and displays it on the cathode ray tube 5. In addition, RUM13 and microprocessor 14
is provided to control the main memory 11.

Although the conventional character multiplex signal receiver is constructed as described above, the present invention relates to the clock recovery circuit 9.

FIG. 3 is a concrete block diagram of the clock recovery circuit 9 shown in FIG. gJ2, and FIG. 4 is a waveform diagram of each part in FIG.

Next, the specific configuration and operation of the conventional clock recovery circuit 9 will be explained with reference to FIGS. 3 and 4.

The oscillation circuit 91 operates as shown in FIG. 4 (C) based on the vibration of the crystal resonator.
7IJ- oscillates the clock signal shown in ).

This clock signal is provided to a percent divider 92. on the other hand,
The reset pulse generation circuit 93 is connected to the data slicer circuit 7
The reset pulse shown in FIG. 4(b) is generated based on the slice data (FIG. 4(a)) output from the J84.

The clock signal is divided by i (
Figure 4(d)). This frequency-divided signal is delayed by the ΔT period by the ΔT delay circuit 94 (FIG. s4 (e)). The reason why the branch output signal is delayed by the ΔT period in this manner is to ensure that the trailing edge timing of the branch output signal is approximately at the center of the data, and sampling is performed at approximately the center of the data.

It should be noted that the numbers in parentheses in FIG. 3 indicate a specific example of the N1-11-C system in the case of sentence ¥ hoin (bit rate = 5.73 MHz).

As mentioned above, in the conventional clock regeneration circuit 9, the oscillation circuit 9 is allowed to freely oscillate, and the i frequency divider 92 is reset at the falling (or rising) edge of the clock run-in signal to regenerate the sampling clock. ing. Therefore, the slice data and the output signal of the first oscillation path 91 are not synchronized. That is, the oscillation circuit 91 adjusts the timing of the reset pulse output based on the slice data.
Derive the clock signal regardless. Therefore, since the reset pulse is output sometime between the rising edge of the oscillation output and the next rising edge, the phase becomes unstable. That is, as shown in gJ4 diagram (bl, (C), 4
It fluctuates by 1 time. This variation causes jitter between the data and the recovered sampling clock.

This situation is shown in FIG.

As shown in FIG. 115, the variation in the sampling point due to the sampling clock with respect to the data eye pattern is as much as 100, which means that data identification becomes that much more difficult. Note that T in FIG. 5 is the data pulse width, which is, for example, l 75 m5ec in the case of the NHK-C system. Furthermore, in the conventional clock regeneration circuit 9, the oscillation circuit 91 operates not only during the character multiplexing period but also during the period when a normal broadcast program is displayed, and is a source of unnecessary radiation. Furthermore, no correction is made for sampling point deviations due to low frequency group delay distortion of the character signal transmission path.

Therefore, the main object of the present invention is to provide a sampling clock regeneration circuit that regenerates a clock signal synchronized with the clock run-in signal in a device that regenerates the clock signal using the clock run-in signal.

According to this invention, a gate signal is output based on the clock run-in signal, the oscillation operation of the oscillation means is started based on this gate signal, and the oscillation signal output from the oscillation means is divided to generate data. It is configured to output a sampling signal for sampling. .

The above-mentioned objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 6 is a schematic block diagram of an embodiment of the present invention.

This FIG. 6 is the same as the above-mentioned FIG. 3 except for the following points. That is, a gated oscillation circuit 95 is provided in place of the oscillation path 91 shown in FIG. 3, and a gate signal generation circuit 96 for providing a gate signal to the gated oscillation circuit 95 is provided. This gate signal generation circuit 96 is configured to generate a gate signal based on slice data, and further enhance the oscillation operation of the gated oscillation circuit 95 based on this gate signal.

FIG. 7 is a more detailed block diagram of the clock recovery circuit shown in FIG. 6. In the configuration, the gated oscillation circuit 9
5 is NAND gates 951 and 952 and crystal oscillator 953
This is a well-known oscillation circuit including inverters 954 and 955. The gated oscillation circuit 95 opens the NAND gate 951 with a gate signal synchronized with the slice data, thereby outputting a pulse signal synchronized with the slice data, that is, the clock run-in signal. This pulse signal is passed through inverters 954 and 955 to i frequency divider 9.
given to 2.

On the other hand, the gate signal generation circuit 96 connects the inverter 961 and J
K flip-flop 962.

Multiple horizontal line pulses are input to the clear input terminal of this JK flip-flop. Furthermore, slice data whose polarity has been inverted by an inverter 961 is input to the clock input terminal. Q of this JK flip-flop
The output signal is sent to the NAND gate 951 as a gate signal.
Divide the frequency with one input end! 1931 enable input terminal.

The branching unit 931 constitutes a reset pulse generation circuit 93 together with a JK flip-flop 932 and a NOR gate 933. Slice data is directly input to the clock input terminal of the divider 931, and the JK flip-flop 932
Slice data whose polarity has been inverted by an inverter 961 is input to the clock input terminal of the inverter 961 . The Q output signal of JK flip-flop 932 is applied to NOR gate 933. Mamata, i minute 7m! ! ! 92 QC signal is NOR gate 93
given to 3. The output signal of N0iL gate 933 is i
It is applied to the reset input terminal of frequency divider 192.

FIG. 8 is a waveform diagram of each part of the cabinet 7.

Next, the specific operation of one embodiment of the present invention will be explained with reference to FIGS. 6 to 8. Multiple horizontal line pulses are extracted from the multiple period extraction circuit 6 shown in FIG.
Flip-flop 962 and frequency division! 1931 and J4 flip 70 tube 932, respectively. This multi-voltage horizontal line pulse 1 becomes H level only within the vertical synchronization period. Therefore, this clock regeneration circuit 9 operates only during the vertical retrace period, and is in a reset state at other times. Multiplex horizontal line pulse 1 rises to H level and slice data b is output to inverter 96
When the JK clip-flop 962 is inverted by 1 and the JK clip-flop 962 is set, an H-level gate signal C is applied from the 9 output terminal of the %J4 flip-flop 962 to the NAND gate 951. In response, gated oscillation circuit 95 starts oscillating operation.

On the other hand, the frequency divider 931 and the JK flip-flop 932
are cleared in the initial state, so J
The Q output signal f of the K flip-flop 932 is at H level and is applied to this H level. therefore,
When the 6 frequency divider 931, which also clears the 1 frequency divider 92, counts the third pulse of the slice data b, it supplies the division signal C to the JK flip-flop 932 from its QB output terminal.

JK flip-flop 932 is set when branch signal C becomes H level and slice data b inverted by inverter 961 falls to L level. That is,
The q output signal of the JK flip-flop 932 becomes L level. Thereby.

The clear input terminal of the 1 frequency divider 92 becomes H level.

Then, the i frequency divider 92 starts counting the oscillation output signal d of the gated oscillation circuit 95 inputted via the inverters 954 and 955. Then, the frequency-divided signal derived from the QB output terminal is delayed by a ΔT period by a ΔT delay circuit 94 and output as a sampling pulse.

Note that the 1 frequency divider 92 is cleared by this signal when the Qc multiplied signal reaches H level, and frequency division by 1 is repeated, and sampling is achieved at approximately the center of the slice data b by the output signal i of the ΔT delay circuit 94. be done.

As mentioned above, in this embodiment, the oscillation circuit starts the oscillation operation at the first rising edge of the clock run-in signal, so a certain phase relationship is established between the clock run-in signal and the oscillation output. Notes shown in Figure 9i68
It is possible to eliminate fluctuations in Therefore, jitter between the data and the sampling clock can be eliminated, and the relationship between the eye pattern and the sampling points shown in FIG. 5 can be fixed. Thereby, data can be easily identified and identification errors can be reduced. Furthermore, since the operation of the clock regeneration circuit 9 is stopped except during the vertical synchronization period, that is, the multi-voltage period, it is possible to prevent negative effects caused by unnecessary radiation.

Furthermore, with respect to the low-band group delay distortion of the transmission path, the first rise of the clock run-in signal acts in a direction to correct the phase shift of the sampling point due to the group delay distortion. Therefore, in the case of this embodiment, Δ[
increases or decreases in the direction of correcting the low-frequency group delay distortion, and as a result, the reproduced sampling clock works in the direction of correcting the phase shift.

Note that the present invention is not limited to teletext broadcasting, but can be applied to any device that reproduces a clock axis using a clock run-in signal.

As described above, according to the present invention, since the oscillation operation is started at the first rise of the clock run-in signal, a sampling clock synchronized with the clock run-in signal can be obtained.

[Brief explanation of the drawing]

! Figure 1!1 is an illustrative diagram showing an example of a television text multiplex signal. FIG. 2 is a schematic block diagram of a conventional Mojitaden No. 48 receiver. FIG. 11N3 is a detailed block diagram of the clock recovery circuit included in FIG. FIG. 4 is a waveform diagram of each part of the Vs3 diagram. FIG. 5 is an illustrative diagram showing the relationship between an eye pattern and a sampling point, which is neglected in a conventional teletext receiver. FIG. 6 is a schematic block diagram of an embodiment of the present invention. FIG. 7 is a detailed block diagram as well. Figure 8 is j17! ? It is a waveform diagram of each part of Q. In the figure, 2 is a tuner or video detection circuit, 6 is a multi-voltage period extraction circuit, 7 is a data slicer circuit, 9 is a clock regeneration circuit, 92 is a 1 frequency divider, 93 is a reset pulse generation circuit, 94 is a 417414 circuit, Reference numeral 95 indicates a gated oscillation circuit, and reference numeral 96 indicates a gate signal generation circuit.

Claims (1)

[Scope of Claim] A sampling clock regeneration circuit that regenerates a clock signal using a clock run-in signal that determines data sampling timing. 1 gate means for outputting a gate signal based on the lock run-in signal; oscillation means for starting an oscillation operation based on the gate signal output from the gate means and continuing oscillation only within the gate period; A frequency dividing means is provided for dividing the frequency of the oscillation signal output from the oscillating means and outputting a sampling signal for sampling the data. Sampling clock regeneration circuit.