JPH02192319A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To shorten a time until synchronization is established without depending on the timing of an input signal in a synchronizing operation at an early stage by providing a reset circuit to reset a frequency divider by a reset signal based on the input signal. CONSTITUTION:The input signal (a) inputted from a signal input terminal 1 and an internal signal (b) in which the output signal of a voltage controlled oscillator 4 is 1/N-frequency divided by a frequency divider 6 are inputted to a phase comparator 2, and phase difference between them is detected, and a phase difference voltage is outputted. Next, a DC voltage which controls the oscillation frequency of the voltage controlled oscillator 4 can be obtained from the above output voltage via an LPF 3, and the oscillation frequency of the oscillator 4 is controlled, and the signal (a) and a signal in which the synchronization is established and with the frequency of N times are outputted to an output terminal 5. In a series of operations stated above, the reset circuit 7 operated only in the synchronizing operation at the early stage is provided, and the reset signal (c) setting the signal (a) as reference is generated, thereby, the frequency divider 6 can be reset. In such a way, it is possible to set the phase relation of the signal (a) with the signal (b) appropriately in the synchronizing operation at the early stage, and to shorten the time until the synchronization can be established.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase-locked loop circuit that quickly synchronizes an internal signal with an input signal during initial operation.

(Prior art) Fig. 4 is a block connection diagram showing a conventional phase-locked loop circuit (hereinafter referred to as PLL circuit) shown in, for example, How to use rPLL-IC (co-authored by Hata and Yoshikawa), Akiba Publishing, page 169. In the figure, 1 is a signal input terminal, 2 is a phase comparator that compares the phase of the human input signal and the internal signal, 3 is a low-pass filter, 4 is a voltage controlled oscillator, 5 is a signal output terminal, and 6 is a voltage controlled oscillator. 4 output frequency to 1
This is a frequency divider that divides the frequency by /N.

Next, the operation will be explained. The input signal input from the signal input terminal 1 and the internal signal obtained by dividing the output signal of the voltage controlled oscillator 4 by 1/N by the frequency divider 6 are input to the phase comparator 2, and the phase difference between these is input to the phase comparator 2. is detected and outputs a phase difference voltage corresponding to the phase lead or lag. Furthermore, by filtering this output voltage with the low-pass filter 3, a DC voltage that controls the oscillation frequency of the voltage-controlled oscillator 4 is obtained.

When the phase of the internal signal lags behind the phase of the input signal, the level of the output voltage of the low-pass filter 3 that filters the phase difference voltage of the phase comparator 2 increases, and the oscillation frequency of the voltage-controlled oscillator 4 increases. do. Therefore, the phase difference between the input signal and the internal signal becomes small. On the other hand, when the phase of the internal signal leads the phase of the input signal, the level of the output voltage of the low-pass filter 3 decreases, the oscillation frequency of the voltage controlled oscillator 4 decreases, and the phase of the input signal and internal signal decreases. By repeating one or more operations in which the phase difference becomes smaller, a signal of N times the frequency that is synchronized with the input signal is output from the signal output terminal 5.

[Problem to be solved by the invention]

Since the conventional PLL circuit is configured as described above,
The phase relationship between the input signal and internal signal is uncertain during the initial synchronization operation, so if the initial phase relationship conditions are poor, it may take a long time to achieve synchronization (pull-in time). was there.

This invention was made to solve the above-mentioned problems.In the initial synchronization operation, the time until synchronization is achieved (pull-in time), regardless of the timing of the input signal.
An object of the present invention is to obtain a PLL circuit that can shorten the time.

[Means to solve the problem]

In the PLL circuit according to the present invention, in an initial synchronous operation, a reset signal is generated based on an input signal by a reset circuit, and the frequency divider is reset by this reset signal.

(Operation) The reset circuit according to the present invention sets the phase relationship between the input signal and the internal signal appropriately by resetting the frequency divider in the initial synchronization operation, thereby shortening the time until synchronization is achieved.

(Embodiment of the Invention) Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, 1 is a signal input terminal, 2 is a phase comparator, 3 is a low-pass filter, 4 is a voltage controlled oscillator, 5 is a signal output terminal, and 6 is a frequency divider, and these are circuits that constitute a conventional PLL circuit. It is exactly the same as the means. 7 is a reset circuit that resets the frequency divider 6 using a reset signal based on an input signal.

Next, the operation will be explained. The input signal input from the signal input terminal 1 and the internal signal obtained by dividing the output signal of the voltage controlled oscillator 4 by 17N in the divider 6 are input to the phase comparator 2, and the phase difference between them is detected here. , outputs a phase difference voltage.

Furthermore, by filtering this output voltage with the low-pass filter 3, a DC voltage that controls the oscillation frequency of the voltage-controlled oscillator 4 is obtained. The oscillation frequency of the voltage controlled oscillator 4 is controlled by this output voltage, and a signal with a frequency N times higher than the input signal is outputted to the output signal terminal 5. In this series of operations, the reset circuit 7 operates only in the initial synchronous operation. This initial synchronous operation will be explained with reference to the signal waveform diagram of each part of the circuit shown in FIG. First, the input signal a and the internal signal S have an arbitrary phase relationship in the initial synchronization process. Therefore, the reset circuit 7 generates a reset signal C based on the input signal a, and resets the frequency divider 6. Through this operation, the phase relationship between the input signal a and the internal signal A in the initial synchronization operation is properly set.

In the above embodiment, the reset signal C was generated based on the input signal a, but the input signal a is generated by dividing the clock signal by another frequency divider 8 as a reset circuit, as shown in FIG. In the case that the signal is obtained from the input signal a, the reset signal C is simultaneously applied to the frequency divider 6 and the frequency divider 8 in the initial synchronization operation to appropriately set the phase relationship between the input signal a and the internal signal A. be able to.

〔Effect of the invention〕

As described above, according to the present invention, the reset circuit that forcibly draws the internal signal into synchronization with the input signal is connected to the frequency divider, so that in the initial synchronization operation, the human input signal and the internal signal This has the effect of shortening the time it takes to achieve initial synchronization (pull-in time).

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a PLL circuit according to an embodiment of the present invention, and FIG. 2 is a block connection diagram showing a PLL circuit according to an embodiment of the present invention.
FIG. 3 is a block connection diagram showing another embodiment of the PLL circuit of the present invention, and FIG. 4 is a block connection diagram showing a conventional PLL circuit. 2 is a phase comparator, 3 is a low-pass filter, 4 is a voltage controlled oscillator, 6 is a frequency divider, and 7 is a reset circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 2 Sugoittoi No. 9 C

Claims (1)

[Claims] A phase comparator detects the phase difference between the input signal and the internal signal obtained by dividing the output of the voltage controlled oscillator with a frequency divider, and filters the phase difference voltage output by this phase comparator, and filters the filtered output. In the phase-locked loop circuit, the frequency divider is configured to forcibly pull the internal signal into synchronization with the input signal during initial operation. A phase-locked loop circuit characterized by having a reset circuit for controlling.