JPH09252250A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a phase locked loop circuit in which no phase jump is caused for an output phase synchronizing signal in the case of switching a reference signal for phase locking and no out of frame synchronism is caused in an opposite device. SOLUTION: When a reference signal switching circuit selects a new reference signal from a reference input terminal 1a, phase locking control is stopped by a free run control signal 5 to cause free running. Thus, tri-state buffers 13a, 13b of a charge pump 6 reach a high impedance state, then an output level of the charge pump 6 is given by resistors 14a, 14b and a voltage controlled oscillator 9 outputs a frequency in the vicinity of the frequency substantially to be synchronized. In this case, since no phase lock control is conducted strictly, a phase of an output phase locking signal is slowly changed and the phase locking control is restarted when the phase of the output phase synchronizing signal is closer to the phase of the new reference signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit for generating a signal synchronized with a reference signal.

[0002]

2. Description of the Related Art FIG. 10 is a configuration diagram of a plurality of reference signal inputs, a switching circuit therefor, and a conventional phase locked loop circuit which outputs a phase-locked signal to the reference wires. In FIG. 10, 1 is a reference signal input terminal, 2 is a switching control signal input terminal for controlling the reference signal switching circuit, 3 is a reference signal switching circuit, 4 is a phase frequency comparator, 6 is a charge pump, 7 is a low pass filter, Reference numeral 8 is an amplifier, 9 is a voltage controlled oscillator, 10 is an output terminal for a phase synchronization signal, and 11 is a frequency divider.

Next, the operation of the conventional phase locked loop circuit shown in FIG. 10 will be described. The reference signal switching circuit 3 selects one of the plurality of reference signals input from the reference signal input terminal 1 based on the switching control signal input to the reference signal control terminal 2, and the selected reference signal is It is input to the phase frequency comparator 4. The phase frequency comparator 4 is
The phase of the reference signal selected by the reference signal switching circuit 3 is compared with the signal phase from the frequency divider 11, and the phase difference is output to the charge pump 6. The charge pump 6 outputs a voltage signal proportional to the phase difference from the phase frequency comparator 4. This voltage signal is smoothed by the low pass filter 7, amplified by the amplifier 8, and then input to the voltage controlled oscillator 9. The voltage controlled oscillator 9 outputs the oscillation frequency according to the input voltage value to the output terminal 10.

Here, when another reference signal is selected by the control signal of the switching control signal input terminal 2, a new reference signal is input to the phase frequency comparator 4, so that the phase locked loop circuit receives the new reference signal. Output terminal 1 for phase-synchronized signals
The output is controlled to 0.

[0005]

Since the conventional phase locked loop circuit is constructed as described above, when the reference signal is changed, the signal phase input to the phase frequency comparator 4 changes instantaneously. When the control of the phase synchronization circuit suddenly operates and a phase jump occurs in the phase synchronization signal output from the output terminal 10, and the output of this phase synchronization signal is transmitted as it is,
There is a problem that frame phase synchronization is lost in the opposite side transmission device.

The present invention has been made to solve such a problem, and an object thereof is to obtain a phase locked loop circuit which does not cause phase jump of the phase locked signal even when the reference signal is changed.

[0007]

To achieve the above object, a phase locked loop circuit according to a first aspect of the present invention comprises a reference signal switching circuit for switching a plurality of reference signals having substantially the same frequency but different phases. A phase frequency comparator that compares the phases of the reference signal and the generated synchronization signal in order to obtain a signal synchronized with the reference signal selected by the reference signal switching circuit, and input by inputting the output from the phase frequency comparator A charge pump that outputs a voltage according to a value, a low-pass filter and an amplifier that smoothes and amplifies the output from the charge pump, and a voltage-controlled oscillator that outputs a signal synchronized with the output voltage from the amplifier as a control voltage. , A frequency divider circuit for dividing the output from the voltage controlled oscillator and inputting it to the phase frequency comparator, and for switching the reference signal. And a phase control restarting means for restarting the control of the phase synchronizing circuit when the phase of the output synchronizing signal is gradually changed by stopping the control of the phase synchronizing circuit and gradually changing the phase of the output synchronizing signal. Is.

Further, in the phase locked loop circuit according to the second aspect of the invention, the phase change circuit includes a free run circuit for free running the phase locked loop circuit.

Further, in the phase locked loop circuit according to the third aspect of the invention, the phase changing means includes control voltage changing means for changing the control voltage of the voltage controlled oscillator.

In the phase locked loop circuit according to the fourth aspect of the present invention, the control voltage changing means changes the offset voltage of the amplifier.

In the phase locked loop circuit according to the fifth aspect of the present invention, the control voltage changing means changes the operating point of the charge pump.

In the phase locked loop circuit according to the sixth aspect of the present invention, the control voltage changing means changes the frequency division ratio of the frequency divider.

Further, the phase locked loop circuit according to the seventh aspect of the present invention, in the case of gently changing the phase of the output sync signal,
The control means is provided so as to control the output synchronizing signal to change in the direction close to the phase of the new reference signal.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention. 2 is a circuit configuration diagram of the charge pump 6 in FIG. In FIG. 1, reference numeral 1 is a reference signal input terminal, 2 is a switching control signal input terminal for controlling a reference signal switching circuit, 3 is a reference signal switching circuit, 4 is a phase frequency comparator, and 5 is no control for matching with a reference. Free run control terminal, 6 is a charge pump, 7 is a low pass filter, 8 is an amplifier, 9 is a voltage controlled oscillator, 10 is an output terminal of a phase synchronization signal, and 11 is a frequency divider. In FIG. 2, 6 is a charge pump, 1
Reference numeral 2 is an AND circuit, 13 is a 3-state buffer, 14 is a resistor, and 15 is an output terminal of the charge pump 6.

Next, the operation of the phase locked loop circuit shown in FIG. 1 will be described with reference to FIG. In FIG. 1, it is assumed that the reference signal switching circuit 3 first selects the reference signal from the reference signal input terminal 1a, and a signal phase-locked with this is output to the phase-synchronization signal output terminal 10.
Next, a case where the reference signal switching circuit 3 selects the reference signal from the reference signal input terminal 1b based on the switching control signal input to the switching control signal input terminal 2 will be described.

When the reference signal switching circuit 3 selects a new reference signal based on the signal input to the switching control signal input terminal 2, the free-run control terminal 5 is used before the reference signal switching circuit 3 executes the switching. From logic "L"
By inputting this signal, the outputs of the AND circuits 12a and 12b of the charge pump 6 become "L", and the three-state buffers 13a and 13b become high impedance. In this case, the output potential of the charge pump 6 is given by the resistors 14a and 14b, and the voltage controlled oscillator 9 outputs a frequency near the frequency to be originally synchronized.

From the free run control terminal 5, the logic "
The reason why the voltage controlled oscillator 9 outputs a frequency in the vicinity of the frequency to be synchronized by inputting the signal of L ″ will be described. The phase frequency comparator (PFC) 4 outputs the voltage controlled oscillator (VCO) 9 Frequency divider 11
And a reference signal are input, and a voltage corresponding to the phase difference is output. The phase frequency comparator 4 has two outputs, one of which outputs the phase difference when the output of the voltage controlled oscillator (VCO) 9 leads the phase of the reference signal, and the other of which has a phase delay. In that case, the phase difference is output. Also,
If there is no phase difference between the output of the voltage controlled oscillator (VCO) and the reference signal, there will be no two outputs of the phase frequency comparator 4. In this case, the two inputs of the charge pump 6 are "L"
Therefore, the output of the 3-state buffer becomes high impedance. In this case, there is no phase difference between the output of the voltage controlled oscillator (VCO) and the reference signal as described above. That is, the phase of the output of the voltage controlled oscillator (VCO) and the phase of the reference signal are almost equal. When the free-run control terminal 5 is set to "L", the output of the 3-state buffer is forcibly set to high impedance, which is the same state as this. The above is the explanation of the reason.

In this case, since the phase synchronization control is not performed strictly, the phase synchronization signal output from the output terminal 10 of the voltage controlled oscillator 9 gradually starts changing its phase. The phase frequency comparator 4 monitors the phase of the new reference signal and the phase synchronizing signal changing in phase, and returns the control signal input from the free-run control terminal 5 to logic “H” when the phases of both approaches. By switching the reference signal switching circuit 3 to the new reference signal, it is possible to restart the phase synchronization control, perform the phase synchronization with the new reference signal, and gently perform the phase synchronization with the new reference signal.

According to this embodiment, there is an effect that a sudden phase jump does not occur, and the frame phase synchronization is not lost in the opposite device even if the phase synchronization signal is transmitted. .

Embodiment 2 FIG. 3 is a block diagram showing another embodiment of the phase locked loop circuit according to the present invention. Also,
FIG. 4 is a circuit configuration diagram of the amplifier 8 in FIG. FIG.
1, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions. 1
Reference numeral 6 is an offset voltage control terminal. Further, in FIG. 4, 8 is an amplifier, 16 is an offset voltage control terminal, 17
Is an input terminal of the amplifier 8, 18, 19, 20, 21, 2
Reference numerals 2 and 23 are resistors, 24 is an electronic switch, 25 is an operational amplifier, and 26 is an output terminal of the amplifier 8.

Next, the operation of the phase locked loop circuit shown in FIG. 3 will be described with reference to FIG. In FIG. 3, it is assumed that the reference signal switching circuit 3 first selects the reference signal from the reference signal input terminal 1a, and a signal phase-locked with this is output to the phase-synchronization signal output terminal 10. Next, a case where the reference signal switching circuit 3 selects the reference signal from the reference signal input terminal 1b based on the switching control signal input to the switching control signal input terminal 2 will be described.

When the reference signal switching circuit 3 selects a new reference signal based on the signal input to the switching control signal input terminal 2, the offset voltage control terminal 16 is used before the reference signal switching circuit 3 executes this switching. By inputting a control signal to close the electronic switch 24, an offset voltage different from that at the time of phase synchronization is applied to the non-inverting input of the operational amplifier 25, so that the output terminal 26 of the amplifier 8 is not at the time of phase synchronization. Output different voltages. Since the voltage control oscillator 9 operates by the control voltage of the output terminal 26, the phase synchronization signal output from the phase synchronization output terminal 10 gradually changes its phase. The phase frequency comparator 4 monitors the phase of the new reference signal and the phase synchronizing signal that changes in phase, and when the phases of both approaches, the electronic switch 24 is opened by the control signal to the offset voltage control terminal 16 to open the reference signal. By the switching circuit 3 switching to the new reference signal, the phase synchronization with the new reference signal can be performed, and the phase synchronization with the new reference signal can be performed gently.

According to the embodiment of the present invention, a sudden phase jump does not occur, and even if transmission is performed with the output of this phase synchronization signal, the opposite side device does not lose the frame phase synchronization. Play.

Embodiment 3. FIG. 5 is a configuration diagram showing another embodiment of the phase locked loop circuit according to the present invention. Also,
FIG. 6 is a circuit configuration diagram of the charge pump 6 in FIG. 5, the same symbols as those in FIG. 1 indicate the same or corresponding portions. 27 is an operating point voltage control terminal. Further, in FIG. 6, the same reference numerals as those in FIG. 2 indicate the same or corresponding portions. 27
Is an operating point voltage control terminal, 29 is a resistor, 30 is an electronic switch, and 31 is an output terminal of the charge pump 6.

Next, the operation of the phase locked loop circuit shown in FIG. 5 will be described with reference to FIG. In FIG. 5, it is assumed that the reference signal switching circuit 3 first selects the reference signal from the reference signal input terminal 1a, and a signal phase-locked with this is output to the phase-synchronization signal output terminal 10.
Next, a case where the reference signal switching circuit 3 selects the reference signal from the reference signal input terminal 1b based on the switching control signal input to the switching control signal input terminal 2 will be described.

When the reference signal switching circuit 3 selects a new reference signal based on the signal input to the switching control signal input terminal 2, the operating point voltage control terminal is selected before the reference signal switching circuit 3 executes this switching. By inputting a control signal to 27 to close the electronic switch 30, an operating point voltage different from that at the time of phase synchronization is given as the operating point voltage at the time of high impedance of the three-state buffer 13 in the case of phase synchronization. Therefore, a voltage different from that at the time of phase synchronization is output to the output terminal 31 of the charge pump 6. The output voltage of the output terminal 31 operates the low-pass filter 7, the amplifier 8, and the voltage control oscillator 9, so that the phase synchronization signal output from the phase synchronization output terminal 10 gradually changes its phase. Phase frequency comparator 4
The phase of the phase synchronization signal that changes in phase with the new reference signal is monitored at, and when the phases of both approaches, the electronic switch 30 is opened with the control signal to the operating point voltage control terminal 27, and the reference signal switching circuit 3 is used. By switching to the new reference signal, the phase synchronization with the new reference signal can be performed, and the phase synchronization with the new reference signal can be performed gently.

According to the embodiment of the present invention, a sudden phase jump does not occur, and even if transmission is performed by outputting this phase synchronization signal, the opposite side device does not lose the frame phase synchronization. Play.

Fourth Embodiment FIG. 7 is a block diagram showing another embodiment of the phase locked loop circuit according to the present invention. 7, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. 32
Is a frequency division ratio control terminal.

Next, the operation of the phase locked loop circuit shown in FIG. 7 will be described. In FIG. 7, it is assumed that the reference signal switching circuit 3 first selects the reference signal from the reference signal input terminal 1a, and a signal phase-locked with this is output to the phase-synchronization signal output terminal 10. Next, the reference signal switching circuit 3 receives the reference signal input terminal 1 based on the switching control signal input to the switching control signal input terminal 2.
The case of selecting the reference signal from b will be described.

When the reference signal switching circuit 3 selects a new reference signal based on the signal input to the switching control signal input terminal 2, before the reference signal switching circuit 3 executes this switching, the division ratio control terminal Divider 11 to 32
Since the phase of the phase synchronization signal input from the frequency divider 11 to the phase frequency comparator 4 is changed by inputting the control signal so as to change the frequency division ratio, the phase frequency comparator 4 outputs the phase difference signal. To be done. Due to this phase difference signal, a voltage different from that at the time of phase synchronization is output to the output of the charge pump 6, and this voltage operates the low pass filter 7, the amplifier 8 and the voltage control oscillator 9, so that the output from the phase synchronization output terminal 10 is performed. The phase synchronization signal is gradually changed in phase. The phase frequency comparator 4 monitors the phase of the new reference signal and the phase synchronizing signal that changes in phase, and when the phases of both approaches, the control signal to the frequency division ratio control terminal 32 determines the frequency division ratio based on the frequency division ratio. By returning and switching to the new reference signal by the reference signal switching circuit 3, it is possible to perform phase synchronization with the new reference signal and gently perform phase synchronization with the new reference signal.

According to the embodiment of the present invention, there is no abrupt phase jump, and the frame phase synchronization is not lost in the opposite device even if the phase synchronization signal is transmitted. Play.

Embodiment 5 FIG. 8 is a block diagram showing another embodiment of the phase locked loop circuit according to the present invention. Also,
FIG. 9 is a circuit configuration diagram of the amplifier 8 in FIG. FIG.
1, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions. 1
6a and 16b are offset voltage control terminals. Also,
In FIG. 9, 8 is an amplifier, 16a and 16b are offset voltage control terminals, 17 is an input terminal of the amplifier 8, 18, 1
Reference numerals 9, 20, 21, 22, 23 are resistors, 24 is an electronic switch, 25 is an operational amplifier, and 26 is an output terminal of the amplifier 8.

Next, the operation of the phase locked loop circuit shown in FIG. 8 will be described with reference to FIG. In FIG. 8, it is assumed that the reference signal switching circuit 3 first selects the reference signal from the reference signal input terminal 1a, and a signal phase-synchronized with the reference signal is output to the phase-synchronization signal output terminal 10. Next, a case where the reference signal switching circuit 3 selects the reference signal from the reference signal input terminal 1b based on the switching control signal input to the switching control signal input terminal 2 will be described.

When the reference signal switching circuit 3 selects a new reference signal based on the signal input to the switching control signal input terminal 2, the phase of the reference signal so far is compared with the phase of the new reference signal. , Determines whether the phase of the output phase synchronization signal should be advanced or delayed, and inputs a control signal to the offset voltage control terminal 16 to close the electronic switch 24a or the electronic switch 24b before the reference signal switching circuit 3 executes the switching. To do.

When the electronic switch 24a is controlled to be closed in order to delay the phase of the output synchronizing signal, the non-inverting input of the operational amplifier 25 has an offset voltage different from that at the time of phase synchronization, here, the resistor 22a and the resistor 22a. Since 23 is connected in parallel, a lower voltage is applied than before closing the electronic switch 24a. Therefore, a voltage lower than that at the time of phase synchronization is output to the output terminal 26 of the amplifier 8.
Since the voltage control oscillator 9 is operated by this control voltage, the phase synchronization signal output from the phase synchronization output terminal 10 gradually delays the phase. The phase frequency comparator 4 monitors the phase of the new reference signal and the phase synchronizing signal that changes in phase, and when the phases of both approaches, the electronic switch 24 sends a control signal to the offset voltage control terminal 16.
By opening a and switching to a new reference signal by the reference signal switching circuit 3, it is possible to perform phase synchronization with respect to the new reference signal and gently perform phase synchronization with respect to the phase with respect to the new reference signal.

On the contrary, when the electronic switch 24b is controlled to be closed in order to advance the phase of the output synchronizing signal, the non-inverting input of the operational amplifier 25 has an offset voltage different from that at the time of phase synchronization, here, the resistor 22b and the resistor. Since 20 are connected in parallel, a higher voltage is applied than before closing the electronic switch 24b. Therefore, the output terminal 26 of the amplifier 8
A voltage higher than that at the time of phase synchronization is output to the output terminal 26, and the voltage control oscillator 9 is operated by this control voltage. Therefore, the phase synchronization signal output from the phase synchronization output terminal 10 advances the phase gently. To go. Phase frequency comparator 4
The phase of the phase synchronization signal that changes in phase with the new reference signal is monitored at, and when the two phases approach each other, the electronic switch 24b is opened with the control signal to the offset voltage control terminal 16, and the reference signal switching circuit 3 uses the new signal. By switching to the reference signal, the phase synchronization with the new reference signal can be performed, and the phase synchronization with the new reference signal can be performed gently in the direction of advancing the phase.

According to the embodiment of the present invention, a sudden phase jump does not occur, and even if the phase synchronization signal is transmitted at the output, the opposite side device does not lose the frame phase synchronization. Play.

[0038]

According to the first aspect of the present invention, when the reference signal is switched, the phase synchronization control is stopped and the phase of the phase synchronization signal output from the output terminal 10 is gradually changed to a new reference signal phase. When it approaches, the phase synchronization control is restarted so that the phase is synchronized without causing a phase jump. There is an effect that the frame phase synchronization is not lost in the side device.

Further, according to the second aspect of the invention, since the phase changing means is provided with the free-run means for free-running the phase synchronizing circuit, abrupt phase jump does not occur and the phase synchronizing signal is output. Even if the data is transmitted, there is an effect that the frame phase synchronization is not lost in the opposite device.

Further, according to the third aspect of the invention, since the phase changing means is provided with the control voltage changing means for changing the control voltage of the voltage controlled oscillator, abrupt phase jump does not occur and this phase synchronization signal Even if the output is transmitted, there is an effect that the frame phase synchronization is not lost in the opposite device.

Further, according to the fourth aspect of the invention, since the control voltage changing means changes the offset voltage of the amplifier, abrupt phase jump does not occur, and even if the phase synchronization signal is transmitted, There is an effect that the frame phase synchronization is not lost in the opposite device.

According to the fifth aspect of the invention, since the control voltage changing means changes the operating point of the charge pump, abrupt phase skipping does not occur, and even if the phase synchronizing signal is transmitted, it is transmitted. The effect is that the frame phase synchronization is not lost in the opposite device.

According to the sixth aspect of the invention, since the control voltage changing means changes the frequency division ratio of the frequency divider, a sudden phase jump does not occur and the phase synchronization signal is transmitted at the output. Even in this case, it is possible to obtain the effect that the frame phase synchronization is not lost in the opposite device.

According to the seventh aspect of the invention, when the phase of the output synchronizing signal is gently changed, the control means is provided so as to control the output synchronizing signal to change in the direction close to the phase of the new reference signal. Therefore, there is no abrupt phase jump, and there is an effect that the frame phase synchronization is not lost in the opposite device even if the phase synchronization signal is transmitted.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is a circuit configuration diagram of a charge pump 6 in FIG.

FIG. 3 is a configuration diagram showing another embodiment of the phase locked loop circuit according to the present invention.

4 is a circuit configuration diagram of an amplifier 8 in FIG.

FIG. 5 is a configuration diagram showing another embodiment of the phase locked loop circuit according to the present invention.

6 is a circuit configuration diagram of a charge pump 6 in FIG.

FIG. 7 is a configuration diagram showing another embodiment of the phase locked loop circuit according to the present invention.

FIG. 8 is a configuration diagram showing another embodiment of the phase locked loop circuit according to the present invention.

9 is a circuit configuration diagram of an amplifier 8 in FIG.

FIG. 10 is a configuration diagram of a conventional phase locked loop circuit.

[Explanation of symbols]

1 Reference signal input terminal 2 Switching control signal input terminal for controlling the reference signal switching circuit 3 Reference signal switching circuit 4 Phase frequency comparator 5 Free run control terminal 6 Charge pump 7 Low pass filter 8 Amplifier 9 Voltage control oscillator 10 Phase synchronization signal Output terminal 11 frequency divider 12 AND circuit 13 3 state buffer 14 resistance 15 charge pump output terminal 16 offset voltage control terminal 17 amplifier input terminal 18 resistance 19 resistance 20 resistance 21 resistance 22 resistance 23 resistance 24 electronic switch 25 operation Amplifier 26 Amplifier output terminal 27 Operating point voltage control terminal 28 Charge pump input terminal 29 Resistor 30 Electronic switch 31 Charge pump output terminal 32 Dividing ratio control terminal

Claims (7)

[Claims] 1. A reference signal switching circuit for switching a plurality of reference signals having substantially the same frequency and different phases, and a reference signal for generating a signal synchronized with the reference signal selected by the reference signal switching circuit. A phase frequency comparator that compares the phases of the synchronization signals, a charge pump that inputs the output from the phase frequency comparator and outputs a voltage according to the input value, and the output from the charge pump is smoothed and amplified. A low-pass filter and an amplifier, a voltage-controlled oscillator that outputs a signal that is synchronized with the output voltage from the amplifier as a control voltage, and a frequency divider circuit that divides the output from the voltage-controlled oscillator and inputs it to a phase frequency comparator. , Phase change that gradually changes the phase of the output synchronization signal by stopping the control of the phase synchronization circuit when switching the reference signal And a phase control resuming means for resuming control of the phase synchronizing circuit when the phase of a new reference signal is approached. 2. The phase synchronizing circuit according to claim 1, wherein the phase changing means includes a free running means for free running the phase synchronizing circuit. 3. The phase locked loop circuit according to claim 1, wherein the phase changing means comprises control voltage changing means for changing the control voltage of the voltage controlled oscillator. 4. The phase locked loop circuit according to claim 3, wherein the control voltage changing means changes the offset voltage of the amplifier. 5. The phase locked loop circuit according to claim 3, wherein the control voltage changing means changes the operating point of the charge pump. 6. The phase locked loop circuit according to claim 3, wherein the control voltage changing means changes the frequency division ratio of the frequency divider. 7. The control means for controlling the output synchronizing signal to change in a direction close to the phase of the new reference signal when the phase of the output synchronizing signal is gently changed. The phase synchronization circuit described.