JP2862078B2 - PLL - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL, and more particularly to a PLL for extracting a clock signal from an NRZ signal.

[0002]

2. Description of the Related Art In the field of optical communication and the like, N
RZ (Non Return to Zero) signals are often used. This is because the NRZ signal is different from the RZ (Return to Zero) signal and the required bandwidth is only about 2/3 of the bit rate.
This is because there is a feature that the load on the high-speed electric circuit is small.

However, the NRZ signal does not have a clock signal spectral component. Therefore, in order to extract the clock signal from the NRZ signal, it is necessary to perform a non-linear operation. To extract the clock signal,
A method of combining a nonlinear circuit and a filter, and a PLL
(Phase Locked Loop: phase-locked loop). The method using the PLL is smaller than the method using a combination of a nonlinear circuit and a filter. However, the phase comparison between the NRZ signal and the clock signal requires RZ
Since a mixer used in a PLL for a signal or the like cannot be used, another phase comparison method must be adopted.

FIG. 4 shows a conventional PLL for an NRZ signal.
Such a PLL is described, for example, in the document ISSCC93, T
This is shown in FIGS. 1 and 2 of P10.4.

The PLL shown in FIG. 4 includes two DF / Fs (D-flip-flops) 41, 4 connected to an input terminal 40.
2, loop filter 43, amplifier 44, VCO
(Voltage Controlled Oscilater) 45. Here, two DF / Fs 41 and 42 constitute a phase comparator.

In this PLL, an input signal (NRZ signal) input to an input terminal 40 is split into two, and a DF / F
41 and 42 are supplied to clock input terminals (C terminals). Also, the data input terminals (D-F / F 41, 42) (D
(Terminal) is supplied with a clock signal from the VCO 45.

The DF / F 41 identifies a clock signal when the input signal rises, and outputs a signal indicating the phase relationship between the input signal and the clock signal. That is, DF
/ F41 outputs "1" to the positive logic output terminal (Q terminal) when the phase of the clock signal is advanced with respect to the input signal, and conversely, the phase of the clock signal is delayed with respect to the input signal. Output, "0" is output to the positive logic output terminal. The DF / F 42 identifies a clock signal when the input signal falls, and outputs a signal indicating the phase relationship between the input signal and the clock signal. DF / F41
Outputs "0" to the negative logic output terminal (QB terminal) when the phase of the clock signal is advanced with respect to the input signal, and conversely, the phase of the clock signal is delayed with respect to the input signal. At this time, "1" is output to the positive logic output terminal.

The loop filter 43 includes a DF / F 41,
The harmonic component of the output signal at 42 is cut off. The amplifier 44 amplifies the output of the loop filter 43 and
5 is controlled.

As described above, a PLL that can establish phase synchronization with an input NRZ signal is realized.

Note that Japanese Patent Application Laid-Open No. Hei 4-221188 discloses
JP-A-4-207632 and JP-A-62-18
No. 3216, etc., there is a P using two DF / Fs.
Although LL is disclosed, none of them corresponds to the NRZ signal.

[0011]

In the conventional PLL, each circuit is configured by using a bipolar transistor. However, when such a phase comparison circuit is realized by CMOS, low power consumption is a problem. Become.

In a circuit using CMOS, the lower the operating frequency, the smaller the amount of current (average current) flowing through the circuit, and low power consumption becomes possible. When the output destination of the clock signal from the PLL is a DMUX circuit or the like, the VCO
The frequency of the clock output from the input signal may be の of the clock frequency (bit rate) of the input signal.
Therefore, if the frequency of the clock output from the VCO can be reduced to の of the bit rate of the input signal and the operating frequency of the phase comparator can be reduced to の of the conventional frequency, the PLL
Low power consumption should be realized.

However, in the conventional PLL, the VCO
Clock signal is 1/1 of the bit rate of the input signal.
In the case of 2, there is a problem that the phase comparison between the input signal and the clock signal cannot be performed, that is, it does not operate as a PLL.

An object of the present invention is to provide a PLL capable of extracting a clock signal having a frequency half the bit rate of an input NRZ signal, thereby providing a PLL capable of low power consumption. And

[0015]

According to the present invention, there is provided a VCO for generating a clock signal having a frequency corresponding to an input voltage;
A PL having a phase comparator for performing a phase comparison between an input signal and the clock signal, and a loop filter for filtering an output of the phase comparator and supplying the output to the VCO as the input voltage.
L, the VCO generates the clock signal and generates an auxiliary clock signal having a phase difference of 90 ° from the clock signal, and the phase comparator compares the phase of the input signal with the clock signal. And performing a phase comparison between the input signal and the auxiliary clock signal, and combining these phase comparison results, when the clock signal has a clock frequency of ビ ッ ト the bit rate of the input signal, A signal representing the advance or delay of the phase of the clock signal with respect to the input signal can be supplied to the loop filter.
LL is obtained.

Further, according to the present invention, the phase comparator includes two clock signals, the clock signal and the auxiliary clock signal being input to a data input terminal, and the input signal being both input to a clock input terminal. A PLL is obtained, comprising: a D flip-flop; and a gate circuit for generating a signal indicating the advance or delay of the phase from the outputs of the two D flip-flops.

The gate circuit passes / outputs one positive logic output and one negative logic output of one of the two D flip-flops based on the positive logic output and the negative logic output of the other D flip-flop. A pair of CMOS switches for blocking and an exclusive OR gate for outputting an exclusive OR of a positive logic output or a negative logic output of one D flip-flop and a positive logic output or a non-logic output of the other D flip-flop. Can be used.

[0018]

The VCOs can generate clock signals having a frequency which is 1/2 of the bit rate of the input signal.
Clock signals (0 ° and 90 °) with a phase difference of
Occurs. The two clock signals are different D-
The data is input to the data input terminal of the F / F. An input signal is input to the clock input terminal of each DF / F, and the clock signal is identified at the rising timing of the input signal. Since the two clock signals input to the data input terminals of each DF / F have a phase difference of 90 ° from each other, if the outputs of these DF / Fs are combined by a CMOS switch or the like, 1 / bit of signal bit rate
As a result, a signal representing the phase lead / lag of the input signal of the clock signal of frequency 2 is obtained. This signal is used to control the VCO via a filter, and the clock signal generated by the VCO is phase-synchronized with the input signal.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
The PLL of FIG. 1 includes two DF / Fs 2 and 3 whose clock input terminals (C terminals) are connected to a signal input terminal 1;
A phase comparison circuit 6 having OS switches 4 and 5; a filter 7; and a VCO 8 capable of outputting a clock signal having a frequency half the clock rate of the input signal and generating clock signals having a phase difference of 90 ° from each other. doing.

Here, the data input terminal (D terminal) of the DF / F2 receives a clock signal having a phase of 0 ° (synchronized with the clock signal supplied to the output terminal 9). It is connected to VCO8. Also, DF
The data input terminal of / F3 is connected to the VCO 8 so that a clock signal having a phase of 90 ° (90 ° phase ahead of the clock signal supplied to the output terminal 9) is input. The positive logic output terminal (Q terminal) of the DF / F 2 is connected to the input terminal of the CMOS switch 4, and the negative logic output terminal (QB terminal) is connected to the input terminal of the CMOS switch 5. Furthermore, the positive logic output terminal of the DF / F3 is connected to the positive logic control terminal of the CMOS switch 4 and the CM.
The negative logic output terminal is connected to the negative logic control terminal of the OS switch 5 and the negative logic control terminal of the CMOS switch 4 is connected to the CM.
It is connected to the positive logic control terminal of the OS switch 5. The output terminals of the CMOS switches 4 and 5 are both connected to the input terminal of the filter 7, and the output terminal of the filter 7 is connected to the control terminal of the VCO 8 to constitute a PLL.

Next, the operation of the PLL of FIG. 1 will be described with reference to FIG. First, a method of comparing the phase of a clock having a frequency half the bit rate of the input signal (NRZ signal) with the phase of the input signal will be described.

Since the phases of the two clock signals generated by the VCO 8 have a phase difference of 90 ° from each other, FIG.
The relationship is as shown in FIG. Here, one cycle of the 0 ° clock signal is divided into four, and each area is defined as α, β, γ, and δ. One bit of the input signal corresponds to a half cycle of the clock signal. Therefore, when the rising edge is in the region of α or γ, the phase of the clock signal is ahead of the phase of the input signal. When the rising edge of the input signal exists in the region of β and δ, the phase of the clock signal is delayed from the phase of the input signal.

Now, when the rising edge of the input signal exists in the area α, the 0 ° clock signal is in the state of “1”. Also, when the rising edge of the input signal exists in the region β, the 0 ° clock signal is in the state of “1”. Therefore, it is not possible to determine in which region the rising of the input signal exists from the state of the 0 ° clock signal alone. That is, it cannot be determined whether the phase of the clock signal is ahead of or behind the phase of the input signal. Similarly, the rising edge of the input signal corresponds to the area γ of the clock signal,
When it is present at δ, it cannot be determined whether the phase of the clock signal is ahead of or behind the phase of the input signal.

However, looking at the 90 ° clock signal, the rising edge of the input signal is “1” when the rising edge of the input signal exists in the area α, and is “0” when the rising edge of the input signal exists in the area β. The 90 ° clock signal is “0” when the rising edge of the input signal exists in the region γ, and is “1” when the rising edge of the input signal exists in the region δ. Therefore, by looking at the states of both the 0 ° clock signal and the 90 ° clock signal, it is possible to determine in which region the rising of the input signal exists. That is, it is possible to determine whether the phase of the clock signal is ahead of or behind the phase of the input signal. In the PLL of FIG. 1, such determination is realized by two DF / Fs 2, 3.

The DF / Fs 2 and 3 respectively have a 0 ° clock signal and a 90 ° clock at the rising timing of the input signal.
° Sample the clock signal. When the phase of the 0 ° clock signal is advanced with respect to the input signal, for example, it becomes as shown in FIG. That is, at sampling points A and B, DF / F2 outputs "0" to the positive logic output terminal, and DF / F3 also outputs "0" to the positive logic output terminal. This is because the rise of the input signal
This corresponds to the case where it exists in the region γ in FIG. Also,
At sampling point C, DF / F2 outputs "1" to the positive logic output terminal, and DF / F3 also outputs "1" to the positive logic output terminal. This corresponds to the case where the rise of the input signal exists in the area α in FIG.

When both the DF / Fs 2 and 3 output "1" to the positive logic output terminal and output "0" to the negative logic output terminal, a CMOS is output based on the output of the DF / F3. The switch 4 turns on, and the CMOS switch 5 turns off. The input terminal of the CMOS switch 4 has a DF / F2
Since "1" is given from the positive logic output terminal of "1", its output becomes "1". When both the DF / Fs 2 and 3 output "0" to the positive logic output terminal and output "1" to the negative logic output terminal, the CMOS switch based on the output of the DF / F 3 4 turns off and the CMOS switch 5
Turns on. Since "1" is given to the input terminal of the CMOS switch 5 from the negative logic output terminal of the DF / F2, the output is "1". That is, FIG.
As shown in (b), when the phase of the 0 ° clock signal is advanced with respect to the input signal, the loop filter includes:
“1” is input.

Conversely, when the phase of the 0 ° clock signal lags behind the input signal, for example, the waveform becomes as shown in FIG. That is, at sampling points A 'and B', DF / F2 outputs "1" to the positive logic output terminal, and DF / F3 outputs "0" to the positive logic output terminal. This corresponds to the case where the rise of the input signal exists in the region β in FIG. At the sampling point C ', the DF / F2 outputs "0" to the positive logic output terminal, and the DF / F3 outputs "0" to the positive logic output terminal. This is because the rise of the input signal
This corresponds to the case where it exists in the region δ in FIG.

DF / F2 is "1" at the positive logic output terminal.
When the DF / F3 outputs “0” to the positive logic output terminal, the CMO is output based on the output of the DF / F3.
The S switch 4 turns off and the CMOS switch 5 turns on. At this time, the input terminal of the CMOS switch 5
Since "0" is given from the negative logic output terminal of -F / F2, the output is "0". Also, DF / F2
Outputs “0” to the positive logic output terminal, and the DF / F3
Outputs “1” to the positive logic output terminal, the DF /
The CMOS switch 4 is turned on based on the output of F3,
The CMOS switch 5 turns off. At this time, since “0” is given to the input terminal of the CMOS switch 4 from the positive logic output terminal of the DF / F2, the output is “0”.
Becomes As described above, when the phase of the 0 ° clock signal is delayed with respect to the input signal, “0” is input to the loop filter as shown in FIG.

As described above, in the PLL of FIG. 1, in the phase comparison circuit 6, comparison between an input signal and a clock signal having a frequency half the bit rate of the input signal can be realized.

The comparison result in the phase comparison circuit 6 is output to the filter 7 and, after removing harmonics, is supplied to the VCO.

A 2.4 Gb / s PLL for optical communication having this embodiment was prototyped. The prototype PLL generated a 1.2 GHz clock signal in synchronization with the input NRZ signal. In addition, the power consumption was almost half of the conventional power.

Next, a second embodiment of the present invention will be described with reference to FIG. In this PLL, the CM shown in FIG.
An exclusive OR gate (EX-OR) 10 is provided instead of the OS switches 4 and 5.

The EX-OR 10 has an input terminal D-OR.
The positive logic output terminal of F / F2 and the negative logic output terminal of DF / F3 are connected, and both DF / F2 and 3 output "0" or "1" to the positive logic output terminal. Output “0”. When DF / F2 outputs "0" to the positive logic output terminal and DF / F3 outputs "1" to the positive logic output terminal, and when DF / F2 outputs positive logic. It outputs "1" to the output terminal and outputs "1" when the DF / F3 outputs "0" to the positive logic output terminal. Thereby, the same operation as that of the PLL of FIG. 1 can be realized.

In this embodiment, by using an exclusive OR gate, other circuits can also be constituted by bipolar transistors. Of course, in this embodiment, the CMO
As in the case of using S, the power consumption cannot be significantly reduced, but the power supply voltage can be reduced with a decrease in the operation speed, which has the effect of reducing power consumption.

[0036]

According to the present invention, an output clock signal;
Since the phase of each of the output clock signal and the signal having a phase difference of 90 ° is compared with that of the input signal, the frequency of the output clock signal is 1/1 / the bit rate of the input signal.
Even with 2, the phase comparison between the output clock signal and the input signal can be performed. Thus, the operation speed of each circuit can be reduced, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIGS. 2A and 2B are waveform diagrams for explaining the operation of the PLL of FIG. 1. FIG. 2A shows the phase relationship between a 0 ° clock signal and a 90 ° clock signal, and the phase relationship between these signals and an input signal. FIG. 4B is a diagram for explaining, FIG. 4B is an output waveform diagram of each part when the phase of the output clock signal is ahead of the phase of the input signal, and FIG. FIG. 7 is an output waveform diagram of each unit when the signal is also delayed.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional PLL.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal input terminal 2, 3 DF / F 4, 5 CMOS switch 6 Phase comparison circuit 7 Filter 8 VCO 9 Output terminal 10 Exclusive OR gate (EX-OR) 40 Input terminal 41, 42 DF / F (D-flip-flop) 43 Loop filter 44 Amplifier 45 VCO (Voltage Controlled Oscilater)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/033

Claims (4)

(57) [Claims] 1. A VCO for generating a clock signal having a frequency corresponding to an input voltage, a phase comparator for comparing a phase between an input signal and the clock signal, and a filter for filtering an output of the phase comparator to output the VCO to the VCO. In a PLL having a loop filter that supplies the input voltage, the VCO generates the clock signal, and generates an auxiliary clock signal having a phase difference of 90 ° from the clock signal. Performing a phase comparison between the input signal and the clock signal, and a phase comparison between the input signal and the auxiliary clock signal, and combining these phase comparison results, the clock signal can be used to determine the bit rate of the input signal. When the clock signal has a clock frequency of １ ／, a signal representing the advance or delay of the phase of the clock signal with respect to the input signal is transmitted to the loop. PLL, characterized in that to be able to supply to the loop filter. 2. The phase comparator according to claim 2, wherein the clock signal and the auxiliary clock signal are respectively input to a data input terminal, and the two input signals are both input to a clock input terminal. 2. The PLL according to claim 1, further comprising a gate circuit configured to generate a signal indicating the phase lead / lag from the outputs of the two D flip-flops. 3. The gate circuit passes a positive logic output and a negative logic output of one of the two D flip-flops based on a positive logic output and a negative logic output of the other D flip-flop. 3. The PLL according to claim 2, comprising a pair of CMOS switches for blocking / blocking. 4. An exclusive OR circuit for outputting an exclusive OR of a positive logical output or a negative logical output of one D flip-flop and a positive logical output or a non-logical output of the other D flip-flop. 3. The PLL according to claim 2, wherein the PLL is a gate.