JP2745060B2 - PLL frequency synthesizer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a PLL-type frequency synthesizer.

[Conventional technology]

In a conventional PLL frequency synthesizer including a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider, when there is a phase difference between the reference frequency and the comparison frequency input to the phase comparator, the phase of both frequencies is determined. In order to shorten the time required to reach the phase constrained state by coincidence, so-called lock-up time, and to accurately maintain the phase constrained state, the time constant of the loop filter is initially reduced and immediately before the phase constrained state is reached. The time constant was being increased.

[Problems to be solved by the invention]

However, there is a problem that the lock-up time cannot be sufficiently reduced only by reducing the time constant of the loop filter as described above.

[Means for solving the problem]

The present invention has been made in view of the above problems,
In the PLL frequency synthesizer according to the present invention, a reference frequency divider that divides a reference frequency by a division ratio greater than 1, and one of an input signal and an output signal of the reference frequency divider is selectively output. A reference frequency divider comprising: a reference frequency switching device for performing a comparison; a comparison frequency divider for dividing the comparison frequency by a division ratio greater than 1; and one of an input signal and an output signal of the comparison frequency divider A comparison frequency divider comprising a comparison frequency switcher for selecting and outputting a signal; a phase comparator for detecting a phase difference between an output of the reference frequency switcher and an output of the comparison frequency switcher; A loop filter that outputs an analog voltage signal corresponding to the phase difference detected by the comparator; an oscillator that oscillates a frequency based on the analog voltage signal; A frequency divider that divides the oscillation frequency of the oscillation frequency by a desired frequency division ratio, and outputs the frequency to the comparison frequency divider as a comparison frequency. Set the desired division ratio, then
Controlling the reference frequency switch to selectively output the input signal of the reference frequency divider, and controlling the comparison frequency switch to selectively output the input signal of the comparison frequency divider; After a lapse of time, the reference frequency switch is controlled to selectively output the output signal of the reference frequency divider, and the comparison frequency switch is selected to selectively output the output signal of the comparison frequency divider. And a frequency control means for controlling the frequency division.

[Action]

In the PLL frequency synthesizer according to the present invention, when the frequency oscillated by the oscillator is changed to a desired frequency, the frequency division control means changes the frequency division ratio in the frequency divider to a frequency division ratio corresponding to the desired frequency. After setting, the reference frequency switch is controlled so as to select and output the input signal of the reference frequency divider, and the comparison frequency switch is controlled so as to select and output the input signal of the comparison frequency divider. In the phase comparator, the frequencies which are not divided are compared with each other, the frequency oscillated by the oscillator changes quickly, and this PLL circuit quickly shifts to the phase locked state.

After a lapse of a predetermined time, the reference frequency switch is controlled so as to selectively output the output signal of the reference frequency divider, and the comparison is performed such that the output signal of the comparison frequency divider is selectively output. Since the frequency switch is controlled, the phase comparator compares the divided frequencies and follows a slight phase difference, and the PLL circuit maintains the phase locked state with high accuracy.

〔Example〕

Hereinafter, an embodiment of a frequency synthesizer according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the PLL frequency synthesizer of the embodiment.

In the drawing, 1 is a phase comparator, 2 is a loop filter, 3 is a voltage controlled oscillator, 4 is a frequency divider, 5 is a reference frequency divider, 6 is a comparison frequency divider, 7 is a reference frequency switch, 8 Is a comparison frequency switch, 9 is a delay circuit, and 10 is a frequency data setter.

Here, the reference frequency divider 5 and the reference frequency switch 7 constitute a reference frequency divider, and the comparison frequency divider 6 and the comparison frequency switch 8 constitute a comparison frequency divider. The delay circuit 9 and the frequency data setter 10 constitute frequency division control means.

When changing the output frequency, the frequency data setter 10 first sets the frequency division ratio of the frequency divider 4 to a desired ratio, and switches the switching signal a output from the delay circuit 9.
Is switched from “L” to “H”, a setting end signal c described later is output after the setting of the frequency division ratio in the frequency divider 4, and after a predetermined delay time, the switching output from the delay circuit 9 is performed. Control is performed so that the signal a is switched from “H” to “L”.

The reference frequency switch 7 is supplied with a reference frequency F1 and a divided reference frequency F1 'whose frequency is divided by the reference frequency divider 5 at a division ratio N (> 1).
Is "H", the reference frequency F1 is output. When the switching signal a is "L", the divided reference frequency F1 'is output.

The comparison frequency switch 8 receives the comparison frequency F2 and the divided comparison frequency F2 'whose frequency has been divided by the comparison frequency divider 6 at the division ratio N (> 1), and the switching signal a
Is "H", the comparison frequency F2 is output, and when the switching signal a is "L", the divided comparison frequency F2 'is output.

That is, when the switching signal a is "L", the divided reference frequency F1 'and the divided comparison frequency F2' are input to the phase comparator 1, and when the switching signal a is "H", the reference frequency F1 And the comparison frequency F2 are input to the phase comparator 1.

The phase comparator 1 compares the output of the reference frequency switch 7 with the phase of the output of the comparison frequency switch 8 and outputs a pulse train signal having a pulse width corresponding to the phase difference as a phase difference signal b. The phase difference signal b is converted into an analog voltage signal by the loop filter 2, and the output frequency F3 oscillated by the voltage controlled oscillator 3 is controlled by the analog voltage signal.

When the switching signal a is "L", the divided frequencies are compared with each other, so that even a slight phase difference is detected and the phase constrained state is maintained with high accuracy. In the case of "H", the frequencies which are not divided are compared with each other, so that the output frequency F3 changes in a short time, and immediately shifts to the phase locked state.

Then, the frequency divider 4 divides the output frequency F3 of the voltage controlled oscillator 3 by a desired frequency division ratio, and
Output as

In the PLL frequency synthesizer having the above configuration, before the output frequency F3 is changed, the switching signal “a” is “L”, and the voltage controlled oscillator 3 outputs the predetermined output frequency F3.
Is output in a phase constrained state. At this time, since the phase comparator 1 compares the divided frequencies, even a slight phase difference is detected, and the phase locked state is maintained with high accuracy.

In such a state, when changing the output frequency F3, the frequency data setter 10 sets the frequency division ratio of the frequency divider 4 to a desired ratio and changes the switching signal a from "L" to "H". Let it.

After the frequency data setter 10 completes the setting of the frequency division ratio in the frequency divider 3, the frequency data setter 10 outputs a setting end signal c. At this time, the switching signal a is still "H". , The reference frequency switch 7 outputs the undivided reference frequency F1, and the comparison frequency switch 8 outputs the undivided comparison frequency F2. Then, a phase difference signal b is output based on the phase difference between the two, and this phase difference signal b is converted into an analog voltage signal from which a pulse component has been removed by the loop filter 2, and the voltage controlled oscillator 3 Is controlled, the oscillation frequency F3 changes, and the comparison frequency F2 divided by the frequency divider 4 also changes.

At this time, since the comparison frequency F2 is input to the phase comparator 1 without being divided by the comparison frequency divider 6, the oscillation frequency F3 approaches the predetermined oscillation frequency at high speed, and shifts to the phase constraint state. I do.

When the switching signal a changes from “H” to “L” a predetermined delay time after the input of the setting end signal c, the reference frequency switch 7 divides the signal by the dividing ratio N (> 1). The frequency-divided reference frequency F1 'is output, and the frequency-divided comparison frequency F2' divided by the frequency division ratio N (> 1) is output from the comparison frequency switch 8; Is detected, and the phase is accurately locked.

Further, the lock-up time may be further reduced by outputting a time constant changing signal d for changing the time constant of the loop filter 2 from the delay circuit 9.

〔The invention's effect〕

As described above, according to the PLL frequency synthesizer of the present invention, when changing the oscillating frequency, the phase shifts to the phase locked state promptly, and after the lock-up after the elapse of a predetermined time, the phase locked state is accurately maintained. The effect is that a high-performance PLL frequency synthesizer can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a PLL frequency synthesizer according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Phase comparator, 2 ... Loop filter, 3 ... Voltage controlled oscillator, 4 ... Divider, 5 ... Reference frequency divider, 6 ... Comparison frequency divider, 7 ... Reference frequency Switching device 8, comparison frequency switching device 5, 7, reference frequency dividing means 6, 8, comparison frequency dividing means 9, delay circuit 10, frequency data setting device 9, 10, ... Dividing control means.

Claims (1)

(57) [Claims] 1. A reference frequency divider for dividing a reference frequency by a division ratio greater than 1, and a reference frequency switch for selecting and outputting one of an input signal and an output signal of the reference frequency divider. Frequency dividing means comprising a frequency divider, a comparison frequency divider for dividing the comparison frequency by a division ratio larger than 1, and one of an input signal and an output signal of the comparison frequency divider for switching. Comparison frequency dividing means comprising: a comparison frequency switching unit that outputs a reference frequency; a phase comparator that detects a phase difference between an output of the reference frequency switching unit and an output of the comparison frequency switching unit; A loop filter that outputs an analog voltage signal corresponding to the phase difference, an oscillator that oscillates a frequency based on the analog voltage signal, and a desired frequency division of the oscillation frequency of the oscillator. And a divider that outputs the comparison frequency as the comparison frequency to the comparison frequency divider.A PLL circuit, comprising: setting a division ratio in the divider to a desired division ratio; Thereafter, while controlling the reference frequency switch to selectively output the input signal of the reference frequency divider,
The comparison frequency switch is controlled so as to selectively output the input signal of the comparison frequency divider, and after a lapse of a predetermined time,
A frequency divider that controls the reference frequency switch to selectively output the output signal of the reference frequency divider and controls the comparison frequency switch to selectively output the output signal of the comparison frequency divider. A PLL frequency synthesizer comprising: control means;