JP2785996B2 - PLL frequency synthesizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Synchronous Group) frequency synthesizer, and more particularly to a frequency synthesizer capable of switching at a high speed at an output frequency.

[Conventional technology]

In general, a PLL frequency synthesizer includes a voltage controlled oscillator, a phase frequency comparator, a reference frequency oscillator, a loop filter, and the like. The output of the reference frequency oscillator divided by the first divider and the second divided frequency The output of the voltage-controlled oscillator divided by the comparator is compared with the phase-frequency comparator, and this comparison error is passed through a loop filter and fed back to the voltage-controlled oscillator, thereby controlling the oscillation frequency of the voltage-controlled oscillator. , To obtain the required frequency output.

[Problems to be solved by the invention]

In the above-mentioned conventional PLL frequency synthesizer, there are a frequency lock-in area and a phase lock-in area as responses when switching frequencies, and the time of these areas is a factor that determines the switching time of the output frequency. Conventionally, in order to shorten the switching time, attempts have been made to shorten the time in the frequency pull-in region by increasing the output frequencies of the first and second frequency dividers.

However, in the conventional frequency synthesizer, the first and second frequency dividers are merely used to pull in the phase by using the relative phase error change accompanying the frequency change by the voltage controlled oscillator. However, even if the output frequency is increased, it is difficult to shorten the time of the phase lock-in area, and as a result, it is difficult to switch the frequency at high speed.

An object of the present invention is to provide a PLL frequency synthesizer that can perform high-speed switching at high speed.

[Means for solving the problem]

A PLL frequency synthesizer according to the present invention includes a reference frequency oscillator, a voltage controlled oscillator, a variable phase shifter for changing a phase of an output of the voltage controlled oscillator, and each phase of output signals of the reference frequency oscillator and the variable phase shifter. And a frequency filter that compares the frequency and outputs a frequency error and a phase error, respectively, and a loop filter that smoothes the frequency error of the phase frequency comparator and serves as a control input of the voltage-controlled oscillator. The phase shift amount of the variable phase shifter is configured to be changed and controlled independently of the voltage control oscillator based on the frequency error based on the phase error of the phase frequency comparator.

In this case, a first frequency divider that divides the output of the reference frequency oscillator and a second frequency divider that divides the output of the variable phase shifter are provided. It is preferable to make the comparison by a vessel.

[Action]

According to the present invention, the output frequency of the voltage controlled oscillator is controlled based on the frequency error obtained from the comparison between the reference frequency oscillator and the voltage controlled oscillator in the phase frequency comparator, and the shift of the variable phase shifter is controlled based on the phase error. By controlling the phase amount, it is possible to shorten the time of each frequency and phase pull-in area.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, reference numeral 1 denotes a phase frequency comparator, which divides the output of a reference frequency oscillator 2 by a first frequency divider 3 and the output of a voltage controlled oscillator 4 by a second frequency divider 5. The frequency and the phase of each output are compared, and the frequency error ΔF and the phase error Δ
P can be output from terminals A and B as a voltage or a current, respectively. Further, the phase frequency comparator 1 has means for distinguishing between the frequency lock-in state and the phase lock-in state, and has a function of fixing the phase error ΔP from the terminal B in the frequency lock-in state.

A loop filter 6 for smoothing the output of the frequency error ΔF is connected to a terminal A of the frequency error ΔF of the phase frequency comparator 1, and the smoothed output voltage of the loop filter 6 is applied to the voltage controlled oscillator 4. And the output frequency of the voltage controlled oscillator 4 is controlled to change. A variable phase shifter 7 is connected to an output terminal of the voltage controlled oscillator 4, and the output terminal of the variable phase shifter 7 is connected to the second frequency divider 5.
Are connected. The control terminal of the variable phase shifter 7 has a phase error ΔP from the terminal B of the phase shift frequency comparator 1.
Is input, and the phase shift amount is changed and controlled by the phase error ΔP.

According to this configuration, in the phase frequency comparator 1, the output of the reference frequency oscillator 2 divided by the first divider 3 and the output of the voltage controlled oscillator 4 divided by the second divider 5 are output. The output phase and frequency are compared. Then, the frequency error ΔF output from the terminal A is smoothed by the loop filter 6, and the output frequency of the voltage controlled oscillator 4 is controlled by the output voltage to obtain a required output frequency. At this time, by increasing the output frequencies of the first frequency divider 3 and the second frequency divider 5, the time in the frequency lock-in region can be shortened.

On the other hand, the amount of phase shift of the variable phase shifter 7 is changed from the terminal B of the phase shift frequency comparator 1 based on the phase error ΔP obtained by comparing the output of the reference frequency oscillator 2 and the voltage controlled oscillator 4, Control is performed so that the phase error between the two outputs becomes zero.
This makes it possible to shorten the time of the phase acquisition region.

When the frequency error ΔF is larger than a preset value, the output from the terminal B of the phase frequency comparator 1 should be prevented from being output, and unnecessary disturbance at the time of frequency pull-in should not be given to the system. Frequency pull-in can be performed stably.

Here, it goes without saying that in the present invention, the first frequency divider and the second frequency divider may be constituted by variable frequency dividers.

〔The invention's effect〕

As described above, the present invention controls the output frequency of the voltage controlled oscillator based on the frequency error obtained from the comparison between the reference frequency oscillator and the voltage controlled oscillator in the phase frequency comparator, and based on the phase error obtained simultaneously. Since a variable phase shifter in which the amount of phase shift is provided is provided, controlling the amount of phase shift can shorten the time of the phase pull-in region, and the effect of switching the frequency at high speed can be obtained. is there. In the present invention, the control of the voltage-controlled oscillator based on the frequency error and the control of the variable phase shifter based on the phase error can be performed independently. Therefore, when the frequency error is large, the control of the variable phase shifter is temporarily performed. In this case, unnecessary disturbance during the pull-in operation of the voltage-controlled oscillator can be suppressed, and stable frequency pull-in can be quickly performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a PLL frequency synthesizer of the present invention. 1 ... Phase frequency comparator, 2 ... Reference frequency oscillator, 3
... First divider, 4... Voltage-controlled oscillator, 5.
, A loop filter, and a variable phase shifter.

Claims (2)

(57) [Claims] A reference frequency oscillator; a voltage controlled oscillator;
A variable phase shifter for changing the phase of the output of the voltage controlled oscillator, and a phase frequency comparison for comparing each phase and frequency of the output signals of the reference frequency oscillator and the variable phase shifter to output a frequency error and a phase error, respectively. And a loop filter that smoothes the frequency error of the phase frequency comparator and serves as a control input of the voltage controlled oscillator, and the phase shift amount of the variable phase shifter based on the phase error of the phase frequency comparator. Characterized in that PL is controlled to change independently of the control of the voltage-controlled oscillator by the frequency error.
L frequency synthesizer. A first frequency divider for dividing the output of the reference frequency oscillator; and a second frequency divider for dividing the output of the variable phase shifter. 2. The PLL frequency synthesizer according to claim 1, wherein said PLL frequency synthesizer is configured to compare by a frequency comparator.