JPH0719440B2 - PLL circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention extracts the clock component from the NRZI data string and outputs the NR
PL that generates a demodulation clock to demodulate the ZI data string
It relates to the L circuit.

[Technical background of the invention and its problems]

A PLL circuit of this kind finds its use in, for example, a rotary head digital audio tape recorder (R-DAT).

In R-DAT, for example, 16-bit data is divided into upper 8 bits and lower 8 bits, and recorded as an 8 / 10-modulated (8 / 10M) NRZI data string in which a 10-bit code is associated with each 8 bits. Is being done. Then, in order to demodulate the reproduced NRZI data sequence, that is, the 8 / 10M signal, it is necessary to extract a clock component from the NRZI data sequence and read the data by the demodulation clock generated based on the extracted clock component.

In order to read the data with a minimum error rate, a demodulation clock having a frequency twice the maximum repetition frequency of the NRZI data string and having a predetermined phase relationship with the NRZI data string is required. For this purpose, the 8 / 10M signal is input as the reference input of the phase comparator of the PLL circuit, and the output signal of the VCO that is the demodulation clock is input as the variable input, and the VCO is controlled by the output of the phase comparator to control the 8 / 10M signal. A VCO is used to generate a demodulation clock whose phase matches the signal.

However, in the phase comparator, the frequency of the 8 / 10M signal is too different from the free-running frequency of the VCO, and if the difference between both frequencies is not within the predetermined range generally called the capture range, no signal appears at the output and the VCO control Therefore, the PLL circuit is not in the phase locked state forever.

By the way, when the reproduction is turned on in the R-DAT, the tape running is started by the circuit of the capstan, the drum having the rotary head is rotated, and the rotary head is run on the tape. As a result, the recording on the tape is reproduced by the rotary head and an 8 / 10M signal is obtained. However, unless the relative speed between the rotary head and the tape reaches a predetermined value, an 8 / 10M signal of a regular frequency cannot be obtained. Therefore, various measures have been made to the drum servo and the capstan servo so that the relative speed of the rotary head and the tape reaches a predetermined value early after the reproduction is turned on, but there is a limit to this and the servo system is There are drawbacks such as being expensive.

Although such a defect can be solved by expanding the capture range of the PLL circuit, there has been no PLL circuit having a capture range sufficient to satisfy this in the past.

[Object of the Invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks of the related art, and an object thereof is to provide a PLL circuit that can realize a sufficiently large capture range.

〔Overview〕

In order to achieve the above object, the PLL circuit according to the present invention aims to expand the capture range by enabling the voltage controlled oscillator to be controlled not only by the output of the phase comparator but also by the output of the frequency comparator. There is.

〔Example〕

An embodiment of a PLL circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the embodiment. In FIG. 1, 1 is a signal input terminal to which an 8 / 10M signal which is a reproduction signal of R-DAT is input, and 2 is a demodulator of an 8 / 10M signal. This is a clock output terminal that outputs the demodulated clock generated by the PLL circuit. Reference numeral 3 is a phase comparator (PD) in which the 8 / 10M signal is input to the reference input and the demodulation clock is input to the variable input. In PD3, the frequency difference between the 8 / 10M signal and the demodulation clock is the first capture range. When it is within the range, the two phases are compared and an error signal having a magnitude and polarity corresponding to the phase shift amount and the direction is output. 4 is a frequency comparator (FC) to which the 8 / 10M signal is input to one input and the demodulation clock is input to the other input.
Then, when the frequency difference between the 8 / 10M signal and the demodulation clock is within the second capture range wider than the first capture range, the two frequencies are compared and the magnitude and polarity corresponding to the frequency deviation amount and direction are respectively set. The error signal of is output.

The error signals from PD3 and FC4 are input to each of the two inputs of the adder 7 after the high frequency components are removed by the first low pass filter (LPF) 5 and the second LPF6, respectively. The adder 7 adds both error signals and applies it to the control input of a voltage controlled oscillator (VCO) 8. The VCO8 has its oscillation frequency controlled by a control signal applied to its control input and generates a demodulation clock at its output.

In this example, the first capture range is approximately ± 5% and the second capture range is approximately ± 10%, and the PLL circuit as a whole works to have a capture range of ± 10%. .

By the way, the 8 / 10M signal is composed of an NRZI data string as shown in FIG. 2 (a), which is a combination of HL pulses of 1T, 2T, 3T, and 4T when the minimum time interval is T due to its modulation principle. . Note that T changes depending on the relative speed of the rotary head and the tape, and at a predetermined relative speed during normal reproduction, And the demodulation clock cycle at that time Is equal to

From the above, a frequency comparator for performing frequency comparison of continuous signals with a constant period cannot be used for frequency comparison between the 8 / 10M signal and the demodulation clock.

FIG. 3 is a timing chart showing the principle of FC4. In the explanation of the principle, for the sake of simplicity, it is assumed that the 8 / 10M signal is composed of a series of 8 / 10M of 1T HL, as shown in FIG. 3 (a). Now, when the frequency of the demodulation clock is higher than the frequency of the 8 / 10M signal as shown in FIG. 3 (b),
The rising edge of the demodulated clock may appear twice within the HL T period of the 8 / 10M signal, as indicated by the vertical arrow. On the other hand, when the frequency of the demodulation clock is lower than the frequency of the 8 / 10M signal as shown in FIG. 3 (c), the rising edge of the demodulation clock is 8/10 as shown by the horizontal arrow.
It may not appear at all within the T period of the HL pulse of the M signal.

Therefore, it is possible to know that the frequency of the demodulation clock is high by detecting that the rising edge of the demodulation clock appears twice within the period of 1T pulse, and the frequency of the detection is proportional to the frequency difference. Also, by detecting that no rising edge of the demodulation clock appears within the period of 1T pulse, it can be known that the frequency of the demodulation clock is low, and the frequency of the detection is proportional to the frequency difference.

Therefore, an error signal having a magnitude and polarity corresponding to the detection frequency and its content is generated, and this is generated by the LPF 5 and the adder 8
By applying to VCO8 via
The oscillation frequency of the VCO8 can be controlled so that the 8 / 10M signal frequencies match.

If the frequency difference between the 8 / 10M signal and the demodulation clock falls within the first capture range during the above control process, PD3
An error signal also appears in the output of, and the VCO8 is controlled by adding this and the error signal from FC4, and finally the frequency and phase of the 8 / 10M signal and the demodulation clock match. Get locked.

Next, the principle of detecting 1T pulse from 8 / 10M signal
It will be described with reference to the drawings. In order to detect the 1T pulse, it is sufficient to distinguish it from the 2T pulse, and this determination ability determines the second capture range. Now, assuming that the capture range is ± 10%, the maximum time interval for 1T pulse is 1.1T, and the minimum time interval for 2T pulse is 1.8T.
Therefore, if the interval can be measured with an accuracy of 0.7T, which is the difference in time interble between both pulses, that is, with an accuracy of ± 0.35T, 1T pulse can be detected separately from 2T pulse. Therefore, in order to detect the 1T pulse from the pulse signal, it is sufficient to use a constant frequency detection clock having a period of 0.35T generated by the crystal oscillator.

Of course, the same operation may be performed by detecting a 2T pulse,
In this case, a detection clock having a high frequency is required to discriminate between the 2T pulse and the 3T pulse, which is not practical because it may be unfavorable in terms of the high frequency characteristics of the IC.

FIG. 5 shows a concrete example of FC4 which operates based on the above-mentioned principle. In the figure, 4-1 is a detection clock input terminal to which a detection clock having a frequency of a period 0.35T is inputted, 4-2.
Is an 8 / 10M signal input terminal to which an 8 / 10M signal is input, and 4-3 is a demodulation clock input terminal to which the output of VCO8 (FIG. 1) is input.

The detection clock is input to the clock inputs CK of the 3-bit counters 4-6 and 4-7 via the AND gates 4-4 and 4-5, respectively, and the D latch circuit 4 via the inverter 4-8.
It is input to the clock inputs CK of -9 and 4-10, and to the clock input CK of the shift register 4-11, respectively. 8 /
The 10M signal is input to the reset input R of the counter 4-6 and the clock input of the D latch circuit 4-13 via the inverter 4-12.
The reset input R of the counter 4-7, the serial data input SI of the shift register 4-11, and the D latch circuit 4-14 are input to CK.
Clock input CK, one input of AND gate 4-15 and N
It is input to one input of each of the OR gates 4-16. The demodulated clock is input to clock inputs CK of counters 4-19 and 4-20 via AND gates 4-17 and 4-18, respectively.

The Q3 outputs of the counters 4-6 and 4-7 are D latch circuits 4-
9 and 4-10 are respectively input to the D inputs, and the Q outputs of the D latch circuits 4-9 and 4-10 are inverters 4-21 and 4 respectively.
Gate signals are input to the inputs of the AND gates 4-4 and 4-5 via −22 respectively. The output of the inverter 4-21 is input to one of the AND gates 4-23 and 4-24, and the output of the inverter 4-22 is the AND gate 4-25.
, And 4-26, respectively.

The Q2 output of the shift register 4-11 is AND gate 4-15 and O.
It is input to the other input of the R gate 4-16. AND
The output of the gate 4-15 is input to the reset input R of the D latch circuit 4-13 and the counter 4-20, and the output of the NOR gate 4-16 is input to the reset input R of the D latch circuit 4-14 and the counter 4-19. To be done. Counters 4-19 and 4-20
The Q1 output is input to one input of NOR gates 4-27 and 4-28, respectively, and the Q2 output of the counter 4-19 is input to the other inputs of AND gate 4-23 and NOR gate 4-27, respectively. AND gate 4 via inverter 4-23
Input to the other input of -17.

The Q2 output of the counter 4-20 is input to the other inputs of the AND gate 4-25 and NOR gate 4-28, respectively, and is also input to the other input of the AND gate 4-18 via the inverter 4-30. .

The outputs of the NOR gates 4-27 and 4-28 are input to the other inputs of the AND gates 4-24 and 4-26, and the outputs of the AND gates 4-23 and 4-24 are D1 and D1 of the D latch circuit 4-14. The outputs of the AND gates 4-25 and 4-26 are input to the D2 input, respectively, and are input to the D1 and D2 inputs of the D latch circuit 4-13, respectively.

The Q1 and Q2 outputs of the D latch circuit 4-14 are input to one of the inputs of the OR gates 4-31 and 4-32, and the Q1 and Q2 of the D latch circuit 4-13 and
The Q2 output is input to the other inputs of the OR gates 4-31 and 4-32. The outputs of the OR gates 4-31 and 4-32 are input to the inputs of the mono-multivibrator (MMV) 4-33 and 4-34, and the outputs of the MMV4-33 and 4-34 are the -input and the -input of the increaser 4-35. Each is input to the + input, and the output of the adder 4-35 is input to the input of the second LPF 6 (FIG. 1).

The counters 4-6, 4-7, 4-19 and 4-20 count "1" when the clock input CK falls from H level to L level, and the reset input R changes from L level to H level. It is reset in response to rising and does not count during the H-level period. The shift register 4-11 takes in and shifts the state of the 8 / 10M signal of the serial data input SI in response to the fall of its clock input from H level to L level. The D latch circuits 4-9 and 4-10 have their clock inputs
When the CK falls from the H level to the L level, the state of the D input is taken in, latched and sent to the Q output. The D latch circuits 4-13 and 4-14 fetch and latch the states of D1 and D2, respectively, in response to the clock input CK falling from H level to L level, and send them to the Q1 and Q2 outputs, respectively.

The operation of the above configuration will be described with reference to the timing charts of FIGS. 6 to 8 showing the waveforms of the respective portions in FIG.

Now, as shown in FIG.
It is assumed that the 0M signal is input and the demodulation clock having the same frequency as the demodulation clock to be originally reproduced is input to the demodulation clock input terminal 4-3. The counter 4-6, to which the 8 / 10M signal is input to the reset input R via the inverter 4-12, does not count the detection clock while the 8 / 10M signal is at the L level, but counts only at the H level. I do. On the other hand, the counter 4-7 in which the 8 / 10M signal is directly input to the reset input R does not count the detection clock while the 8 / 10M signal is at the H level, but only during the L level period.

If both D latch circuits 4-9 and 4-10 are in a state of latching L level, their Q outputs are both L level.
AND gates 4-4, 4-23, 4-- which are at the level and are inputted via the inverters 4-21 and 4-22, respectively.
24 and AND gates 4-5, 4-25, 4-26 are open. Therefore, the outputs of the AND gates 4-4 and 4-5 are shown in FIG.
The detected clocks that have passed through these appear as shown in FIGS. 6 and 7, and are input to the clock inputs CK of the counters 4-6 and 4-7, respectively.

The counter 4-7 counts the detection clock appearing at the output of the AND gate 4-5 between the time t ₀ and the time t ₁ when the 8 / 10M signal is at the L level, but the time before the count value becomes 4 Since it is reset at t ₁ , the output of the counter Q3 is at L level as shown in FIG. 6e. Time point
The counter 4-6 does not count between t _{0 and} t ₁ , and 8 /
The detection clock is counted between the time points t _{1 and} t ₂ when the level of the 10M signal is H level. But this t ₁ ~
Since the period of t ₂ is equal to T and four detection clocks cannot be counted within this T time, the counter 4
The Q3 output of -6 also remains at L level. Counter 4-6
And 4-7 are reset and ready for the next count by the falling and rising edges of the 8 / 10M signal, respectively.

During the next time point t _{2 to} t ₃ , the counter 4-7 counts the detection pulse. This time period from t _{2 to} t ₃ is equal to 2T, so within this 2T time the counter 4-7 counts four detection clocks, at which time its Q3 output changes from L to L as shown in FIG. 6e. It rises to the H level and the D latch circuit 4-10
D input of goes from L to H level. The D input at the H level is latched by the D latch circuit 4-10 at the falling edge of the detection pulse input to the clock input CK of the D latch circuit 4-10, and its Q output which has been at the L level until then is output. H
The output of the inverter 4-22, which becomes the level and is inverted, becomes the L level as shown in FIG. 6f. Inverter 4-
When the output of 22 becomes L level, AND gate 4-
5 is closed, the detection clock no longer appears at its output, as shown in FIG. 6d, and no further counting of the counters 4-7 takes place. The counter 4-7 is reset when the 8 / 10M signal rises from the L level to the H level at the time point t ₃ , and its Q output becomes the L level.
The level of the next detection clock causes the D latch circuit 4-10
Latched by the output of the inverter 4-22,
The level becomes high, the AND gate 4-5 is opened again, and the detection clock appears again at the output of the AND gate 4-5 as shown in FIG. 6d.

During the next time point t _{3 to} t ₄ , the counter 4-6 counts the detection clock. This period from t _{3 to} t ₄ is equal to 3T,
Therefore, the counter 4-6 counts four detection clocks within this 3T time, and at that time, the Q3 output rises from the L level to the H level as shown in FIG. The D input changes from L level to H level. This H level D input is the clock input of the D latch circuit 4-9.
At the falling edge of the detection pulse input to CK, the D output is latched by the D latch circuit 4-9, its Q output, which was at L level until then, becomes H level, and the output of the inverter 4-21 which inverts this is As shown in FIG. 6c, it becomes L level. When the output of the inverter 4-21 becomes L level, the AND gate 4-4 is closed, the detection clock does not appear at its output as shown in FIG. Is not done. The counter 4-6 is reset when the 8 / 10M signal rises from the H level to the L level at the time point t ₄ , and its Q output becomes the L level, so that the L level is changed by the next detection clock to the D latch circuit 4-. The output of the inverter 4-21 becomes H level, the AND gate 4-4 is opened again, and the detection clock appears again at the output of the AND gate 4-4 as shown in FIG. 6a. Like

Hereinafter, the same operation as described above is performed, and the inverter 4-
As shown in FIG. 6c, the output of 21 becomes L level when the 8 / 10M signal is at H level except 1T, and the output of the inverter 4-22 is as shown in FIG. 6f. , 8 / 10M
When the signal is at L level for a period other than 1T, it becomes L level. The outputs of the inverters 4-21 and 4-22 are input as gate signals to the AND gates 4-23, 4-24 and AND gates 4-25, 4-26.

The shift register 4-11 delays the 8 / 10M signal input to its serial data input SI by two detection clock cycles and sends it to its Q2 output, as shown in FIG. 6g. The Q2 output of this shift register 4-11 is the AND gate 4-15 and the NOR gate 4-4 whose 8 / 10M signal is input to one input.
Input to 16 other inputs. As a result, the outputs of the AND gate 4-15 and NOR gate 4-16 are shown in FIG.
And i respectively appear and are applied to the reset inputs R of counters 4-20 and 4-19, respectively.

The counters 4-19 and 4-20 are reset when the reset input R rises from the L level to the H level, do not count during the H level, and the clock input CK is held while the reset input R is at the L level. Every time it falls from H to L level, "1" is counted. Then, in these reset states, the Q1 and Q2 outputs are both at the L level.

The clock inputs of the counters 4-19 and 4-20 are demodulated via AND gates 4-17 and 4-18, which are gate-controlled by signals obtained by inverting the respective Q2 outputs by inverters 4-29 and 4-30. The clock is set to be input. The AND gates 4-17 and 4-18 allow the counters 4-19 and 4-20 to set the falling edge of the demodulation clock from H level to L level by 2 respectively.
It is opened as long as the Q2 outputs are not counted at the H level after counting the times, and the demodulation clock is passed as shown in FIGS. 6j and 0, respectively.

Now, regarding the counter 4-19, while the reset input R is at the L level, the falling of the demodulation clock from the H level to the L level is counted, and when the count value is 1, its Q1 output is shown in FIG. As shown, it becomes H level. Then, when the reset input R rises from the L level to the H level, it is reset, and its Q1 output falls from the H level to the L level as shown in FIG. When the reset input R of the counter 4-19 is at L level for a long period of time, the falling edge of the demodulation clock from L to H is counted twice, and its Q2 output is L level as shown in FIG.
To rise to H level. The Q1 and Q2 outputs of the counter 4-19 are input to the NOR gate 4-27, but the NOR gate 4-
The output of 27 becomes H level when both inputs are at L level, and becomes L level at other times, and this is input to the AND gate 4-24. Since the Q2 output of the counter 4-19 is input to the AND gate 4-23, the outputs of the AND gates 4-23 and 4-24 are at H level while both inputs thereof are at the H level. As shown in FIG. The D latch 4-14 latches the D1 and D2 inputs when the 8 / 10M signal input to the clock input CK falls from H level to L level.
8 / 10M when the frequency of the signal and demodulation clock are equal
At the time when the signal falls, the outputs of the AND gates 4-23 and 4-24 are not at the H level, and the latch circuit 4-14
Is not latched to the H level, and both Q1 and Q2 outputs are kept at the L level.

The same is apparent from FIGS. 6 p and q showing the Q1 and Q2 outputs of the counter 4-20, respectively, and FIG. 6 r and s showing the outputs of the AND gates 4-25 and 4-26, respectively. It also occurs at the Q1 and Q2 outputs of the D latch circuit 4-13.

Thus, the output of OR gate 4-31 and 4-32 keeps together L level as shown in FIG. 6 f _H and f _L, MMV4-33 and 4
-34 is not triggered and therefore no signal is sent from the output of adder 4-35 to LPF6 (Fig. 1).
Is kept as is.

On the other hand, when the frequency of the demodulated clock becomes high as shown in FIG. 7, the waveform of each part in FIG. 5 changes as shown in FIGS. pulse as shown in FIG. 7 f _H is generated in the output. OR gate 4-
Since the pulse width that appears at the output of 31 is not constant, this triggers MMV4-33 to generate a pulse of constant width,
By inputting this to the-input of the adder 4-35, a negative pulse is output at its output. The negative pulse of the output of the adder 4-35 is input to VCO8 as an error signal after LPF6 (the high frequency component is removed in FIG. 1). Since this error signal has a negative value, VCO8 Reduce the oscillation frequency.

FIG. 8 shows the waveform of each part when the frequency of the demodulation clock is low. As is clear from the figure, a pulse as shown in FIG. 8 f _L is generated at the output of the OR gate 4-32, and Based on this, a positive error voltage signal is applied to VCO8 (FIG. 1) to raise the frequency of VCO8.

〔effect〕

As described above, according to the present invention, in addition to the phase comparator, a frequency comparator capable of comparing the frequencies of the NRZI data string and the demodulated clock is provided, and the voltage controlled oscillator is output by the outputs of both comparators. Since it is controlled, the capture range can be widened, and the demodulation clock can be phase-locked to the NRZI data string at an early stage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram showing an example of an 8 / 10M signal, and FIG. 3 is for explaining the principle of the frequency comparator in FIG. 4 is an explanatory diagram for explaining the principle of detecting the minimum time interval, FIG. 5 is an electric circuit block diagram showing a concrete example of the frequency comparator in FIG. 1, and FIGS. FIG. 8 is a timing chart showing the waveform of each part in FIG. 3 ... Phase comparator, 4 ... Frequency comparator, 7 ... Adder, 8 ... Voltage controlled oscillator, 4-4, 4-5 ... AND gate, 4-6, 4-7, 4-19 , 4-20 ... Counter, 4-9,4-1
0,4-13,4-14 ... D latch circuit, 4-11 ... Shift register.

Claims (1)

[Claims] 1. A voltage-controlled oscillator for generating a demodulation clock of an NRZI data string, and a demodulation clock from the voltage-controlled oscillator as a variable input,
And a phase comparator that compares the phases of the NRZI data string as a reference input and outputs a signal according to the phase shift, and compares the frequency of the demodulation clock from the voltage-controlled oscillation yellow with the frequency of the NRZI data string. A frequency comparator that outputs a signal according to a shift, and an output of the phase comparator and an output of the frequency comparator are added, and an adder that controls the voltage-controlled oscillator according to the addition result is provided. The comparator comprises interval detection means for detecting data of the minimum time interval from the NRZI data string, and counting means for counting the number of demodulation clocks from the voltage controlled oscillator appearing within the detected data length. A PLL circuit, which outputs a signal according to a frequency difference between the NRZI data string and the demodulated clock based on the result.