JP2979528B2 - PLL frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer in which a lock-up time is shortened without deteriorating spuriousness and responsiveness when switching channels of a radio transceiver.

[0002]

2. Description of the Related Art Conventionally, in order to shorten the channel switching time of a radio transceiver, the number of divisions of a variable frequency divider and a reference frequency divider in a PLL loop is changed as shown in FIG. At the time of switching the output frequency, the comparison reference frequency is set to n times the steady state for a certain time after the start of the switching, and at the same time, the frequency division number of the variable frequency divider after the completion of the switching is set to n.
There is a proposal of a switching system in which the constant of the loop filter is changed to approximately 1 / n of the quotient of the halved value.

However in now to Figure 3 the relationship between the output frequency f ₀ = f _r × N of the voltage controlled oscillator satisfied, the channel step frequency Δf = f _r. For example, f ₀ = 800.
If set to 025KHz, temporarily to step up the f _r f _r = 400KHz, frequency division number N = 2,000, f ₀ =
After setting to 800.000 MHz and locking at high speed, switching to a steady loop is performed, f = 25 KHz, N = 32,001,
f ₀ = 800.025 MHz. However, FIG.
From the relationship between the control voltage of the VCO and the output frequency,
For example, f ₀ is changed from 800 MHz to 800.2 MHz or 8
If you try to change from 00.4MHz to 800.2MHz, you have to move the frequency as much as 200KHz,
After all, it is too ineffective to reduce lock-up time.

[Problems to be solved by the invention]

According to the present invention, when the frequency division number of the variable frequency divider is changed in order to change the output frequency of the voltage controlled oscillator which is the final output of the PLL system, the interval of the reference frequency, ie, f
Since changes in _r step, change the output frequency of the voltage controlled oscillator fine, but must be kept to a low reference frequency f _r from the beginning, when it is lowered PL
In order to maintain the stability of the phase synchronization of L, the time constant of the integrator constituting the loop filter must be increased, and as a result, it is necessary for the output frequency of the voltage controlled oscillator to stabilize when the frequency is switched. There has been a problem that the time becomes longer and the responsiveness eventually deteriorates.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, the present invention provides a switch having a variable reference frequency divider for temporarily increasing the reference frequency and switching between a normal frequency and a normal frequency. A variable frequency divider, a two-modulus prescaler, and a pulse swallow counter are combined so that the PLL is locked below the reference frequency, and the frequency detection function attached to the phase comparator is used to respond to the synchronization status. A control unit for switching the loop is provided to ensure the stability and spuriousness of the PLL system.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a circuit diagram of a PLL synthesizer according to the present invention. Reference numeral 11 denotes a fixed oscillator that sends out a reference frequency, 12 denotes a first variable frequency divider that variably divides a reference frequency, and 13 has a synchronous detection function. A phase comparator, 14 is a loop filter composed of an integrator, 15 is a voltage-controlled oscillator, and 16 and 17 are movable contacts in a steady state (steady operation).
a and the movable contact (high-speed lock-up operation) b of the high-speed lock-up operation are interlocked and switched, so that the output frequency f ₀ of the voltage-controlled oscillator is provided on the feedback route to the phase comparator. The second changeover switches 18 and 19 are a second variable frequency divider and a third frequency divider, respectively. Reference numeral 20 denotes a two-modulus prescaler having a frequency dividing function whose frequency dividing ratio can be changed in two ways, 21 a first counter having a set value of Ns, and 22 a second counter which is set to N _A smaller than Ns. The counter 23 is a control unit such as a CPU, and a command is transmitted via the BUS.

The additional functions of the first and second counters, the third variable frequency divider, the two-modulus prescaler, and the like will be described. Among the set values Ns of the first counter, the set value N _A of the second counter is: Np + 1 frequency division, Ns-N times N
The frequency is divided by p and the divided output frequency is applied to a third variable frequency divider. This frequency is divided by Ni and the first and second selector switches are compared with each other when the high-speed lock-up contact b is connected. since applied to vessels, give the pulse output corresponding to the phase difference between the reference frequency f _r, and smoothed DC voltage to the pulse by the loop filter, it is fed back as an input of the voltage controlled oscillator.

[0008] In the loop configuration of such present invention, the output frequency f ₀ of the voltage controlled oscillator is _{f 0 = f r × Ni ×} {N A
(Np + 1) + Np (Ns−N _A )｝ Ns (Ns>
Given by N _A), after all _{f = f r × Ni × (} Np + N A
/ Ns), and if the frequency step is Δf, Δf
= (F _r / Ns) becomes × Ni, it is possible to vary the output frequency of the voltage controlled oscillator at f _r / Ns step by varying the number of Ni, that the third variable divider, a reference frequency f _{Since r} can be increased, the lock-up time of the PLL can be shortened. By the way, the spurious often occurs near the output frequency of the voltage controlled oscillator which is the PLL output having the above-mentioned configuration, and the first and the second are operated by the operation of the synchronization detecting function attached to the phase comparator at the moment when the PLL is synchronized. The second switching switch is returned to a steady state to eliminate noise in the loop. Also, when switching loops, the phase comparator compares the divided frequency of the divided frequency f _r of the first variable frequency divider 12 the output frequency of the fixed oscillator and the second variable frequency divider 18 in phase It has a configuration.

[0009]

According to the present invention, since the reference frequency is temporarily increased by the variable frequency divider without switching and changing the reference frequency of the fixed oscillator itself, the output frequency of the voltage controlled oscillator serving as the PLL output is increased. At the time of switching, for a certain period immediately after the start of the switching, the above-mentioned reference frequency is made to be a fixed multiple, and the loop gain is increased so that the lock-up time is shortened. This is different from the configuration in which noise enters from the power supply for generating the preset voltage, and the setting value of the preset voltage increases when switching between multiple channels, and the circuit becomes complicated and power consumption increases. The circuit configuration of the present invention can be of a low power consumption type, and constitutes a synthesizer that does not impair spurious characteristics and responsiveness. It has become possible. In addition, PLL
When returning the loop of the system from high speed to the steady state, the reference frequency and the divided frequency of the variable frequency divider are compared in the same phase at first. Operate. In addition, it is possible to control the switching of the loop by obtaining a comparison output, and to combine a two-modulus prescaler and a pulse swallow type counter with a variable frequency divider so that the PLL is locked below the reference frequency. Therefore, the complexity of the circuit configuration of the entire PLL system is prevented.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a PLL frequency synthesizer according to the present invention.

FIG. 2 is a graph showing a relationship between a control voltage and an output frequency of the voltage controlled oscillator in FIG.

FIG. 3 is a circuit block diagram of a conventional PLL frequency synthesizer.

FIG. 4 is a graph showing a relationship between a control voltage and an output frequency of the voltage controlled oscillator of FIG. 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Fixed oscillator 12 1st variable frequency divider 13 Phase comparator 14 Loop filter 15 Voltage controlled oscillator 16 and 17 1st, 2nd changeover switch 18 2nd variable frequency divider 19 3rd variable frequency divider 20 2 Modulus prescaler 21 the first counter 22 second counter 23 outputs the frequency of the divided output frequency f ₀ voltage controlled oscillator of the control unit f _r the reference frequency

Claims (1)

(57) [Claims] 1. A feedback loop to a voltage controlled oscillator via a loop filter, wherein a comparison output frequency by a phase comparator between a divided frequency of an output frequency of a voltage controlled oscillator for generating a frequency of a frequency synthesizer and a reference frequency of a fixed oscillator is provided. A first frequency divider for dividing the reference frequency of the fixed oscillator, a phase comparator having a synchronization detection function for receiving the divided frequency of the first variable frequency divider, A pulse swallow type first switch having a fixed contact and a movable contact for turning on and off a second variable frequency divider provided in a feedback circuit for the output frequency of the voltage controlled oscillator to the phase comparator; Counter and second
A first switch and a second switch that are provided with movable contacts on the input side and the output side, respectively, which connect the two-modulus prescaler responsive to the counter, and command the set values of the frequency dividers and the counters. And a control unit that issues a switching command to the first variable frequency divider, the loop filter, and each of the changeover switches after detecting that the phase comparator has entered the lock range. A PLL frequency synthesizer wherein a time loop is variably switched.