JP2002158581A - Frequency-variable pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency-variable PLL circuit, in which time for stabilizing the PLL circuit is reduced and the jitter of an output signal is suppressed. SOLUTION: The PLL circuit consists of frequency dividers 11 and 12, respectively having a plurality of frequency-dividing circuits A1 to An and B1 to Bn, selectors 13 and 14 for selecting these circuits A1 to An and B1 to Bn, a phase detector 15 and a VCO 16. The detector 15 includes a phase comparing circuit 31, a jitter detection circuit 32 and a frequency-dividing ratio selection circuit 33. The circuit 33 has a selector 41 for inputting a jitter detection signal and a logical gate 42 for inputting the output signal of the selector 41 and a synchronization detection signal from the circuit 31 to generate a frequency division ratio selection signal for controlling the selectors 13 and 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phase Lock).
The present invention relates to an ed Loop) circuit, particularly to a frequency variable PLL circuit.

[0002]

2. Description of the Related Art A PLL circuit uses a phase comparator and a voltage controlled oscillator (VCO), for example, a feedback (feedback) used for extracting (demodulating) a baseband signal from a frequency-modulated carrier. ) It is a loop. The prior art relating to such a PLL circuit is disclosed, for example, in Japanese Patent Application Laid-Open No. 5-227017, "Convergence Mode Switching Digital PLL Device" and Japanese Patent Application Laid-Open No. 2000-22523.
No. 6,086,098, which is incorporated herein by reference.

The above-mentioned prior art is shown in a block diagram of FIG. This PLL circuit includes a frequency dividing circuit A101, a frequency dividing circuit B102, a phase comparator 103, and a VCO 104.
It consists of. The input signal (or reference signal) is input to the frequency dividing circuit B102. On the other hand, the output of the VCO 104 is taken out as the output signal of the PLL circuit and is inputted to the frequency dividing circuit A101. Then, these frequency dividing circuits A1
01 and the frequency dividing circuit B10
The comparison signal B, which is the output signal of No. 2, is input to the phase comparator 103 and is compared in phase. The UP control signal and the DOWN control signal from the phase comparator 103 are applied to the V control signal through a filter circuit composed of a resistor R and a capacitor C.
The output signal is input to the CO 104 and has a frequency corresponding to the DC control signal.

On the other hand, the latter prior art described above is shown in a block diagram of FIG. This PLL circuit includes a main counter 201, an N-ary counter 203, and a P counter 204. Here, the N-ary counter 203 and the P counter 204 constitute a pulse counter 202. In the PLL circuit 200, the up signal Sup and the down signal Sdw from the phase comparator are counted, and the main counter 201 increases or decreases the count value M according to the count result of the N counter 203 for setting the count value. P counter 204 counts clock signal PLCK output from the frequency multiplier. The selection circuit selects the count value M of the main counter 201 and outputs it to the frequency multiplier until the count value reaches the count value A of the N-ary counter 203. When the count value of the P counter 204 is between (A + 1) and (N-1), the operation value (M ± 1) is selected and output to the frequency multiplier. Thus, it is possible to reduce the jitter of the oscillation signal PLCK of the frequency multiplier and to supply a stable clock signal.

[0005]

However, the above-mentioned conventional PLL circuit has the following problems. First, in order to shorten the time (frequency stabilization time) until the frequency of the reference clock signal matches the frequency of the output of the voltage controlled oscillator (frequency stabilization time), the conventional PLL circuit increases the phase comparison frequency. And the jitter component increases. The reason is that the sensitivity of the PLL increases with an increase in the phase comparison frequency, and the response of the phase comparison circuit to a frequency change becomes more sensitive. As a result, the control over the oscillator becomes excessive.

[0006] Second, in a method of smoothing a control signal output from a phase comparison circuit by a low-pass filter (LPF), which has been conventionally performed to solve the first problem described above, suppression of a jitter component is performed. Is possible, but the frequency stabilization time becomes longer. The reason is that the smoothing of the control signal makes the control over the oscillator modest.
This is because the sensitivity of LL decreases.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a variable frequency PLL circuit capable of obtaining a stable output clock with a short frequency stabilization time and low jitter.

[0008]

According to the present invention, a frequency variable type P according to the present invention is provided.
The LL circuit includes a phase comparison circuit and a VCO whose oscillation frequency is controlled by an output control signal from the phase comparison circuit. The input signal and the output signal of the VCO are input through frequency dividers, respectively, and the comparison signal is phase-converted. In the PLL circuit input to the comparison circuit, the frequency divider includes a plurality of frequency division circuits having different division ratios, and inputs a comparison signal to the phase comparison circuit via a selector for selecting the plurality of frequency division circuits. .

Further, according to a preferred embodiment of the frequency variable PLL circuit of the present invention, the selector sets the frequency dividing ratio of the frequency dividing circuit so as to increase the comparison frequency in an asynchronous state and decrease the comparison frequency in an asynchronous state. . The selector is controlled based on a jitter detection signal from a jitter detection circuit that detects jitter of a reference signal output from the VCO. The selector is controlled by a frequency division ratio selection signal generated based on the jitter detection signal and the synchronization detection signal from the phase comparison circuit. A frequency division ratio selection signal is generated by a selector to which the jitter detection signal is input and a logic gate to which the output signal of the selector and the synchronization detection signal are input.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a frequency variable PLL circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a frequency variable PLL circuit according to the present invention. The PLL circuit 10 includes frequency dividers 11 and 12, selectors 13 and 14, a phase detector 15, and a VCO 16. Here, the frequency divider 11 includes a plurality of frequency dividing circuits A
1 to An. Similarly, the frequency divider 12 also includes a plurality of frequency dividing circuits B1 to Bn. An input signal is input to each of the frequency dividing circuits B1 to Bn of the frequency divider 12. On the other hand, a reference signal which is an output signal of the VCO 16 is input to each of the frequency dividing circuits A1 to An of the frequency divider 11 and the phase comparator 15. The output signals of the frequency dividers A1 to An of the frequency divider 11 are
The signal is selected by the selector 13 and input to the phase detector 15 as the comparison signal A. Similarly, the output signals of the frequency dividers B1 to Bn of the frequency divider 12 are selected by the selector 14 and input to the phase comparator 15 as the comparison signal B. These selectors 13 and 14 are controlled by a frequency division ratio selection signal from the phase detector 15. The UP control signal and the DOWN control signal from the phase detector 15 are
6 is input.

The frequency divider 12 divides the frequency of the input signal by a plurality of frequency division ratios (n ways) and outputs it to the selector 14. The selector 14 controls the frequency divider 12 based on the frequency division ratio selection signal.
From the frequency divider circuits B1 to Bn are selected and input to the phase detector 15 as the comparison signal B. The divider 11 has V
The reference signal from the CO 10 is divided by a plurality of division ratios and output to the selector 13. The selector 13 selects signals from the frequency divider circuits A1 to An of the frequency divider 11 based on the frequency division ratio selection signal, and inputs the signals as the comparison signal A to the phase detector 15. Based on the phases of the comparison signal A and the comparison signal B and the jitter amount of the reference signal, the phase detector 15 controls an UP control signal and a DOWN control signal for controlling the VCO 16, and controls the selector 13 and the selector 14. A frequency division ratio selection signal is output. The VCO 16 includes a phase detector 15
An output signal and a reference signal are generated based on the control signal from the control unit.

As described above, the frequency divider 11 and the frequency divider 12
Has frequency dividing circuits A1 to An and B1 to Bn having a plurality of frequency dividing ratios from “1” to “n”. Since the frequency division ratio increases as the number increases, the number “1” is the lowest and the number “n” is the maximum. Therefore, the frequency dividing circuits A1 to A1
The frequency of the signals output from An and B1 to Bn is
The “1” number is the highest and the “n” number is the lowest.

Next, FIG. 3 shows the phase detector 1 shown in FIG.
5 is a block diagram showing a detailed configuration of No. 5. FIG. The phase detector 15 includes a phase comparison circuit 31, a jitter detection circuit 32, and a frequency division ratio selection circuit 33. Phase comparison circuit 3
1 receives the above-described comparison signal A and comparison signal B as inputs, and outputs an UP control signal, a DOWN control signal, and a synchronization detection signal. The reference signal from the VCO 16 is input to the jitter detection circuit 32. The jitter detection signal from the jitter detection circuit 32 is input to the frequency division ratio selection circuit 33 together with the synchronization detection signal from the phase comparison circuit 31. And
The division ratio selection circuit 33 generates a division ratio selection signal input to the selectors 13 and 14.

FIG. 4 is a block diagram showing a detailed configuration of the frequency division ratio selection circuit 33 shown in FIG. The frequency division ratio selection circuit 33 includes a selector 41 and a logic gate 42. The selector 4 of the frequency division ratio selection circuit 33
1 is supplied with a jitter detection signal.
Is output to the logic gate 42. Then, a division ratio selection signal is generated from the logic gate 42.

Prior to the description of the operation, the sensitivity characteristics of a general PLL circuit composed of the phase comparator 1, the VCO 2 and the frequency divider 3 will be described with reference to FIG. Here, assuming that the gain of the phase comparator 1 is Kp, the gain of the VCO 2 is Kv, the frequency division ratio of the frequency divider 3 is N, the transfer function of the PLL circuit is M, and the Laplace transform is s, the transfer function M of the PLL circuit is M
Is represented by the following equation. M = (Kp · Kv / N) / (s + (Kp · Kv / N)) That is, the gain (sensitivity) of the PLL circuit increases as the division ratio N decreases, and the PLL circuit increases as the division ratio N increases. Gain decreases.

Next, the phase comparison control operation of the frequency variable PLL circuit 10 shown in FIGS. 1, 3 and 4 will be described with reference to the flowchart of FIG. First, the phase of the comparison signal A and the phase of the comparison signal B are compared to monitor the synchronization state (step S1). In this step S1, these comparison signals A
When the comparison signal B is out of synchronization, the division ratio selection circuit 33 of the phase detector 15 sets the division ratio to the minimum value (0) (step S2). In the frequency variable PLL circuit 10 of FIG. 1, the frequency divider A1 of the frequency divider 11 and the frequency divider B1 of the frequency divider 12 are selected. Since the frequency of the signal input to the phase comparison circuit 31 increases as the frequency division ratio decreases, the sensitivity of the PLL circuit increases and the frequency stabilization time is shortened.

On the other hand, in a state where the frequency is stabilized and the comparison signal A and the comparison signal B are synchronized (step S1: synchronized state), the division ratio selection circuit 33 of the phase detector 15 increases the division ratio. By lowering the frequency of the signal input to the phase comparison circuit 31, the sensitivity of the PLL circuit is reduced, and jitter is suppressed. At this time, the jitter detection circuit 32 of the phase detector 15 observes the amount of jitter of the reference signal (Step S).
3). Then, the dividing ratio of the dividing ratio selection circuit 33 is varied according to the magnitude of the jitter. Specifically, when the jitter increases (step S3: large jitter), the frequency division ratio is increased and the frequency input to the phase comparison circuit 31 is reduced (step S6). In the frequency variable PLL circuit 10 of FIG. 1, the (n + 1) frequency divider of the frequency dividers 11 and 12 is selected. By increasing the frequency division ratio, the PLL
The sensitivity of the circuit is reduced, and the occurrence of jitter is suppressed. next,
The frequency division ratio n is determined (step S7). If n + 1 <n, the process returns to step S3 described above. Also, n + 1 =
In the case of n, the process returns to step S1 described above.

If the jitter is reduced in step S3 (step S3: small jitter),
The frequency division ratio is reduced, and the frequency input to the phase comparison circuit 31 is increased (step S4). Specifically, the frequency divider 1
The (n-1) frequency dividers 1 and 12 are selected. Then, the frequency division ratio is determined (step S5). If n> 1, the process returns to step S3 described above. If n = 1, the process returns to step S1 described above. By reducing the frequency division ratio, the sensitivity of the PLL circuit is increased, and the frequency stabilization time is shortened when the state of the PLL circuit becomes out of synchronization from the stable state.

As described above, in the phase detector 15 shown in FIG.
To generate an UP control signal, a DOWN control signal, and a synchronization detection signal. The jitter detection circuit 32 measures the amount of jitter of the reference signal output from the VCO 16 and outputs the jitter detection signal to the frequency division ratio selection circuit 33. Division ratio selection circuit 3
3 is when the PLL circuit is out of synchronization and is not stable.
The frequency division ratio is set to the minimum to stabilize the PLL circuit. PL
After the L circuit is stabilized, the frequency division ratio is increased based on the detection signal from the jitter detection circuit 32 to suppress the jitter.

Next, the operation of the phase detector 15 shown in FIG. 3 will be described with reference to the timing chart of FIG. FIG.
3, (a) to (e) show, as shown in FIG. 3, (a) a comparison signal A, (b) a comparison signal B, (c) a synchronization detection signal, and (d) a jitter detection signal. And (e) are frequency division ratio selection signals. In the asynchronous state, the frequency division ratio selection signal (e) is fixed to “1” in order to speed up the frequency stability.
In this case, since the frequency division ratio is minimum, the phase comparison circuit 31
Have the maximum frequency of the comparison signal A (a) and the comparison signal B (b). Upon transition to the synchronous state, the comparison frequency is selected based on the control signal from the jitter detection circuit 32 or the jitter detection signal (d). In the case of FIG. 5, "1" is selected as the frequency division ratio selection signal (e).

The frequency dividing ratio selection circuit 33 shown in FIG.
The selector 41 is controlled using the jitter detection signal (d) input from the jitter detection circuit 32 and the synchronization detection signal (c) input from the phase comparison circuit 31, and the logic gate 4 is controlled.
2, a frequency division ratio selection signal (e) is generated. The frequency division ratio selection signal (e) has a minimum value of “1” and always generates “0” when asynchronous. After synchronization is established, values from “1” to “n” are generated by the jitter detection signal (d).

The configuration and operation of the preferred embodiment of the frequency variable PLL circuit according to the present invention have been described above in detail. However, such embodiments are merely exemplary of the present invention,
It should be noted that the present invention is not limited in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0024]

As is evident from the above description, according to the frequency variable PLL circuit of the present invention, the following remarkable practical effects can be obtained. First, the stabilization time of the PLL circuit is reduced. The reason is that by increasing the phase comparison frequency, the sensitivity of the PLL circuit can be increased, and the frequency stabilization time is shortened.

Second, the jitter of the output signal can be suppressed.
The reason is that the frequency of the signal input to the phase comparison circuit is variable, so that after the PLL circuit is stabilized, P
This is because the sensitivity of the LL circuit can be reduced, and control in which jitter does not easily occur can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a preferred embodiment of a frequency variable PLL circuit according to the present invention.

FIG. 2 is a flowchart illustrating an operation of a phase detector of the variable frequency PLL circuit shown in FIG.

FIG. 3 is a block diagram showing a detailed configuration of a phase detector shown in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a frequency division ratio selection circuit shown in FIG. 3;

FIG. 5 is a timing chart illustrating the operation of the phase detector shown in FIG.

FIG. 6 is a diagram illustrating sensitivity characteristics of a typical PLL circuit.

FIG. 7 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 8 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 11, 12 frequency divider 13, 14, 41 selector 15 phase detector 16 voltage controlled oscillator (VCO) A1 to An, B1 to Bn frequency divider 31 phase comparator 32 jitter detector 33 frequency divider selector 42 logic gate

Claims (5)

[Claims] 1. A phase comparator and a voltage controlled oscillator (VCO) whose oscillation frequency is controlled by an output control signal from the phase comparator, and an input signal and an output signal of the VCO via a frequency divider, respectively. Wherein the frequency divider is provided with a plurality of frequency dividers having different frequency division ratios, and via a selector for selecting the plurality of frequency dividers. A frequency variable PLL circuit, wherein the comparison signal is input to the phase comparison circuit. 2. The frequency variable according to claim 1, wherein the selector sets the frequency division ratio of the frequency dividing circuit so as to increase the comparison frequency in an asynchronous state and decrease the comparison frequency in a synchronous state. Type PLL circuit. 3. The frequency variable PLL circuit according to claim 1, wherein said selector is controlled based on a jitter detection signal from a jitter detection circuit for detecting jitter of a reference signal output from said VCO. . 4. The frequency variable PLL circuit according to claim 3, wherein said selector is controlled by a frequency division ratio selection signal generated based on said jitter detection signal and said synchronization detection signal from said phase comparison circuit. 5. The frequency division ratio selection signal is generated by a selector to which the jitter detection signal is input, and a logic gate to which an output signal of the selector and the synchronization detection signal are input. Variable frequency type P described in 4.
LL circuit.